Elevated-Metal Metal-Oxide Thin-Film Transistors Based on Indium-Tin-Zinc Oxide

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1 Elevated-Metal Metal-Oxide Thin-Film Transistors Based on Indium-Tin-Zinc Oxide Zhihe XIA,2, Lei LU,2,3, Jiapeng LI,2, Zhuoqun FENG,2, Sunbin DENG,2, Sisi WANG,2, Hoi-Sing KWOK,2,3 and Man WONG*,2 Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology, Hong Kong 2 State Key Laboratory on Advanced Displays and Optoelectronics and Technologies, the Hong Kong University of Science and Technology, Hong Kong 3 Jockey Club Institute for Advanced Study, the Hong Kong University of Science and Technology, Hong Kong Abstract The elevated-metal metal-oxide (EMMO) thin-film transistor (TFT) architecture is based on the distinct effects of oxidizing thermal annealing on the properties of metal-oxide semiconductors under covers of different gas-permeability. EMMO TFTs based on indium-tin-zinc oxide as channel material are fabricated and characterized. Good performance metrics are obtained: a relatively higher field-effect mobility of 23.2±0.8 cm 2 /Vs, a width-normalized offstate current of at most A/µm, and robust stability against gate-bias stress. based on TC and 2TC designs based on λ = µm and W/L =, where W is the channel width.. Introduction Due to their relatively higher field-effect mobility (μfe) and process compatibility with that of the conventional amorphous silicon thin-film transistors (TFTs), metaloxide (MO) TFTs have recently emerged as promising candidates for the construction of active-matrix liquidcrystal displays (AMLCDs) and active-matrix organic light-emitting diode (AMOLED) displays,2. Based on the distinct effects of oxidizing thermal annealing on the properties of MO semiconducting thin films under covers of different gas-permeability, the elevated-metal metal-oxide (EMMO) TFT architecture with various MO semiconductors as active channel materials has been proposed 3 5. The EMMO architecture (Fig. a) offers channel protection during the definition of the source/drain (S/D) electrodes and the small device foot-print as in the respective conventional etch-stop (ES) and backchannel-etched (BCE) TFT architectures. Compared with the ES architecture (Fig. b), reductions of the minimum channel length (L) from 3λ to λ and the minimum gate length from 5λ to 3λ are possible with the EMMO architecture, where λ is the minimum lithography feature size. This leads to an obvious advantage for the realization of higher resolution displays. Shown in Figure 2 are the dependence of the aperture ratio on pixel density for EMMO and ES TFTs Figure. The cross-sectional schematics of (a) an EMMO and (b) an ES TFT. Figure 2. The aperture ratio versus the pixel density for backplanes based on ES and EMMO TFTs with W-to-

2 L ratio of and a design-rule of µm. As TFTs with a μfe of at least 6 cm 2 /Vs are needed to realize an 8k 4k AMOLED display driven at 20Hz 6, amorphous indium-tin-zinc oxide (ITZO) is a promising material to realize high resolution and high frame-rate displays because of its higher μfe >20 cm 2 /Vs 7,8. This is higher than the typical ~0 cm 2 /Vs offered by IGZO TFTs. Presently reported is the fabrication and characterization of EMMO TFTs with ITZO as the channel material. The resulting TFT exhibits good performance metrics: a relatively higher μfe of 23.2±0.8 cm 2 /Vs, an on/off current ratio over 0 0, a pseudo subthreshold slope (SS) of 65±5 mv/decade, a W-normalized off-state current of at most A/µm, and robust stability against gate-bias stress. 2. Experimental The fabrication of an EMMO TFT started with the sputter deposition and patterning of 20 nm-thick molybdenum (Mo) gate electrode (Fig. 3a) on an oxidized n-type silicon substrate. The gate dielectric consisted of 50-nm thick silicon nitride (SiNx) under 75- nm thick silicon oxide (SiOy), both formed at 300 C in a plasma-enhanced chemical vapor deposition (PECVD) system. (a) (b) (c) Metal Oxide Gate Dielectric Passivation Etch-stop Layer Metal Oxide Gate Dielectric layer and contact hole opening. (d) Completed the EMMO TFTs. A 30 nm-thick ITZO active layer was subsequently deposited at room temperature by co-sputtering of ZnO and ITZO in a radio-frequency magnetron sputtering machine at a process pressure of 3 mtorr in a mixed atmosphere of oxygen (O2) and argon. The molar ratio of the ITZO target was In2O3:SnO2:ZnO = 35:35:30 and the base pressure was ~ Torr. The active layer was patterned using /2000 molar aqueous hydrofluoric acid solution (Fig. 3b), before a 300 nmthick SiOy passivation layer was deposited in the same PECVD system. Following a thermal treatment at 300 C for 2 hrs in an O2 atmosphere, contact holes (Fig. 3c) were opened in an inductively coupled plasma etcher running a sulfur hexafluoride chemistry. The S/D electrodes were made of sputtered and patterned stacks of 300-nm thick aluminum (Al) on 50-nm thick Mo. The overlap (Fig. 3d) between each end of the gate electrode and the corresponding S/D electrode was 4 μm. Finally, conductive S/D regions were formed using a thermal treatment at 400 C in O2 for 4 hrs. The TFTs were electrically characterized at room temperature using an Agilent 456C Semiconductor Parameter Analyzer. 3. Results and Discussion Shown in Figure 4 is the transfer curves of EMMO ITZO TFT before and after the 400 C thermal annealing process. Since there is no overlap between the metal S/D contacts and the bottom gate electrode (Fig. 3d), the on-current of the EMMO ITZO TFT before the thermal annealing process is limited by the highly resistive and un-gated active regions. (d) Source Metal L Metal Passivation Etch-stop Layer MO n + Gate Dielectric n + Drain Figure 3. The cross-sectional fabrication process flow of the EMMO TFTs. (a) Gate electrode formation. (b) Active channel Patterning. (c) Passivation etch-stop

3 voltage (Vg) transfer characteristics of EMMO TFTs with different L but the same W of 00 µm at Vd of 5V. A µfe ( Lgm/WCiVd) of 23.2±0.8 cm 2 /Vs was extracted from the maximum trans-conductance (gm) at the low Vd of 0.5 V, where Ci is the gate capacitance per unit area. An SS of 65±5 mv/decade was extracted from the minimum value of logid/ Vg when Vg is larger than the turn-on voltage Von ( Vg to induce an Id of L/W 0 na at Vd=5 V) of.2 V. The off-state current is limited by the noise level of ~5 0-4 A of the Analyzer. Consequently for a TFT with W/L = 20, an on/off current ratio of no smaller than 0 0 was estimated. Annealing Time On current (A) Off Current (A) V on (V) 0 hours.37e-7 5.3E hours.04e-4.3e hours.04e-4.34e Figure 4. The transfer curves of EMMO ITZO TFT with and without the thermal annealing process. After the annealing, donor-defects are formed in ITZO underneath the impermeable S/D electrodes 9,0. This results in the formation of the conductive S/D regions (highlighted in red in the device cross-section shown in Fig. 3d), leading to significantly improved oncurrent summarized in Table.. Though the S/D activation process could be achieved with 2 hours of annealing, the turn-on voltage is more positive for a TFT subjected to a 4-hr annealing process, due to the more complete oxidation of the active channel region. Figure 5. The transfer characteristics of EMMO ITZO TFTs via different L with the same W = 00 µm at Vd =5 V. Shown in Figure 6 are the transfer characteristics with different Vd of a TFT with a large W/L of 0 5 µm /0 µm. The device, the layout of which is shown in the Inset, was fabricated for a more accurate estimation of the off-state leakage current as the large W to L ratio could amplify the off-state current. From the noiselimited off-state current of ~ A, a W- normalized off-state current of no larger than A/μm was estimated. Hysteresis was negligible, as illustrated by the excellent overlap of the transfer characteristics resulting from both forward and reverse Vg sweeps. Table. the electronic parameters of EMMO ITZO TFTs with different annealing conditions. (Vd=5V) Shown in Figure 5 are the drain current (Id) vs. gate

(P/NBS). At room temperature, the evolution of the respective transfer characteristics with the stress time is shown in Figures 7a and 7b. Shifts in Von of ~ 0.5V for PBS and ~+0.

4 Figure 6. The transfer characteristics of a wide EMMO ITZO TFT with W of 0 5 µm. Shown in the Inset is the part of layout of the large W/L device. The gate bias stress-induced instability of the EMMO TFTs at different temperature were characterized, with respective Vg of (Von + 20) V and (Von 20) V for positive and the negative bias stress (P/NBS). At room temperature, the evolution of the respective transfer characteristics with the stress time is shown in Figures 7a and 7b. Shifts in Von of ~ 0.5V for PBS and ~+0.5V for NBS were obtained after 0 4 s of stress. These are considered negligible as they are equal in magnitude to the Vg step of 0.5V used during the measurement. Positive and negative gate-bias temperature stress (PBTS/NBTS) were also carried out at 60 C. Shifts in Von of ~.8V for PBTS and ~+0.6V for NBTS were obtained after 0 4 s of stress, as shown in Figures 7c and 7d. Figure 7. The time evolution of the transfer characteristics of EMMO ITZO TFTs subjected to (a) PBS and (b) NBS with Vg of Von±20 V and (c) PBTS and (d) NBTS with Vg of Von±20 V at temperature of Conclusion EMMO TFTs with ITZO as the channel material have been realized and characterized. Good performance metrics were obtained: such as transfer characteristics free of hysteresis, high on/off current ratio and a low width-normalized off-state leakage current of no more than A/μm. Stability against gate-bias stress has also been demonstrated. Reference K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M.

5 Hirano, and H. Hosono, Nature 432, 488 (2004). 2 E. Fortunato, P. Barquinha, and R. Martins, Adv. Mater. 24, 2945 (202). 3 L. Lu, J. Li, Z.Q. Feng, H.-S. Kwok, and M. Wong, IEEE Electron Device Lett. 37, 728 (206). 4 Z. Xia, L. Lu, J. Li, Z. Feng, S. Deng, S. Wang, H.S. Kwok, and M. Wong, IEEE Electron Device Lett. 38, 894 (207). 5 L. Lu, J. Li, H.S. Kwok, and M. Wong, Tech. Dig. - Int. Electron Devices Meet. IEDM (207). 6 T. Arai, J. Soc. Inf. Disp. 20, 56 (202). 7 T. Arai and T. Sasaoka, SID Symp. Dig. Tech. Pap. 42, 70 (20). 8 T. Sun, L. Shi, C. Su, W. Li, X. Lv, H. Zhang, Y. Meng, W. Shi, S. Ge, C. Tseng, Y. Wang, and C. Lo, 766 (205). 9 L. Lu and M. Wong, IEEE Trans. Electron Devices 62, 574 (205). 0 L. Lu and M. Wong, IEEE Trans. Electron Devices 6, 077 (204). K. Kato, Y. Shionoiri, Y. Sekine, K. Furutani, T. Hatano, T. Aoki, M. Sasaki, H. Tomatsu, J. Koyama, and S. Yamazaki, Jpn. J. Appl. Phys. 5, 220 (202).

Study on the hydrogenated ZnO-based thin film transistors

Final Report Study on the hydrogenated ZnO-based thin film transistors To Dr. Gregg Jessen Asian Office of Aerospace Research & Development April 30th, 2011 Jae-Hyung Jang School of Information and Communications