Resistive-switching memory

Transcription

1 Resistive-switching memory Daniele Ielmini DEI - Politecnico di Milano, Milano, Italy ielmini@elet.polimi.it Flash scaling overview 1. Flash scaling: 2. Evolutionary scenario: T. Kamaigaichi, et al., IEDM Tech. Dig H. Tanaka et al., VLSI Symp Paradigm shift M. Lee, et al., IEDM Tech. Dig Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 2 1

2 Outline Introduction RRAM concept Unipolar switching NiO Set/reset mechanisms Reliability Bipolar switching Analog switching and memristors Conclusions Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 3 Resistive-switching memory (RRAM) First observation in the 1960s [J.G. Simmons and R.R. Verderber, The Radio and Electronic Engineer, 81 (1967)] Recently many reports about RRAM: W. W. Zhuang et al., IEDM02 (Sony) I. Baek et al., IEDM04 (Samsung) IEDM05 09: about 30 contributions on RRAM Resistive memories offer the potential for 4F 2 cross-bar memory cell highly attractive for mass-storage application Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 4 2

3 RRAM types Set Reset - + Set Reset + - Set Reset Unipolar Bipolar Bipolar/analog (filamentary) (filamentary) (interface) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 5 RRAM vs. PCM PCM = bulk physical transition agst cgst F. Pellizzer, EPCOS 2007 D. Tio Castro, et al., IEDM 2007 RRAM = localized chemical transition A. Sawa, Materials Today 2008 Yun et al., Phys. Stat. Sol Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 6 3

4 Unipolar switching: materials Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 7 NiO properties E A = 0.4 ev 1. Reset state = crystalline state 2. Poole-Frenkel transport in the as deposited state Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 8 4

5 Conductive filament (CF) Current [ma] RRAM concept Top Electrode NiO Bottom Electrode Low R Set state V reset, I reset reset High R Reset state Reset operation Set operation Pt/NiO/Pt 0.5 set V set, I set Voltage [V] 200 nm Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 NiO W Joule heating + Ni thermal oxidation Pt Threshold switching + NiO reduction (D. Ielmini et al., APL 2009) 9 Reset simulation in NiO RRAM CF edge U. Russo, et al., IEEE T-ED 2009 Mar. 2, 2010 D. Ielmini, "Non volatile memories"

6 T-dependent reset P reset = V I = cell cell T T R th 0 Tcrit = 530 K Rth = 8x10 4 K/W U. Russo, et al., IEDM Tech. Dig Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 11 Set transition V A V cell R L RRAM Vcell [V] (a) Reset state Set state Time [ns] Permanent drop of voltage indicates change of state set transition Mar. 2, 2010 D. Ielmini, "Non volatile memories"

7 Role of threshold switching V A V cell R L RRAM Vcell [V] (b) Switching Recovery D. Ielmini et al., APL Time [ns] Transient drop of voltage indicates threshold switching set transition is triggered by electrical threshold switching Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 13 Interpretation: threshold switching Current Set VT, IT Voltage Threshold switching triggers current overshoot and local extremely high temperature/high current densities reduction How can heating result in either reduction (set) or oxidation (reset)? Mar. 2, 2010 D. Ielmini, "Non volatile memories"

8 Ellingham diagram Standard free energy of formation of oxide: M + O 2 = MO 2 G < 0 drives oxidation G > 0 drives reduction Reset: heating decreases G but enhances reaction/diffusion kinetic Set: sudden nonequilibrium heating which drives local reduction Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 15 Scaling the reset current T = T + R R I 2 crit 0 th el reset T - T A crit 0 I reset = R el R th h PCM: A h A F h F Ireset 2 F RRAM: A h A non scaling Ireset 1 h Mar. 2, 2010 D. Ielmini, "Non volatile memories"

9 Area dependence Current [A] Forming Reset Set Current [ma] φ=80nm 70nm 60nm 50nm 40nm I reset [ma] φ [nm] Cell size [µm 2 ] Voltage [V] Russo et al., IEDM 2007 Cell-area independence Filament area dependence Mar. 2, 2010 D. Ielmini, "Non volatile memories" T-1R experiments I(µA) Reset Set Forming R [Ω] I reset [A] This work [5] [7] [8] [9] (a) (b) V_topelectrode_NiOcell (V) I D [A] Mar. 2, 2010 D. Ielmini, "Non volatile memories"

10 Multilevel cell (MLC) operation Current [µa] I reset = 9.5 µa 4.5 µa 3.5 µa 2 µa Voltage [V] Current [ma] Voltage [V] Partial set Partial reset Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 19 V reset [V] I reset [A] a b I reset scaling Partial reset Partial set Calculated R [Ω] I reset scaling demonstrated, what about reliability? Mar. 2, 2010 D. Ielmini, "Non volatile memories"

11 Data loss mechanism Φ Set Reset Data loss = T-activated oxidation of the metallic CF Statistical spread study on 50 samples Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 21 Resistance dependence τ R [s] E AR = 0.92 ev T [ o C] R < 200 Ω 200 Ω < R < 10 3 Ω R > 10 3 Ω ev 1.02 ev f = 90% /kT [ev -1 ] Cells at higher R display faster data loss size-dependent CF oxidation Mar. 2, 2010 D. Ielmini, "Non volatile memories" R

12 Random telegraph noise (RTN) TE R [Ω] R Trap Trap BE (a) (b) Voltage [V] 10 0 c λ = εkt q n D 2 R/R R[Ω] 23 Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 Oxide RRAM: bipolar switching ZrO 2 Cu 2 O SrZnO 3 TiO 2 Possible mechanism = metal ion drift and electro-deposition Mar. 2, 2010 D. Ielmini, "Non volatile memories"

13 Electrolyte-based RRAM Conductive bridging RAM (CBRAM, Infineon) Programmable metallization cell (PMC, ASU) Concept = electrochemical deposition/retraction of metallic nano-bridges in solid electrolytes Silver or copper can be added to a variety of glasses to form good solid electrolytes Ge-Se, Ge-S, WO 3, SiO 2 (!) glasses can incorporate many tens of atomic % of metal ternaries can have high ion mobility (up to 10-2 cm2/vs) but relatively high resistivity (> 10 2 Ωcm) Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 25 Programming mechanism e- + Metallic electrodeposit low resistance Glassy electrolyte high resistance M M+ + e- M+ + e- M e- Reverse bias dissolves electrodeposit Silver/copper electrode Bias > write threshold Tungsten electrode Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 26 Ion current - MASS FLOW 13

14 Ag bridge Ag Ag ~60 nm Ag-Ge-Se electrolyte Ag filament Unwritten Written Large area (5 µm x 5 µm) device over-written to produce multiple electrodeposits and sectioned using FIB Evidence of multiple nucleation sites on W cathode Deposits continue to grow during analysis Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 27 The mysterious memristor Memristor = charge controlled resistance, based on the seminal work by Chua in 1971 Only qualitative analogy (original memristor links charge and magnetic flux) Mar. 2, 2010 D. Ielmini, "Non volatile memories"

15 HP memristor model Two regions with different doping, e.g. TiO 2 (high resistance R OFF ) and TiO x (low resistance R ON because of V O 2+ ) Bias application the doped/undoped boundary w(t) shifts: Drift velocity given by dw/dt = µ v F = µ v R ON i/d, thus: Substitution yields memristance v/i: Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 29 Dopant = oxygen vacancy V O 2+ Insulating TiO 2 + lowresistivity TiO 2-x reduced oxidized V O 2+ drift toward the cathode: TiO 2 reduction lowers resistance (n doping by V O 2+ ) while TiO 2-x is not majorly affected by oxidation Series model as opposed to parallel model in filamentary switching (e.g. NiO) Experimental evidence for TiO2-TiO2-x model? Mar. 2, 2010 D. Ielmini, "Non volatile memories"

16 V O 2+ migration model V>0 V O 2+ drift out of TiO 2 R down V>0 V O 2+ drift into TiO 2 R up Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 31 Rectification polarity Mar. 2, 2010 D. Ielmini, "Non volatile memories"

17 Memristive perovskytes M. Hasan, et al., APL 92, (2008) LaCaMnO (LCMO) and PrCaMnO (PCMO) display analog (no sudden current jumps) and uniform (area dependent) switching good for memory scaling Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 33 Model: interface switching Mar. 2, 2010 D. Ielmini, "Non volatile memories"

18 Area and I reset scaling Area scaling without any particular control of set results in I reset reduction 15 µa/(50nm) 2 = 0.6 MAcm -2 Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 35 Memristors as artificial synapses As voltage/current/time results in resistance change in a memristor, interaction between pre/post synaptic neurons yields potentiation/depression of a synapse Mar. 2, 2010 D. Ielmini, "Non volatile memories"

19 Hebbian rule Neurons that fire together, wire together Spike-timingdependent potentiation (STDP) at the basis of synapses plasticity or learning Idea is to use analog RRAM (or memristors) as artificial synapses in neural networks Mar. 2, 2010 D. Ielmini, "Non volatile memories" 4 37 Conclusions Unipolar RRAM compatible with diodeselected crossbar Filamentary RRAM most extendedly studied, critical tradeoff between reset current and reliability Analog switching is promising for scalable I reset in memory and artificial synapses Mar. 2, 2010 D. Ielmini, "Non volatile memories"