High Speed Serial Link (HSSL) Channel Modeling. CST workshop series 2010 February 10 1

Transcription

1 High Speed Serial Link (HSSL) Channel Modeling CST workshop series 2010 February 10 1

2 Outline Introduction HSSL design workflow Creating a HSSL model Simulating a HSSL HSSL modeling example CST workshop series 2010 February 10 2

3 Introduction The challenge: Send a data stream from a Tx to a Rx at a given data rate while meeting voltage and timing constraints (eye height and width) Tx Copper traces Main interconnect Multilayer PCB Vref Rx en Tx On-package interconnect - Escape - Main TL On-package vias -PTH -uvias On-board interconnect -MS -SL On-board vias -blind -buried Pkg. to board transition (socket) Rx CST workshop series 2010 February 10 3

4 Introduction Signal integrity issues and considerations: Dielectric Losses Copper Roughness Skin Effect Parasitic modes Signal Degradation Radiation Cross-talk Reflections Need modeling tools which account for physical effects in order to make realistic predictions, 3D Field Full Wave simulators a must Accurate models needed for accurate predictions CST MWS, Full wave physics and accuracy requirements CST workshop series 2010 February 10 4

5 HSSL analysis workflow Workflow and integration Pre and post layout analysis Time and frequency domain solutions S-parameters, Crosstalk analysis, TDR, Eye diagrams Performance SPICE models extraction Circuit EM co-simulation Full channel characterization IBIS and non-linear models CST workshop series 2010 February 10 5

6 HSSL analysis workflow: Pre-layout Approach: Build and cascade segmented models High Speed connector Diff. Pkg. vertical transition Import model from CAD tool if available Create 3D model using MWS s powerful GUI Simulate using Time or Frequency domain solver Create an S-parameter model Synthesize an equivalent circuit using MOR CST workshop series 2010 February 10 6 Socket model

7 HSSL analysis workflow: Pre-layout Design of package and PCB vias plays an important role Standard method: Edit and extract from Layout - Time consuming - Lack of parameterization CST Via Wizard Macro enabled Spreadsheet based High flexibility Full parameterization Automatic port definition CST workshop series 2010 February 10 7

8 HSSL analysis workflow: Pre-layout Cascading the segmented models in CST DESIGN STUDIO: CST MWS TS TS CST DS (coupled SL) TS At pre-layout stage, common approach is to use 2D models for main High speed interconnect (SL, MS) Excellent approach for analysis of interconnect length and data rate scalability Straightforward cascading of segmented models Multiple formats supported (Spice, HSpice, TS, etc.) Transient or Frequency domain simulators Active (IBIS, Spice Netlist, etc.) and passive components Optimization/parameter sweep Co-simulation with CST MWS Included with standard license CST workshop series 2010 February 10 8

9 HSSL analysis workflow: Post-layout A segmented model approach is also a common practice: Extract vias and high speed interconnect models from layout database CST MWS and EDA links 1. Cadence Allegro ( *.brd, *.mcm) 2. Mentor Graphic ( Expedition and Board Station) 3. Zuken 4. ODB++ 5. Gerber ( single/multiple layer) 6. Dxf ( import/export) Self cleaning process Pre-mesh definition Discrete components Stack-up definition Materials definition CST workshop series 2010 February 10 9

10 Powerful EDA interface Customized extraction Area selection Net selection + surrounding area CST workshop series 2010 February 10 10

11 Easy Merging of imported components PCB + package uvw on specific net CST workshop series 2010 February 10 11

12 Post-Layout: Pkg+PCB channel Large HSSL channel modeling example Time domain solver Fast and memory efficient, enables large model simulations High performance computing options available (GPU, MPI, DC) Single vs. multiple simulations and cascading CST workshop series 2010 February 10 12

13 Simulating a High Speed Serial Link Frequency domain simulation SE/Mixed-mode converter RL IL Next Fext CST workshop series 2010 February 10 13

14 Simulating a High Speed Serial Link Time domain simulation Next CST workshop series 2010 February Fext

15 Simulating a High Speed Serial Link Time domain simulation (Eye Diagram calculation) Tx Channel Rx CST workshop series 2010 February 10 15

16 Demo: Chip-to-chip communication Segmentation lines Main interconnect (SL) PCB Via 2 Package 1 PCB Via 1 Package 2 Package Details PCB Transition Details CST workshop series 2010 February 10 16

17 Realistic Example: Package 2 Package 1 CST workshop series 2010 February layer PCB: FR4 Package1: 12-layer organic Package2: 21-layer ceramic

18 Structure of the Entire Channel Pkg 1 PCB Interconnect AC Caps Pkg 2 CST workshop series 2010 February 10 18

19 High-Speed Channel Modeling and Correlation Package 1 modeling Package 2 modeling PCB modeling Entire channel modeling Measurement and correlation CST workshop series 2010 February 10 19

20 Modeling Package 1 CST Links Automatic CST-Cadence Translator A section of the package is extracted via CST Links CST workshop series 2010 February Package details

21 Modeling Package 1 (Cont d) Package top port2 port4 Package interconnect port1 port3 Details of package 1 simulated net and port definition CST workshop series 2010 February Package vertical transition

22 Package 1: Simulation Results in output Simulation approach: TD based on Finite Integration Technique Excite each port with a Gaussian signal with spectral content of interest (40GHz) Capture time signatures at each port Fourier transform to obtain S-parameters NEXT FEXT Run-time statistics: Mesh cells 5.5M Simulation 8h (with GPU) time Memory usage 12GB 32h (no GPU) CST workshop series 2010 February 10 22

23 Modeling Package 2 Net extracted via CST Links WG ports details: Bottom Top Extrude signal and GND pads CST workshop series 2010 February 10 23

24 Simulated Differential S-Parameters - Very low differential Insertion Loss (~7dB at 40GHz) CST workshop series 2010 February 10 24

25 Modeling the Entire Channel 1 2 Model 1 (P1) Model 2 (PCB) Model 3 (P2) 3 4 Simulated Single-Ended S-Parameters CST workshop series 2010 February 10 25

26 Measurement Setup for the Entire Channel Probe 1 300um pitch probe Package1 Package2 200um pitch probe Probe 3 CST workshop series 2010 February 10 26

27 Comparison between Simulation and Measurement Simulation Measurement Very good correlation between simulation and measurement CST workshop series 2010 February 10 27

28 Conclusions A workflow for the design of HSSL was presented Powerful integration between CST MWS and CST DS Pre- and post- layout capabilities discussed CST MWS provides fast and accurate characterization of HSSL passive component CST DS enables full HSSL link simulation A practical example was presented CST workshop series 2010 February 10 28