Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques

Transcription

1 Microelectronics Reliability 47 (2007) Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques D.C. Moschou a, *, M.A. Exarchos b, D.N. Kouvatsos a, G.J. Papaioannou b, A.T. Voutsas c a Institute of Microelectronics, NCSR Demokritos, Agia Paraskevi 15310, Greece b Physics Department, National and Kapodistrian University of Athens, Athens 15784, Greece c LCD Process Technology Laboratory, Sharp Labs of America, 5700 NM Pacific Rim Blvd, WA 98607, USA Received 9 July 2007 Available online 24 August 2007 Abstract SLS ELA polysilicon TFTs fabricated in films crystallized with several novel techniques, yielding different film microstructure and texture, were investigated. The parameter statistics indicate that the TFT performance depends on film quality and asperities, in conjunction with the grain boundary trap density. The drain current transients, upon TFT switch from OFF to ON state, showed gate oxide polarization, related to film asperities and also confirmed the presence of extended defects in the TFTs of small mobilities. DC hot carrier stress was applied, indicating a reliability dependence on polysilicon structure and differences in degradation mechanisms for the various TFT technologies. Ó 2007 Elsevier Ltd. All rights reserved. 1. Introduction Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics, VLSI technology and high performance flat panel display applications [1]. The primary advantage of polysilicon TFTs over a:si ones is their higher field-effect mobility and consequently higher drive current. High reliability should also be achieved for the fabrication of commercial products to be possible. With the recent polysilicon crystallization process breakthroughs, using various excimer laser anneal (ELA) methods such as sequential lateral solidification (SLS), the TFT performance has substantially increased [2 6]. The several variations of the SLS technique allow the manufacturing of polysilicon films with excellent intragrain quality and grains of different geometry. The performance and reliability of the devices fabricated on SLS polysilicon depend on this specific microstructure of the polysilicon film [7]. * Corresponding author. Tel.: ; fax: address: dmoschou@imel.demokritos.gr (D.C. Moschou). 2. Experimental The TFTs studied were fabricated in 50 nm thick polysilicon films, formed by ELA crystallization of a:si, using the SLS technique. The procedure is conducted at room temperature by scanning samples under an appropriately mask-shaped laser beam generated by a LPX 315i Lambda Physik excimer laser (XeCl, 308 nm, discharge frequency 150 Hz) system. For our 2-shot samples, a large beam is shaped into two columns, slightly offset from each other, each with a set of parallel slits. The substrate is moved by a distance equal to the column width after each laser discharge (shot). The whole beam area is crystallized in 2 shots; lateral growth now occurs perpendicularly to the substrate motion, yielding 2-shot polysilicon films, which have rectangular shaped crystal domains that inevitably include point and planar defects. Another variation of this procedure is the one termed 2 N -shot, where the laser beam is divided in a number of regions with sets of slits orthogonal to each other. Half of the N regions are oriented in the x direction and half in the y one, slightly offset, with the substrate moving by /$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi: /j.microrel

2 D.C. Moschou et al. / Microelectronics Reliability 47 (2007) a region width after each shot. With increasing N, the number of times a spot on the film is irradiated increases, yielding progressively more refined material (at the cost of decreasing throughput). This advanced crystallization technique results in grains with excellent internal crystalline quality and engineered shapes, again rectangular with one direction more elongated. In this work, TFTs in 2 6 -shot (i.e., with N = 6) polysilicon films have been investigated. In the procedure called M N, the mask consists again of sets of slits orthogonal to each other. The grains grow first in the y direction (via the M patterns) and, then, sub-boundaries within these grains are swept in the x direction (via the N patterns), which is therefore the preferential direction. The difference of this procedure with the 2 N -shot one is that in the latter case one set of the slits irradiates the same region, and so does not contribute to lateral growth, but improves the intragrain quality. On the contrary, in the M N procedure all of the sets contribute to the lateral growth, advancing the lateral growth front. This results in larger domain sizes but of lower intragrain quality. There are also procedures where the masks consist of arrays of dots rather than slits. This way, the lateral growth of the film begins from the dots and progresses radially, resulting in the presence of grain boundaries within the crystal domain. In this case, the dot spacing is what defines the extent of the lateral growth. When the dots are arranged in a tetragonal matrix we get square domains, whereas when they are arranged in a hexagonal matrix we get hexagonal ones. The TFTs had a non-self-aligned top-metal-gate structure and a PECVD SiO 2 gate dielectric, with channel widths ranging from W =2lmtoW = 200 lm and lengths from L = 0.5 lm tol = 2lm. The TFTs were characterized and stressed using a HP4140B semiconductor analyzer. SIMOX transistors of the same dimensions were characterized and stressed as reference. The I ds V gs transfer characteristics were taken at room temperature, for V gs sweeps of 5 V to +5 V, with V ds of 0.1 V. The slope of the I ds V gs curve, in linear scale, yields the transconductance G m at any V gs value, with its maximum G m,max obtained at V gs,max. The intercept, with the horizontal axis, of a straight line with a slope of G m,max, fitted to the I ds V gs characteristic at V gs = V gs,max, yielded the corresponding extrapolated threshold voltage V th. The subthreshold swing S was extracted from the maximum slope of the same I ds V gs characteristic drawn in semilog scale. Also, we applied Levinson analysis [8] to calculate the grain-boundary trap densities of the TFTs. This can be done for our devices since the intragrain quality is very high, approaching the single-crystal quality described by the Levinson equation. The drain current transients upon application of gate bias pulses, when unstressed TFTs are switched from OFF to ON state, are also investigated. A DC hot carrier stress (V gs, V ds ) of (5V, 10 V) (approaching maximum degradation condition) was applied for a maximum duration of 16 h, for TFTs fabricated in the preferential direction of all of the above described polysilicon films. The I ds V gs curves were taken at each stressing time and the device parameters were extracted. 3. Results and discussion 3.1. Device characteristics Firstly we tried to probe the nature of the polysilicon surface for each crystallization technique by acquiring AFM images of the samples. As we can see in Fig. 1, in the film with the best intragrain quality, due to the larger number of irradiations in the same region, we observe an increased number of high protrusions. The height of the protrusions becomes significantly smaller for the 2-shot film. In the M N and Dot films we again observe very high protrusions, of the same scale as those of the 2 6 -shot one. However, these asperities are more sparsely distributed within the film surface. So sparsely, in fact, that the chance of an asperity to be included within a device is minimal. In Table 1 we can see the average values of the threshold voltage V th, the field-effect mobility l, the subthreshold slope S and the grain-boundary trap density N t as obtained by Levinson analysis of the measured TFTs. We examined two different variations of the Dot technology and three different variations of the M N one, the only differences being (i) for the Dot technologies, the hexagonal dot matrix for the 30 HEX samples vs. the square dot matrix for 50 SQ ones, and (ii) for the M N technologies, the crystal domain size. As far as S is concerned, we can see that it appears to be increased for the samples having an increased N t value, Fig. 1. Atomic force microscopy (AFM) pictures of polysilicon films.

3 1380 D.C. Moschou et al. / Microelectronics Reliability 47 (2007) Table 1 Device parameter statistics V th (V) l (cm 2 /V sec) S (mv/decade) N t (cm 2 ) Mean STD Mean STD Mean STD Mean STD SIMOX Shot Shot Dot 30HEX SQ M N # # # with the sole exception of the Dot TFTs, where we would normally expect it to be higher, since it has the worst polycrystalline quality. This can be explained if we consider the effect of what kind of traps is reflected on each parameter. We know that the N t value extracted by Levinson analysis is a measure of the global density of grain-boundary traps within the polysilicon film, while through S midgap traps, mainly located in intragrain areas, can be probed. Therefore, the small S value of the Dot TFTs, considering the rather increased N t, can be attributed to more tail-states existing for that technology than midgap ones. So, comparing the mean l value of the TFTs crystallized with different technologies, we can see that the largest mobility values, approaching the single crystalline reference one of SIMOX, are obtained for M N TFTs, followed closely by 2-shot and then by 2 6 -shot and Dot ones. This order of these different technologies with decreasing mobility can be attributed to two factors: the grain-boundary trap density and the surface roughness. The first can be probed through the value of the Levinson extracted N t and the second by considering the previous observations on the AFM images of the polysilicon films. Considering these two factors, we see that the M N TFTs, having the largest mobility values, indeed have the lower N t of all and, at the same time, the less pronounced surface roughness. The next lowest value of N t is that for the 2 6 -shot sample, showing its very good polysilicon quality, also observed from the SEM image. Nevertheless, its mobility is lower than that of the 2-shot sample, having a smaller N t. This is because of the extremely pronounced roughness observed in the 2 6 -shot sample, as compared to the 2-shot one. Finally, the Dot TFTs having the largest N t, despite their small surface roughness, exhibit the smallest mobilities of all devices. Therefore, the small N t value is essential to obtain large field-effect mobility, but the effect of surface roughness should not be neglected, since it can substantially degrade the performance of a TFT. These two factors play an essential role also for TFT drain current transient analysis. In Fig. 2, the switch-on drain current transients exhibit a complex behavior, where overshoot and undershoot effects coexist. The switch-on overshoot behavior has been investigated in depth [9 13]. It has been shown that switch-on overshoot transients Fig. 2. Drain current transients of M N TFTs with W/L = 8 lm/2 lm. The ON-state bias value was 2.9 V and the; OFF-state bias value was 1.1 V. The OFF-state duration was 100 msec. relax through stretched exponential law [14] described by following equation: DI d ðt Þ¼DI d ð0þ exp½ ðt=sþ b Š s ¼ s 0 expðe A =kt Þ where DI d (T) is the drain current transient, DI d (0) the drain current transient at t =0, s the relaxation time and b the stretch exponential factor (0 6 b 6 1). The factor b stands for the complexity of the process through which the transient relaxes. The relaxation time s represents a thermally activated mechanism with a corresponding activation energy E A, described by Eq. (2). For infinite temperature relaxation time s equals s 0. Both s and s 0 are determined by Arrhenius plot. The relaxation process takes place through trapping/detrapping states lying deep inside the polysilicon energy gap [14]. The switch-on undershoot behavior is more complex and has not been elucidated so far. For the 2 6 -shot TFTs, switch-on undershoot transients follow a stretched exponential law satisfactorily (1). In this case, the undershoot effect results from mobile charge displacement in the gate oxide, that is, a gate oxide polarization phenomenon [15]. This is not the case for 2-shot and M N#8 TFTs, where ð1þ ð2þ

4 D.C. Moschou et al. / Microelectronics Reliability 47 (2007) a double stretched exponential law (3) seems to be the one followed: DI d ðt Þ¼DI d ð0þ 1 exp½ ðt=s 1 Þ b1 ŠþDI d ð0þ 2 exp½ ðt=s 2 Þ b2 Š ð3þ As far as 2-shot TFTs are concerned, the double stretched exponential law (3) was implemented with excellent fitting results for both switch-on overshoot and switch-on undershoot transients, covering the temperature range of K. The fitting analysis revealed that there is a prevailing mechanism governing drain current transient behavior. This mechanism is thermally activated, represented by a relaxation time s and activation energy E A = ev (Fig. 3). Taking into account that the protrusion density (increased surface roughness) of the 2-shot polysilicon film is considerable, this mechanism could be ascribed to a gate oxide polarization phenomenon. The latter is not so intense as in the case of 2 6 -shot polysilicon films. This is so because the protrusion height for 2-shot films is not as high as that for 2 6 -shot films. Although not evidenced from fitting analysis, the carrier trapping/ detrapping mechanism should not be neglected since the grain-boundary trap density N t is remarkably high (Table 1). Probably, the polarization effect masks carrier trapping/detrapping activity. The case of M N#8 TFTs differs from the 2-shot and 2 6 -shot cases. This is so because the double stretched exponential law (3) was satisfactorily applied for temperature ranges of K and K. Outside these bounds, drain current transients follow the stretched exponential law (1). Fitting results revealed that the relaxation time s consists of two components s 1 and s 2, each one associated to thermally activated mechanisms (Fig. 3). The respective activation energies are E A (1) = ev and E A (2) = ev. This fact indicates that transient relaxation decay is a complex process, where two confronting mechanisms determine the drain current transient behavior. The first mechanism (E A (1),s 1 ) is ascribed to the gate oxide polarization phenomenon, activated in the temperature range of K. Although M N#8 polysilicon films exhibit low surface roughness, the protrusion height is comparable to the film thickness (Fig. 1). Thus, for the deposited dielectric these asperities form locations where the electric field is intense, causing dielectric polarization. The second one (E A (2),s 2 ) is carrier trapping/detrapping mechanism through shallow states. This is in accordance with the results extracted from deep level transient spectroscopy (DLTS) on M N#8 TFTs. Particularly, DLTS assessment was implemented immediately after the device transition from ON- to OFF-state. This transition results in sufficient band bending from the accumulation (OFF) to the strong inversion (ON) condition. DLTS spectra DI d (T) were extracted for rate window e values ranging from 6.25 sec 1 to 800 sec 1. Fig. 4 shows DLTS spectra for four indicative e values. The respective Arrhenius plot is shown in Fig. 5, from which E A (DLTS) = ev is extracted. This value approximates the E A (2) value extracted from double stretched exponential analysis, as previously reported. Also, it is worth noticing that the temperature bounds of DLTS spectra (Fig. 4) coincide with those of the second mechanism (s 2, E A (2) = ev) (Fig. 3). This confirms the existence of a hole trapping/ detrapping mechanism, ascribed to grain boundary traps originating probably from dislocations, according to the Arrhenius signatures DE2 and DH6 (Fig. 5) Stress behavior In Fig. 6 we can see the evolution of V th with the stress time for devices from all of our technologies. In all the figures shown for the stress evolution study, the difference of Fig. 3. Arrhenius plots of Eq. (2), derived from the fitting results of Eqs. (1) and (3) on the drain current transients of the devices: (m) 2-shot. W/ L = 32/8, E A = ev. (5) 2 6 -shot, W/L = 32/8, E A = ev, ()M N#8(1.1). W/L = 200/8, E A (1) = ev, E A (2) = ev. Fig. 4. DLTS spectra DI d (T) for four indicative rate window values e of a M N#8 TFT. The OFF-stale duration was 100 msec.

5 1382 D.C. Moschou et al. / Microelectronics Reliability 47 (2007) Fig. 5. Arrhenius plot (d) of DLTS spectra of Fig. 4. The respective activation energy is E A (DLTS) = ev. The closer Arrhenius signatures are DE2 ( ) and DH6 (...), which are associated with hole traps originating from grain boundary dislocations. initial rapid increase of the threshold voltage, showing the initial injection of hot electrons in the oxide, we observe a decrease. This could be attributed to positive charges at the interface masking the effect of the hot electron injection from a point where they become significant. This could also be supported by the increase of the subthreshold swing (Fig. 7), which is significantly larger than in any other technology. For the M N TFT in particular, we even see a slight improvement in S with stress time. The shortening of the effective channel length could cause an apparent increase of G m,max (Fig. 8), not representing an improvement of the polysilicon quality, as could easily be mistaken for [16]. This initial channel shortening could be caused by an injection of hot electrons in the gate oxide which is localized near the drain region; this is followed by a prevailing degradation of the interface quality extending along the whole channel, causing the subsequent G m,max decrease. Fig. 6. Evolution of DV th = V th (t) V th (0) with stress time. Fig. 7. Evolution of DS = S(t) S(0) with stress time. the parameters with the initial value of the unstressed device has been plotted to facilitate the comparison. For G m,max in particular we plot this difference as a percentage of the initial values. The smallest threshold voltage variation can be observed for M N and Dot samples, probably because of the minimal presence of surface asperities within the channel region, therefore minimizing the local field enhancements caused by the protrusions that can cause increased carrier injection in either the gate oxide or the interface. On the other hand, the 2 6 -shot and SIMOX samples show a logarithmic increase of the threshold voltage with stress time, indicating a mechanism of injection of hot electrons into the gate oxide. This can also be made clear by the positive shift of the threshold voltage (Fig. 6), indicating that this shift is mainly due to the oxide charge. As far as the 2-shot sample is concerned, we see a large variation of the threshold voltage but with a non-monotonous behavior. After the Fig. 8. Evolution of DG m,max /G m,max (0) = (G m,max (t) G m,max (0))/ G m,max (0) with stress time.

6 D.C. Moschou et al. / Microelectronics Reliability 47 (2007) This channel shortening effect seems to appear for longer stress times for the case of SIMOX devices, while for the 2 6 -shot TFT samples the overshoot of G m,max is absent (Fig. 8). The delayed channel shortening and subsequent degradation effects for SIMOX devices could be attributed to their superior quality (minimal roughness and no grain boundaries), as compared with polysilicon TFTs; the higher oxide and interface quality delays the degradation processes. As far as the 2 6 -shot devices are concerned, their pronounced surface roughness, as discussed before, may cause increased surface state generation as compared to oxide injection, being more favoured by surface scattering. Thus, the hot-electron injection effects are small compared to those caused by surface state generation. 4. Conclusions Polysilicon TFTs fabricated in novel SLS ELA films of different intragrain quality, surface roughness and grain boundary trap density were characterized. Apart from the grain quality, film asperities seem to have a significantly negative effect on the device field-effect mobility. A gate oxide polarization effect was observed and related to the polysilicon protrusions, while for 2 6 -shot and M N technology TFTs extended polysilicon defects were probed. The DC hot carrier stress investigation indicated a dependence of the device reliability on the microstructure of the polysilicon film and a possible channel shortening effect present for some of the TFT technologies. Acknowledgement The authors acknowledge financial support through the research project PENED 3ED550, administered by the Greek General Secretariat for Research and Technology. References [1] Matsuo T, Muramatsu T. Proc SID Intern Symposium 2004:856. [2] Sposili RS, Im JS. Appl Phys Lett 1996;69:2864. [3] Brotherton SD, McCulloch DJ, Clegg JB, Gowers JP. IEEE Trans Electron Dev 1993;ED-40:407. [4] Voutsas AT. IEEE Trans Electron Dev 2003;ED-50:1494. [5] Crowder MA, Moriguchi M, Mitani Y, Voutsas AT. Thin Solid Films 2003;427:101. [6] Voutsas AT, Limanov A, Im JS. J Appl Phys 2003;94:7445. [7] Toutah H et al. Microelectron Reliab 2003;43:1531. [8] Levinson J. et al. J Appl Phys 53(2):1193. [9] Papaioannou GJ, Voutsas A, Exarchos M, Kouvatsos D. Thin Solid Films 2005;487: [10] Exarchos M, Papaioannou GJ, Kouvatsos D, Voutsas A. J Phys: conf ser 2005;10:23 6. [11] Exarchos M, Papaioannou GJ, Kouvatsos DN, Voutsas A. J Appl Phys 2006;99: [12] Bavidge N, Boero M, Shimoda T. Appl Phys Lett 2000;77(23): [13] Yan F, Migliorato P, Ishihara R. Appl Phys Lett 2006;88: [14] Papaioannou GJ, Exarchos M, Kouvatsos D, Voutsas A. Appl Phys Lett 2005;87: [15] Exarchos M, Papaioannou GJ, Kouvatsos D, Voutsas A. In: 3rd International TFT Conf. Proceedings (ITC 2007), [16] Farmakis FV et al. Int Semiconductor Conf CAS 99 Proc 1999;1: