Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures

Transcription

1 Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures Heba Saadeldeen Zhaoxia (Summer) Deng Timothy Sherwood Frederic T. Chong (UCSB) (UCSB) (UCSB) (UChicago) 1

2 Phase Change Materials for PCM PCM exploits chalcogenide glass materials to represent bits with different material states at different temperatures. cooled: amorphous glass-like state, high resistance. heated: crystalline state, low resistance. However, different material compositions also exhibit different properties. Ge (at%) The stoichiometry coefficient is: y/(x+y) in (GeTe)x(Sb2Te3)y GeTe e.g. when the stoi coefficient increases, the material exhibits lower operating temperature and longer endurance. GST Te (at%) Sb 2 Te 3 Sb(at%) 2

3 3D PCM Stack Compared to DRAM, PCM emerges as a better candidate for 3D stacking because it s more high-temperature friendly. Traditional homogeneous 3D PCM stack pros cons + High bandwidth + low wire delay + low standby power - Increased power density - Limited lifetime 3

4 Motivation - Increased power density. Non-uniform heat distribution: Layers near the heat sink exhibit cooler ambient temperatures than layers far from it. - Limited lifetime. Non-uniform failure distribution: Cells storing ECC bits should have longer lifetime than cells storing data bits. Exploit non-uniform material distribution to improve the energy efficiency and reliability. 4

5 Heterogeneous 3D PCM Stack Rather than a one-material-fits-all approach, we propose Heterogeneous 3D PCM stack: Choose PCM materials according to each layer s ambient temperatures. Use longer-endurance PCM materials to store ECC bits. Compared to a homogeneous PCM stack, the heterogeneous PCM stack improves energy efficiency by 1.21x to 3.5x, and extends lifetime by 30%. 5

6 Content PCM material tradeoffs Thermal modeling of 3D PCM stack Heterogeneous 3D PCM stack Manufacturing and integration complexity 6

7 Content PCM material tradeoffs Thermal modeling of 3D PCM stack Heterogeneous 3D PCM stack Manufacturing and integration complexity 7

8 An Overview of PCM Material Tradeoffs Parameter tradeoffs across different chalcogenide materials: e.g. meting temp -> reset current -> energy -> endurance 7 - Ambient Temp. (T amb ) Melting temp. (T m ) Reset current (I reset ) Stoichiometry coefficient Write time (T write ) Energy (E) + - Endurance (L) Operating temp. (T op ) Retention (R) - 9 8

9 Reset energy Materials of higher stoi coefficients have lower melting temperatures, thus require lower reset current and shorter write time. Assuming constant resistivity: e.g. from Ge2Sb2Te5 to Sb2Te3, 1.8 reset energy decreases by 54.2%. 1.6 Material Ge2Sb2Te5 Sb2Te3 coefficient T_write I_reset Energy Relative T_write T_write I_reset Relative I_reset Normalized to Ge2Sb2Te y/(x+y)

10 Operating temperature Higher stoi coefficients also lead to lower operating temperatures of materials. Ambient temperatures in a 3D memory stack: peak temperature: ~100 C layers near the heat sink: ~95 C To ensure reliability, Top>Tambient, and this restricts the stoi 1.02 coefficient to be in [0.33, 0.4]. e.g. from Ge2Sb2Te5 to GeSb2Te3, reset energy decreases by up to 10% and T_op decreases by 5%. T_op Relative T_op Relative T_op Relative Energy Relative Energy Energy 1x 0.9x y/(x+y) 10

11 Endurance K. Kim et al. identified that reset energy is responsible for endurance failures due to material melting and quenching ops. [Kinam Kim and Su Jin Ahn Reliability investigations for manufacturable high density PRAM. In Reliability Physics Symposium, 2005] Reducing the reset energy improves the endurance. e.g. from Ge2Sb2Te5 to GeSb2Te3, endurance increases to 2x, but T_op decreases by 5 C. Material Ge2Sb2Te5 Ge3Sb2Te9 coefficient T_op Decrease in T_op in Celcius Decrease in T_op Improvement in Endurance 3 2 Improvement in Endurance Endurance 1x 2x y/(x+y) 11

12 Content PCM material tradeoffs Thermal modeling of 3D PCM stack Heterogeneous 3D PCM stack Manufacturing and integration complexity 12

13 3D Memory Stack The ambient temperature increases as we move away from the heat sink. n_mem memory layers Typical 3D stack structure Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis.. Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis Layer 0 (Processor) Package Heat Sink PCM memory layer n_mem PCM memory layer 1 Tpeak 13

14 Thermal Modeling We use the analytical model described in [Im and Banerjee]. [Sungjun Im and K. Banerjee Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs. In Electron Devices Meeting, 2000.] The temperature rise above ambient temperature at the j th active layer is: Ri: thermal resistance Pk: power dissipation A: the area n: total number of layers Then, we estimate the difference in temperature between the top layer n, and the bottom layer y as follows: 14

15 Homogeneous 3D stack Choosing a material that is optimized for the maximum ambient temperature across the stack is energy inefficient. Less programming current is required at elevated temperatures. Ireset1 >= Ireset2 >= >= Iresetn_mem >= Iresetopt Tpeak n_mem memory layers Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis.. Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis Layer 0 (Processor) Package Heat Sink PCM memory layer n_mem PCM memory layer 1 Tmelting 15

16 Content PCM material tradeoffs Thermal modeling of 3D PCM stack Heterogeneous 3D PCM stack Manufacturing and integration complexity 16

17 Heterogeneous 3D stack For each layer, choose a material whose operating temperature is equal to or slightly higher than Tpeaki. Optimal reset current and write time for all layers. More energy efficient T n, Tpeak n T 2, Tpeak 2 T 1, Tpeak 1 Set n Memory layers (n -1)x to nx... Set 2 Memory layers x to 2x Set 1 Memory layers 1 to x Top n PCM n Top 2 PCM 2 Top 1 PCM 1 Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis Metal Layer Active Silicon Bulk Silicon Face to Back D2D vis Memory layer x Memory layer 1 17

18 Results Energy savings at peak temperature As the set size approaches the total number of layers, the energy savings decrease. With more layers, the energy savings also decrease as the homogeneous base case uses a material that is optimized for an 8-layer 3D stack. Improvement in Write Energy w.r.t Homogeneous stack Homogeneous stack Optimal stack (set size = 1) set size = 2 set size = 4 set size = 6 set size = Total Number of PCM memory layers in 3D stack 18

19 ECC implementation Storing ECC bits in more reliable PCM materials can help mitigate ECC early failures. However, the downside is that such PCM materials require lower operating temperatures. We should place ECC bit cells away from the hotspots. Hotspots IQ RF RF IQ ROB ALU ALU ROB BP LSQ LSQ BP ICache DCache DCache ICache Shared L2 Cache ICache DCache DCache ICache BP LSQ LSQ BP ROB ALU ALU ROB IQ RF RF IQ The floor plan of the processor layer with 4 cores [Kevin Skadron, et al Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim] 19

20 Results Eliminating ECC early failures ECCN-R: N is the code strength and R is the endurance improvement of ECC bits over data bits. Lifetime Normalized to OPT6 (%) Long lifetime and low storage overhead PayG (ECC1-2X) OPT6 PayG (ECP1) ECC6-2X Storage Overhead (%) ECC6 SAFER32 ECP6 Short lifetime and high storage overhead 20

21 Results PCM materials The memory lifetime is comparable to OPT6 with 1.8x endurance improvement on ECC6 bit cells. PCM materials with stoi coefficient of could achieve 1.8x improvement in endurance. Lifetime Normalized to OPT6 (%) >99% OPT6 ECC6 ECC6-NX Decrease in T_op in Celcius Decrease in T_op Improvement in Endurance X Improvement in Endurance X Improvement of endurance of ECC bits over data bits y/(x+y)

22 Content PCM material tradeoffs Thermal modeling of 3D PCM stack Heterogeneous 3D PCM stack Manufacturing and integration complexity 22

23 Manufacturing and integration complexity The feasibility of tailoring the chemical composition of the material has been demonstrated by Yamada et al. e.g. Ge2Sb4Te7, GeSb2Te4, Ge2Sb2Te5, Ge19Sb25Te56, Ge27Sb18Te55 and Ge11Sb31Te58 3D stacking enables combining different technologies. However, the manufacturing cost is still unknown. Further exploration in manufacturing will discover more opportunities for choosing the PCM materials right for the use case. 23

24 Conclusion We explored the various trade-offs of chalcogenide materials. We exploited such material trade-offs to address the energy efficiency and reliability issues in the 3D PCM stack: Choose PCM materials according to each layer s ambient temperatures. Use longer-endurance PCM materials to store ECC bits. Compared to a single-material PCM stack, the multi-material PCM stack improves energy efficiency by 1.21x to 3.5x, and extends lifetime by 30%. 24

25 Thank you Questions? 25