CMP Process Development Techniques for New Materials. Robert L. Rhoades, Ph.D. ECS 213 th Meeting (Phoenix, AZ) May 19-21, 2008

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1 CMP Process Development Techniques for New Materials Robert L. Rhoades, Ph.D. ECS 213 th Meeting (Phoenix, AZ) May 19-21, 2008

2 Outline Background and Industry Drivers Generalized Development Sequence CMP Process Development Techniques Examples Conclusions 2

3 A Market Divided Background Why are development techniques so important? SPEED and COST! New products must be ready on time for market launch Long term efficiency improves competitive strength Moore s Law dominates the CMOS industry Not affected by cycles, markets, analysts, or the economy Photolithography and CMP are two critical process technologies to continue both cost and performance improvements Photolithography enables SHRINKS CMP enables more complex STACKS Trend has held for >35 years! Source: Intel Corporation 3

4 Market Driver The Consumer What do they want? More, Better, Faster, Smaller, and Cheaper inflection point for semiconductors: consumer-based products become primary industry driver. Consumers demand More for Less. Source: 2007 Industry Strategy Symposium Hans Stork, CTO, Texas Instruments Source: 2007 MEPTEC Jim Walker, Gartner Dataquest Consumers demand More in Less. Historically enabled by Moore s Law device shrinks & larger wafers. 4

CMP Drivers (1) % of Wafers Using CMP is Increasing (2) # CMP Polishes per Wafer is Increasing + (3) # CMP Polish Applications is Increasing 1995 2001 2008 Glass (oxide) Glass (oxide) Glass (oxide)

5 CMP Drivers (1) % of Wafers Using CMP is Increasing (2) # CMP Polishes per Wafer is Increasing + (3) # CMP Polish Applications is Increasing Glass (oxide) Glass (oxide) Glass (oxide) Tungsten Tungsten Tungsten Copper Copper Shallow Trench Shallow Trench Polysilicon Polysilicon Low k Cap Ultra Low k = VOLUME (4) Each Application Requires a New CMP Process + = TECHNOLOGY Metal Gates Gate Insulators S ources: Cabot Microelectronics Corp. & E ntrepix, Inc. High k Dielectrics Ir & Pt Electrodes Magnetics 5

6 Growth in Applications CMP is still growing for CMOS applications... And many newer applications are now also being developed beyond traditional CMP. Traditional CMOS Applications - Oxide (ILD, pre-metal dielectric, etc.) - Tungsten (plugs or local interconnect) - Shallow trench isolation (STI) - Copper (integrated with or w/o low-k dielectric) New Apps for CMOS devices - Polysilicon - Polymers (both low-k and other uses) - Capping layers - High-k dielectrics - Gate insulators - Metal gates - Noble metal contacts MEMS - Oxides (doped or undoped) - Polysilicon (usually structural) - Nitrides and oxynitrides - Separation layer (MEMS-first or MEMS-last) Other - Strained layer epi substrates - Custom III-IV and II-IV epi layers - Phase change memory materials - Photoresist and other polymers - Magnetic materials (active or shielding) - Grating structures - Integrated optical layers - Advanced packaging - 3D IC s and similar structures 6

7 Development Sequence Development Sequence Design Concept The vast majority of development efforts follow this basic path Materials Selection Integration Planning Process Development Device Prototype Optimization Qualification Each stage has certain inputs required, activities to be performed, and desired outputs that increase in difficulty and complexity for each successive stage Each stage assumes successful completion of the previous stage, or at least overlapping execution of the previous stage Pilot Production High Volume Manufacturing Failure at any stage usually means backing up at least one stage to try again 7

8 Stage Detail #1 Stages leading to a working device prototype Stage Resources Activities Stage Outputs Design Concept Designers 1.Brainstorming Approval from R&D team, R&D team 2.Sketches/drawings/etc. management for design 3.Documentation approach & use of CMP Materials Selection Designers 1.Assess extendability of List of primary materials and R&D team existing materials & processes backups, if possible, for all Materials scientists 2.Propose/evaluate alternatives materials to be polished Integration Planning Designers 1. Assess extendability of First pass process flow R&D team integration & process flow showing each CMP level Integration team 2. Propose alternatives Process Development Integration team 1.Process screening expt Demonstration of initial Process engineering 2.Repeat trials until acceptable process for new materials, Test wafers performance on blanket films new modules or processes Eng time on process tools 3.Early patt test w frs (maybe) needing major improvements Device Prototype Integration team 1.First silicon on new masks One or a few working devices Process engineering 2.Lots of analysis (SEM,etc.) & proposals for improving Analytical support team any critical path items Wafers & process tool (eng) 8

9 Stage Detail #2 Stages leading to revenue Stage Resources Activities Stage Outputs Optimization Integration team 1.Refine CMP process based Iterative improvements until Process engineering on details from first silicon acceptable performance and Analytical support team 2.Explore process windows yield are achieved Wafers & process tools (1x) 3.Repeat trials (consistency) Qualification Engineering teams 1.Produce live devices for qual Devices for burn-in & life test Manufacturing teams 2.Prep for transfer to mfg Documentation in place for Wafers & process tools (1x) 3.Establish initial SPC limits each process step Pilot Production Manufacturing teams 1.Transfer control to mfg Sellable devices Engineering teams 2.Monitor device and process Assessment of any issues Wafers metrics for signs of instability showing up as volume ramps Process tools (multiple) 3.Refine and lock SPC limits Volume Manufacturing Manufacturing teams 1.Manufacturing controls Profitable devices Engineering teams 2.Monitor SPC trends Technical inputs for next gen Wafers 3.ID yield/cost improvement device designs Process tools (multiple) targets & requal when justified 9

10 CMP Metrics Most CMP processes are measured on 5 basic metrics Removal Rate and Uniformity Defectivity Planarization (step height, dishing/erosion, surface roughness, etc.) Process Stability (repeatability from wfr-to-wfr, run-to-run, etc.) Cost per Wafer 10

11 Interactions CMP Process Metrics Process Settings Rate Uniformity Defectivity Planarization Down force, DF STRONG weak Moderate STRONG Back pressure, BP weak Moderate weak weak Table speed, TS STRONG weak Moderate STRONG Carrier speed, CS weak Moderate (often nonlinear) weak weak Slurry flow, SF nonlinear nonlinear Moderate weak Conditioner force weak weak weak Moderate Conditioner speed don't care don't care weak weak 11

12 CMP Development CMP Development Sequence Generate Test Wafers Consumables Screening Process DOE's Optimize Uniformity Optimize Planarity Optimize Defectivity Repeatability (multiple runs) Stability (marathon) Release for Device Qualification Zoom in on CMP process development Assumes fundamentals of pad/slurry research are already done by suppliers Test wafer availability and quality often impact timeline, validity of results, etc. Initial process DOE s generally focus on removal rate and gross surface quality Optimization stages can be interchanged or executed in parallel Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application Failure at any stage usually means backing up at least one stage to try again 12

13 Early CMP Stages Early stage development efforts often involve: Immature deposition or growth processes Poorly characterized materials or integrations Technologists who may not be familiar with CMP and how it interacts with other process modules Wide variation in pattern density/feature sizes Wafer sizes smaller than 200 mm Limited availability of test wafer These factors can create huge challenges for CMP 13

14 Consumables Screening Resources Pads (one or more types) Slurries (one or more types) Blanket film test wafers Desired Outputs Choose pad/slurry that achieve: Removal Rate at or above target Surface finish acceptable (1 st pass) Experimental Plan Inputs Include blanket films or bulk samples of ALL materials Change pads with major changes in slurry Stick to one mid-point recipe as a common data point for all combinations Include supplier-recommended process recipes whenever practical Keep data analysis quick and simple (optimize later) 14

15 Rate Screening Removal Rate Metal CMP application Removal Rate (Ang/min) Slurry #1 Slurry #2 Slurry #3 Slurry #4 Slurry #5 Slurry #6 Slurry #7 Slurry #8 Slurry #9 Slurry #10 Pad selection frozen Goal of 4 ka/min Multiple slurry candidates Slurry #8 was chosen for further optimization 15

16 Process DOE s Resources Consumables (Pad and slurry) Blanket film test wafers (all mtrls) Defect monitor wafers (if available) Desired Outputs Rate and uniformity responses to changes in major process variables Identify a process to start further optimization Experimental Plan Inputs Goal is to get preliminary process responses to major variables Preston s Equation (RR=k*P*V) is only an approximation Keep % changes below 25% to keep DOE s as linear as possible Responses to slurry flow and back pressure are not usually linear Successive 2x2 or 3x3 DOE s are generally preferable to massive designs Include defectivity as an output metric if wafers are available 16

17 Optimization Resources Consumables (Pad and slurry) Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers for planarization Desired Outputs Single process recipe that meets all required process metrics Data supporting chosen recipe and responses in nearby process space Experimental Plan Inputs Be careful using DOE s single-variable curves often more helpful at this stage Focus on variables with strongest link to parameter being optimized Uniformity: Carrier-to-table speed ratio, back pressure or carrier zones Planarization: Downforce, table speed (keep in mind rate tradeoffs) Defectivity: Downforce, slurry flow, final recipe steps (remember tradeoffs) Number of wafers can quickly get large 17

18 Repeatability Resources Consumables (multiple batches) Blanket film wafers Defect monitor wafers Patterned wafers (optional) Desired Outputs Consistent process performance data using same process settings across multiple consumable sets Experimental Plan Inputs Keep process recipe consistent throughout trials Measure all relevant metrics, not just removal rate Planarization monitor can be low sampling frequency Defect monitor can likewise be low frequency if confident in process 18

19 Marathon Run Resources Consumables Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers Desired Outputs Data showing process consistency through pad life (or at least a reasonably large number of wafers) Experimental Plan Inputs Generally want to prove stability for duration of pad life, or at least 250 wafers Different than repeatability focus is on process stability of a single pad set Can be a continuation of the last pad set of the repeatability trial Liberal use of filler wafers can save cost Sample at some low frequency for defects and planarization 19

20 Example: MEMS Oxide Critical Concerns: 6000 Minimize oxide deposition Incoming topography 2.8 um Final topography must be < 0.4 um Smooth No sharp corners anywhere Removal Rate (Ang/min) Batch to batch consistency Run # Key Process Metrics & Constraints Metric Incoming Value Post-CMP Target Actual Oxide film thickness 6.5 um 3.0 um 3.02 um Step Height 2.8 um < 0.4 um 0.2 um Removal Rate (um/min) n/a

21 Example: SiGe Epi Process Factors: Standard Si process left Ra too high Post-CMP clean had to be developed Composition varied widely Metric Surface Roughness, Ra Removal Rate Incoming Value >10 nm n/a Target <1 nm >500 A/min Actual nm A/min Total Mtrl Removal n/a um Within 5% Polish Rate (Ang/min) % 20% 40% 60% 80% 100% Roughness, Ra (nm) Pre-CMP Post-CMP Epi Layer %Ge 21

22 Multiple Materials Multiple Materials Final surface is comprised of oxide, polymer, and two different metals Goals of CMP process: High rate on oxide and polymer Low Ra on all materials Planar surface across all mtrls Initial focus: slurry screening RR (Ang/min) Material Removal Rates by Formulation Oxide Rate Polymer Rate Metal #1 Rate Metal #2 Rate Baseline Sample A Sample B Sample C Sample D Sample D+ Sample E+ sample delaminated. Data Removal Rate Roughness (Ra) Run Order Slurry Oxide Rate Polymer Rate Metal #1 Rate Metal #2 Rate Oxide Ra (Ang) Polymer Ra (Ang) Metal #1 Ra (Ang) Metal #2 Ra (Ang) 1 Baseline n/a 5 2 Sample A Sample B Sample C Sample D Sample D n/a n/a 7 Sample E

Direct Wafer Bonding Example #1: TEOS on X Oxide surfaces tend to bond well when polished to sufficiently low Ra Incoming roughness driven by surface prep of underlying material Sufficient oxide

23 Direct Wafer Bonding Example #1: TEOS on X Oxide surfaces tend to bond well when polished to sufficiently low Ra Incoming roughness driven by surface prep of underlying material Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness Material Stack Incoming Ra (A) Post-CMP Ra (A) TEOS on Silicon 7 3 TEOS on SiC 72 7 TEOS on Polysilicon 87 7 TEOS on AlN TEOS on Metal Example #2: Inlaid Cu in TEOS Incoming topography >2.5 ka Goal of <200 A total topography Flat across Feature POST-CMP TOPOGRAPHY ACHIEVED Angstroms 23

24 Early Stage Summary In general, the key requirements for early stages of CMP development are: Strong understanding of materials and key integration issues with CMP Fully capable process equipment and metrology Experimental methods adapted to non-linear systems Creativity and innovation Successful early stage efforts lead to working prototype devices and sufficient understanding to move forward with qual 24

25 Transition to HVM Development team stays heavily involved through qualification Handoff to manufacturing occurs during ramp to volume Requirements for smooth transition include: Documented procedures SPC (at least initial limits) Training of manufacturing staff (operators, techs, sustainers, etc.) Followup of any issues uncovered during initial ramp Same basic requirements apply to qualifying an existing fab process in an outsource facility (example follows) 25

26 Blanket wafer marathon Oxide CMP Qualification Run Polisher: AMAT Mirra Mesa Pad: IC1010 Slurry: Klebosol Conditioning: In-situ Metrology: 49-point diameter scan, 3mm EE Removal Rate % NU Removal Rate (Ang/min) Uniformity (% 1-sigma) 1000 Start Wafer Number

27 Oxide Defectivity Wafer-212 Wafer-237 Wafer-187 Wafer-162 Wafer-137 Mesa Cleaner: 2% NH 4 OH in both brush stations Metrology Platform: AMAT Orbot Pre LPD Post LPD LPD Count Setup Wafer-12 Wafer-37 Wafer-62 Wafer-87 Wafer-112

28 Contamination Fab Reference Entrepix Polisher #1 Entrepix Polisher #2 Element All Units = 1E10 atoms/cm2 S Cl K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn W Post-CMP residual surface contamination (shown in table at left) was compared between existing qualified process and desired outsource process no differences were observed Planarization efficiency was compared on test wafers (data not shown) to verify that results were exactly equivalent to in-fab data Based on accumulated data, authorization was obtained to run product split lots to compare device yield 28

29 Split Lot Yields Wfr 1-6 Wfr 7-12 Product yield equivalent between all split lot groups Wfr Wfr Qualification complete for outsource production 29

30 Conclusions Efficient development of new products is required for a fab to remain competitive Many new device technologies require new CMP processes CMP process development generally proceeds along a consistent sequence of stages Choose experimental methods appropriate to the stage Simple rate and surface quality screening to select pad/slurry DOE s for first pass recipe development Optimize uniformity/planarization/defectivity using combination of DOE s, single-variable focus, and engineering instinct Verify repeatability and stability (marathon run) on all metrics Characterize yield and live device performance at appropriate points in preparation for product qual and ramp 30

31 Contact info Anyone desiring copies of this presentation or any other information can contact any of the following individuals: Rob Rhoades Chief Technology Officer Tel: Fax: Bob Tucker V.P. and General Manager Tel: Fax:

New Applications for CMP: Solving the Technical and Business Challenges. Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009

New Applications for CMP: Solving the Technical and Business Challenges Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009 Outline Background and Business Climate for CMP Technical Approach