Preventing Pad Cratering During ICT Using Sherlock

Transcription

1 Preventing Pad Cratering During ICT Using Sherlck DfR Slutins Webinar Nvember 21,

2 Pad Cratering Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), bard depanelizatin, cnnectr insertin, and ther shck and vibratin inducing activities. Simulatin can be used t prevent this serius but prevalent failure. Pad cratering was first recgnized in BGA packages but newer leadless, bttm terminatin cmpnents are als vulnerable.

3 Pad Cratering: Strain & Flexure Cracking initiating within the PCB laminate during a dynamic mechanical event In circuit testing (ICT), bard depanelizatin, cnnectr insertin, shck and vibratin, etc.

4 Laminate Cracking Leads t Trace Fracture Trace ruted externally Functinal failure will ccur Bending Frce

5 Pad Cratering Intel (2006) Drivers Finer pitch cmpnents Mre brittle laminates Stiffer slders (SAC vs. SnPb) Presence f a large heat sink Lcatin PCB thickness Cmpnent size & rigidity Temperatures & cling rates Difficult t detect using standard prcedures X-ray, dye-n-pry, ball shear, and ball pull 5

6 Is Pad Cratering a Pb-Free Issue? N, but 35x35mm, 388 I/O BGA; 0.76 mm/min Average Fracture Paste Slder Ball Std Dev (N) Lad (N) SnPb SnPb SnPb Sn4.0Ag0.5Cu Sn4.0Ag0.5Cu Rubaud, HPAPEX

7 BGA Mechanical Lading Failure Mdes Weakest link in the system fails first

8 IPC 9708 Failure Mdes Defined

9 IPC 9704 N pass / fail limits 3 strain limit appraches Cmpnent supplier prvided Custmer specified Rate limited Maximum allwable strain versus rate and PCB thickness

10 Detecting Pad Cratering CalPly study shwing failure f electrical testing t capture all defects Bard Level Failure Analysis f Chip Scale Package Drp Test Assemblies, 2008 Internatinal Micrelectrnics And Packaging Sciety.

11 Electrical Failure Paret frm CalPly Study Majrity f failures ccur at crners f packages: lcatins f stress & strain cncentratins Bard Level Failure Analysis f Chip Scale Package Drp Test Assemblies, 2008 Internatinal Micrelectrnics And Packaging Sciety.

12 Pad Cratering Failure Analysis Difficult t detect using standard prcedures Cmpanies frequently unaware f pad cratering until failure happens Recalls have been cmmn and painful! Ptential warning signs: Excessive BGA repair rate High percentage f defective BGAs High rate f retest t pass at in circuit test (ICT) New X-ray ptential with 3D m-ct inspectin Precisin crss-sectins are required t cnfirm

13 Ptential Mitigatins t Pad Cratering Design Nn-critical pads Slder mask defined vs. nn-slder mask defined Pad Gemetry Layut & PCB thickness Crner Glue Mre cmpliant slder SAC305 is relatively rigid, SAC105 and SNC are pssible alternatives New laminate acceptance criteria and materials Best Mitigatin! Avid the prblem by nt verstressing the intercnnect Limitatins n bard flexure Simulatin t predict the strains induced during ICT and highlight ptential prbles 750 t 500 micrstrain, cmpnent and layut dependent Prcess Cntrl & Validatin

14 ICT Strain: Fixture & Prcess Analysis Review/perfrm ICT strain evaluatin at fixture supplier and in prcess: 500 µs rule f thumb, critical fr BTCs, CSP, and BGA packages T reduce the pressures exerted n the PCB: First and simplest slutin: reduce the prbe frces when pssible. Secndly, ptimize psitin f the fingers/stppers t cntrl prbe frces. Often difficult t achieve. Mechanically, the stppers must be lcated exactly under the pressure fingers t avid the creatin f shear pints

15 Sherlck Sftware Eliminate ptential bed f nails (ICT) damage by: Identifying cmpnents n the circuit card that culd experience cracking r failure during bed f nails testing. Prir t the ICT, the designer can ptimize the prcess: Change test pints Change pg pin pressure, r Add /mve bard supprts Sherlck analysis is cmpnent-specific, allwing fr mre precise identificatin f at-risk areas

16 Sherlck Autmated Design Analysis Sftware Designers can identify ptential bed f nails damage early in the layut prcess, befre a bed f nails tester is ever designed Allws fr tradeff analyses, saving cstly bard damage and redesign.

17 Setup Test Pints and Fixtures Test pints are autmatically laded if defined in pick and place r the db++ archive Fixture lcatins can als be imprted

18 Test Pint Mdificatin

19 ICT Fixtures Guide Pins (munt hle) cnstrained in-plane (x,y) but can mve up and dwn Supprt pin just cnstrained in the Z directin

20 Finite Element Mesh

21 Displacement

22 Strain Results

23 Cmpnent Risk

24 Pad Cratering Cnclusins Pad Cratering is an increasingly cmmn failure mde Catastrphic and nn-rewrkable Easy t avid detectin and difficult t diagnse Partial cracks riskiest since they escape and expand in the field Multiple paths fr mitigatin Few fr true preventin Best mitigatin is t reduce bard level strains N hard, fast rules fr avidance Dependent n design, cmpnent, layut, prcess Simulatin can be used t quantify the strains assciated with ICT