Electromigration behavior of 60 nm dual damascene Cu interconnects

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1 JOURNAL OF APPLIED PHYSICS 102, Electromigration behavior of 60 nm dual damascene Cu interconnects Jung Woo Pyun, a Won-Chong Baek, Lijuan Zhang, b Jay Im, and Paul S. Ho Microelectronics Research Center, PRC/MER Mail Code R8650, The University of Texas at Austin, Austin, Texas , USA Larry Smith and Gregory Smith SEMATECH, 2706 Montopolis Dr., Austin, Texas 78741, USA Received 5 June 2007; accepted 11 September 2007; published online 8 November 2007 Electromigration EM reliability was investigated for Cu fine lines fabricated using a SiON trench filling process down to 60 nm in linewidth. EM was observed to be dominated by intrinsic failures due to void formation in the line trench. The lifetimes of 60 nm lines were longer than those of 125 nm lines with the standard damascene structure which can be attributed to a distinct via/metal-1 configuration with less process-induced defects at the via interface. The line scaling effect on EM reliability was investigated using three linewidths: 60, 110, and 185 nm. EM lifetimes were found to be similar for different linewidths, consistent with intrinsic failures caused by void formation in the line trench driven by interfacial mass transport. Statistical, multilinked EM test structures demonstrated a monomodal failure distribution for the fine lines, indicating suppression of processing-induced extrinsic defects although processing control on line dimension and geometry remained an issue. The activation energies were found to be around 0.80 ev for both fine lines and standard lines, indicating that interface diffusion dominates mass transport in Cu lines American Institute of Physics. DOI: / I. INTRODUCTION In fabrication of Cu damascene interconnects, chemical mechanical polishing CMP generates a significant amount of process defects on the upper surface of Cu lines, making the interface between Cu and the cap layer the dominant diffusion path for electromigration EM. 1 4 With scaling of the line dimensions, the current density and the ratio of the interface to volume continue to increase. Combined with the implementation of low k dielectrics and thus more processing defects being generated, this raises a basic question concerning the scaling and processing effects on EM reliability. In a previous study, we found that with scaling of the linewidth down to 125 nm, the probability of early failures induced by process-induced defects increased due to the difficulty of controlling the integration process. 5 This paper investigates the scaling and processing effects on EM reliability of Cu dual damascene structures to a linewidth of 60 nm. In this paper, ultrafine lines down to 60 nm were fabricated by refilling with a SiON layer to reduce the trench width while keeping the other line dimensions the same with those of the 125 nm line. The advantage of this process is that the final trench width can be controlled by varying the thickness of the filling material. As it turned out, the trenchfilling process yielded a distinct via/ M1 interface, which helped to eliminate the extrinsic void evolution at the via bottom. This made possible the investigation of intrinsic EM reliability for fine lines. In this study, we first compare the EM reliability of 60 nm lines by SiON filling with 125 nm lines by standard processing. Then this is followed by a study of line scaling effects on EM for three linewidths: 60, 110, and 185 nm with downstream current flow. Finally, we perform EM tests with multilinked structures to investigate early failure statistics for the 60 nm Cu lines. II. EXPERIMENTAL DETAILS Two-level M1, via, and, M2 EM test structures were designed to investigate EM reliability for the Cu interconnects. The trench-filling process using SiON to produce narrow lines was applied only to the M1 level. As shown in Fig. 1, the EM tests performed in this study were all with downcurrent electron flow, where the electron current flowed from a wide and short M2 level to a narrow and long M1 level. This arrangement facilitated the observation and analysis of failure sites and void formation at the M1 line. In addition to single-link structures, multilinked test structures were fabricated to determine the statistics of intrinsic strong-mode failures and process-induced extrinsic weak-mode early failures. 6 Ten N=10 and one hundred N=100 lines were connected in series by using short 10 m M2 lines and long 150 m M1 lines. EM test samples were fabricated at SEMATECH using dual-damascene process on 300 mm wafers. The intermetal dielectric layer for study was silicon oxide. As shown in Fig. 2, the SiON filling layer was deposited after trench formation, followed by Ta barrier deposition and Cu electroplating. a Electronic mail: jw.pyun@samsung.com b Electronic mail: ljzhang@mail.utexas.edu FIG. 1. Schematic diagram of a two level M1/via/M2 EM test structure with a down current electron flow condition /2007/102 9 /093516/5/$ , American Institute of Physics

093516-2 Pyun et al. J. Appl. Phys. 102, 093516 2007 FIG. 3. CDF plots of down stream EM test structures with SiON filling layer 60 nm and without SiON filling layer 125 nm.

7 deduced the following expression for EM lifetime: = L cr / d = L cr hkt/ s D i F i, 1 FIG. 2.

2 Pyun et al. J. Appl. Phys. 102, FIG. 3. CDF plots of down stream EM test structures with SiON filling layer 60 nm and without SiON filling layer 125 nm. EM test was performed at T=270 C and j=1.0 MA/cm 2. For strong-mode EM failure with void formation driven by interfacial mass transport in the line trench, Hu et al. 7 deduced the following expression for EM lifetime: = L cr / d = L cr hkt/ s D i F i, 1 FIG. 2. Color online Schematics of SiON filling process scheme: a trench formation, b SiON deposition + Ta barrier deposition + copper deposition, d CMP, and d cross-sectional TEM image showing 60 nm M1 trench with SiON filling. Using this process, the trench width was reduced from 130 to 60 nm. The Ta barrier thicknesses, shown in Fig. 2 d, atthe trench bottom and sidewall were 13 and 6 nm, respectively. The patterned wafers were diced to yield test chips which were mounted and electrically connected to a ceramic package by wire-bonding using Al wires. Package-level EM tests were performed in a vacuum chamber with a backfilled pure nitrogen environment at 20 Torr, heated at a rate of 5 C/min to the target temperatures and with a current density of 1.0 MA/cm 2. Resistance increase due to void formation was monitored to determine the EM lifetime. The time of 10% resistance increase was taken as the EM lifetime. Based on the lifetime data, the cumulative distribution function CDF was obtained as a function of time. The EM failed samples were examined by transmission electron microscopy TEM to analyze the damage formation in the line structure. III. RESULTS AND DISCUSSION A. Effect of SiON filling on EM reliability To investigate the effect of via interfacial defects, EM tests were performed on test structures with 60 nm lines with a SiON filling layer and 125 nm lines with standard processing. The EM lifetimes obtained at 270 C and 1.0 MA/cm 2 are compared as shown in Fig. 3. Interestingly, the samples with a narrower 60 nm linewidth and SiON filling show a longer lifetime and somewhat larger standard deviation than the control samples of 125 nm linewidth without SiON filling. where L cr is the critical void length to cause line failure, d is the net drift velocity, h is the line thickness, k is the Boltzmann s constant, T is the absolute temperature, s is the effective thickness of the interface region, D i is the Cu/ dielectric interface diffusivity, and F i is the EM driving force at the interface. Accordingly, when mass transport is dominated by interfacial diffusion, the EM lifetime is only related to the metal line thickness, h. Since the line thicknesses for the two sets of test structures are the same, their lifetimes are expected to be the same under identical test conditions. This, however, is not consistent with the results observed for the 60 and the 125 nm line structures. To help understand this unexpected result, crosssectional TEM was employed to examine the damage formation in the EM test samples. The cross-sectional TEM images and the structure schematics are compared in Fig. 4 for these two types of test structures. As shown in Fig. 4 c, the SiON filling made the M1 trench width narrow enough to be fully covered by the via bottom. This unique interface structure between the via and M1 for the 60 nm lines was able to prolong the EM lifetime by about twofold as shown in Fig. 3. When an EM-induced void forms in a standard sample with no SiON filling and grows as wide as the M1 trench on top of the cathode end of M1, such a sample fails most probably by an open circuit. In contrast, for a sample with the SiON layer, the EM current can be shunted to the Ta barrier even when M1 trench is vacated with EM-induced void. The sample will fail only when a void extends to the Ta barrier and the resistance becomes large enough to induce Joule heating to burn out the structure. In addition, the unique M1/ via interface structure can eliminate the most probable void formation sites for early failures. These defects usually occur at the interface between the bottom portion of the via sidewall and the M1 trench top. Therefore, only the intrinsic effect, devoid of the extrinsic effect, through the increased mass transport can affect the EM lifetime of the SiON-filled lines. To further understand the failure mechanism, resistance

093516-3 Pyun et al. J. Appl. Phys. 102, 093516 2007 FIG. 4. TEM images of dual-damascene Cu interconnects.

traces were monitored and the results for the two different linewidths are shown in Fig. 5.

3 Pyun et al. J. Appl. Phys. 102, FIG. 4. TEM images of dual-damascene Cu interconnects. M1 trench width was reduced from 130 a to 60 nm c using the filling SiON layer, and the schematics, b and d, are shown on the right-hand side of each TEM image. traces were monitored and the results for the two different linewidths are shown in Fig. 5. Compared with the 125 nm lines, the 60 nm lines showed a more progressive resistance increase followed by an abrupt increase. Such a behavior indicates that as the void forms and grows in the M1 line, the Ta barrier at the via bottom serves as a redundant layer for current flow. In contrast, all the 125 nm lines without SiON filling showed an abrupt resistance increase indicating void formation underneath the via. In this case, since the Ta barrier at the via bottom did not completely cover the linewidth to serve as a redundant layer, the line failed abruptly as observed. Since the current density in the M1 trench was kept constant for both samples with different linewidths, a higher current was applied to the wider, 125 nm line. Consequently, the current density in the via was higher for the wider line than for the finer 60 nm line. This resulted in a higher current crowding for the wider line near the via bottom which can also contribute to the shorter EM lifetime for the wider lines. An EM failed sample with 60 nm line was examined using cross-sectional TEM. As shown in Fig. 6, a large void near the cathode was found along the M1 line as highlighted by a white boundary while the via bottom was intact. This demonstrates a strong-mode trench voiding mechanism with the void growing extensively in the metal trench region. FIG. 5. Resistance changes of downstream EM test structures a with SiON filling layer 60 nm and b without SiON filling layer 125 nm. EM test was performed at 270 C, with a current density of 1.0 MA/cm MA/cm 2. The trench widths for these line structures before SiON filling were 125, 175, and 250 nm, respectively. The CDF plots obtained for EM tests performed under the downstream electron flow condition are shown in Fig. 7. The results revealed that the CDF was independent of the M1 linewidths employed. This is consistent with that predicted by Eq. 1 for a strong mode EM failure with void formation in line trenches driven by interfacial mass transport, where the EM lifetime is only related to the metal line thickness, h. In this case, since the line thicknesses are identical for these test structures, their lifetimes should be the same under identical test conditions as observed in Fig. 7. This mode of void formation was confirmed for the SiON filling samples as TEM revealed voids present in the M1 trench as shown in Fig. 6. In this case, the L cr can be set equal to the via diameter where intrinsic void forms and grows at the cathode end. B. Linewidth effect on EM among SiON-filled samples To understand the linewidth scaling effect on EM for the samples with a SiON trench-filling layer, EM tests were performed for M1 lines with three different widths of 60, 110, and 185 nm at 300 C and a current density of FIG. 6. TEM image showing a large cathode void in M1 trench for an EM failed 60 nm wide interconnect.

4 Pyun et al. J. Appl. Phys. 102, FIG. 7. CDF plots with different line widths for downstream electron flow. EM tests were performed at T=300 C and j=1.0 MA/cm 2. C. Early failure behavior To investigate the SiON filling process effect on early failure, EM tests were performed using multilinked EM test structures for downstream electron flow. The CDF plots of the EM test results, together with Monte Carlo simulation, are shown in Fig. 8 for the 60 nm wide Cu interconnects with SiON filling. The CDF plots demonstrated approximately straight-line behavior for multilinked structures with N =1, 10, and 100, indicating a monomodal failure distribution. This result implies that no extrinsic factors such as processinduced defects affected this failure. This suggests that process-induced defects in the via bottom, which are a primary cause of early failures, are no longer a dominant factor affecting failure due to the distinct via/ M1 interface. The reason for the shortest lifetime for the N=100 samples is that with the increasing number of line segments, the probability of failure in any of those segments will increase. The experimental CDF plots did not correspond very well with the Monte Carlo simulation result, suggesting statistical variations in line dimension and geometry due to aggressive line scaling. D. Activation energy and current density exponent To measure the activation energy and current density exponent, EM tests were performed at various temperatures FIG. 9. Electromigration lifetimes as a function of test temperature for the Cu interconnects with different linewidths under the current density of 1.0 MA/cm 2. The activation energies were found to be 0.79 and 0.80 ev for the fine lines and standard lines, respectively. ranging from 210 to 290 C. Based on the EM lifetime data, the activation energies for Cu interconnects with 60 and 125 nm lines were determined and the results are shown in Fig. 9. The activation energies, Q, were obtained from fitting the experimental data to the Black s equation 8 t 50 = Aj n exp Q/kT, where A is a constant, j is the current density, n is the current density exponent, and Q is the activation energy for EM. The activation energies were found to be to the same, 0.80 ev, indicating a similar interfacial diffusion behavior in both test structures which was not affected by the SiON filling process. 9,10 Current density exponent n values, using Eq. 2, were obtained for the 60 and 125 nm lines at 240 C. The results are shown in Fig. 10. The current exponents were found to be 1.44 and 1.88 for 125 and 60 nm lines, respectively, and the difference is deemed insignificant. In the case of Al interconnects, it is generally known that EM failure controlled by void growth shows a current exponent of This implies that migration of void flux is directly proportional to the electron flux. In contrast, EM failure controlled by void nucleation yields a current exponent of 2. 12,13 Therefore, all 2 FIG. 8. CDF plots of multilinked EF structures with different number of line segments for down stream electron flow. EM tests were performed at T=240 C and j=1.0 MA/cm 2. FIG. 10. Electromigration lifetimes as a function of current density for the Cu interconnects with different linewidths at T=240 C. The current density exponent values n were found to be 1.88 and 1.44 for the fine lines and standard lines, respectively.

5 Pyun et al. J. Appl. Phys. 102, EM failures which have the current exponent value falling inbetween 1 and 2 are controlled by both nucleation and growth of voids. 14,15 The measured n values are in this general range. IV. CONCLUSIONS Ultrafine M1 Cu interconnects were fabricated by dualdamascene process using a trench-filling method with SiONfilling layer and their EM reliability was investigated. Samples with 60 nm wide lines showed longer lifetimes, which can be attributed to the distinct interface structure between the via and M1. For the SiON-filled samples, EM test results using multilinked structures were signified by the absence of extrinsic early failure. This result suggests that the processing defects, which are the most probable cause for early failures, were not a dominant factor due to the distinct via/ M1 interface structure. The activation energies were found to be around 0.80 ev for both fine lines and standard lines, indicating a similar interfacial diffusion behavior in both structures which is not affected by the SiON filling process. The n values for 60 and 125 nm lines were found to be similar. ACKNOWLEDGMENTS This work was supported by the Semiconductor Research Corporation and the SEMATECH Advanced Materials Research Center. 1 E. Liniger, L. Gignac, C.-K. Hu, and S. Kaldor, J. Appl. Phys. 92, R. Rosenberg, D. C. Edelstein, C.-K. Hu, and K. P. Rodbell, Annu. Rev. Mater. Sci. 30, K. N. Tu, J. Appl. Phys. 94, R. Havemann and J. Hutchby, Proc. IEEE 89, J. W. Pyun, X. Lu, S. Yoon, N. Henis, K. Neuman, K. Pfeifer, and P. S. Ho, Pproceedings of 2005 IEEE International Reliability Physics Symposium, 43th Annual, 2005, pp E. T. Ogawa, K.-D. Lee, V. A. Blaschke, and P. S. Ho, IEEE Trans. Reliab. 51, C.-K. Hu, D. Canaperi, S. T. Chen, L. M. Gignac, B. Herbst, S. Kaldor, M. Krishnan, E. Liniger, D. L. Rath, D. Restaino, J. Rubino, S.-C. Seo, A. Simon, S. Smith, and W.-T. Tseng, Proceedings of 2004 IEEE International Reliability Physics Symposium, 42nd Annual, 2004, pp J. R. Black, IEEE Trans. Electron Devices 16, J. R. Lloyd, J. Phys. D 32, R K.-D. Lee, E. T. Ogawa, S. Yoon, X. Lu, and P. S. Ho, Appl. Phys. Lett. 82, J. J. Clement and J. R. Lloyd, J. Appl. Phys. 71, M. Shatzkes and J. R. Lloyd, J. Appl. Phys. 59, J. R. Lloyd, J. Appl. Phys. 69, A. S. Oates, Appl. Phys. Lett. 66, D. Padhi and G. Dixit, J. Appl. Phys. 94,

Effect of barrier process on electromigration reliability of Cu/porous low-k interconnects

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