Failure Mechanism of Electromigration in Via Sidewall for Copper Dual Damascene Interconnection

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G782 0013-4651/2006/153 8 /G782/5/$20.00 The Electrochemical Society Failure Mechanism of Electromigration in Via Sidewall for Copper Dual Damascene Interconnection Y. L. Hsu, Y. K. Fang, z Y. T. Chiang, S.

1 G /2006/153 8 /G782/5/$20.00 The Electrochemical Society Failure Mechanism of Electromigration in Via Sidewall for Copper Dual Damascene Interconnection Y. L. Hsu, Y. K. Fang, z Y. T. Chiang, S. F. Chen, C. Y. Lin, T. H. Chou, and S. H. Chang VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan We have studied the effects of step coverage of TaN diffusion barrier layer on Cu electromigration EM in detail and found that the EM lifetime strongly depends on the step coverage of via sidewall thickness. We conclude that the EM failures are caused by mechanisms such as unbalanced thermal stress, thermal expansion between Cu and TaN, and surface morphology of TaN including surface roughness and grain sizes. These factors were investigated and evaluated systematically through transmission electron microscopy, field emission scanning electron microscopy, and atomic force microscopy. Furthermore, we also address the enhancement of step coverage to examine Cu EM performance by performing a lifetime experiment, and suggest that the step coverage of TaN barrier becomes an important process integration subject for sub-0.13 m and beyond technologies The Electrochemical Society. DOI: / All rights reserved. Manuscript submitted February 24, 2006; revised manuscript received April 17, Available electronically June 16, As device feature size shrinks to the deep sub-0.13 m and beyond nodes, Cu is widely used as the interconnect metal with dual damascene process for its better electrical conductivity. In practice, TaN has been employed as an effective barrier layer between the upper Cu layers and the lower local interconnect layers because of its good adhesion to the SiO 2, 1 and is usually deposited by sputtering physical vapor deposition PVD. However, with deep submicrometer complementary metaloxide semiconductor CMOS technology, the aspect ratio AR of via holes in dual damascene becomes very high and causes the sputtered TaN to form poor step coverage. Then, the poor step coverage causes high electrical resistance in metal lines and a greater chance of mechanical cracking. In addition, it enhances electromigration EM failure significantly. Hence EM testing associated with multiple metals and via hole levels has been used to qualify its performance of metal interconnection reliability. 2,3 In the past, EM reliability issues of Cu interconnects with signal damascene have been investigated extensively and attributed to various factors, such as local defects from processes, line width and via diameter, adhesion strength of barrier metal/cu interface, and contaminations from via formation process. 4-9 But very few studies of EM failure on poor step coverage of barrier layer for Cu dual damascene process have been reported. In this work, we systematically studied the EM failure of Cu interconnect processes affected by the step coverage of TaN barrier layer in via holes and contributed to the four different mechanisms, i.e., unbalanced thermal stress; thermal expansion between Cu, TaN and FSG; TaN surface morphology; and TaN grain sizes and grain boundaries. Experimental In this study, samples of EM test structures were prepared on 200 mm 100 p-type cm silicon substrates with a sub m CMOS technology. The test structures inset of Fig. 1 consisted of metal-1 and metal-2 chains with 0.22 m width, 100 m length, and 0.21 m diam via holes. We used a single damascene process for metal-1 Cu layer and dual damascene process for metal-2 Cu layer. To form the metal-1, the intermetal dielectric IMD consisted of a 250 nm thick fluorine silicon glass FSG and a 30 nm thick Si 3 N 4 as trench-1 etch stop layer were deposited by plasma-enhanced chemical vapor deposition PECVD and patterned trenches by conventional lithography. We then formed trenches by sputtering a 25 nm thick TaN barrier layer, a 150 nm Cu seed layer, electroplating Cu, and removing redundant Cu by chemical mechanical planarization CMP sequentially. Next, to form metal-2, a 50 nm thick SiN layer was deposited just after the CMP z ykfang@eembox.ee.ncku.edu.tw process to serve as Cu cap and via etch stop layer. After that, layers of 40 nm FSG, 30 nm SiN, 480 nm FSG, and 50 nm SiON were deposited as the IMD-2 in which 30 nm SiN serve as trench-2 stop layer. Then, we patterned via and metal-2 trench and formed them through the processes use for metal-1. In EM test, the samples resistances were examined after a constant current of 2 ma/cm 2 at 350 C stress for fixed periods. The failure criterion is defined as 10% increased resistances of the samples after stress. The total stress time to fail is called the time-to-failure TTF for each sample. Based on the TTF, we plot the cumulative failure distribution. Furthermore, atomic force microscopy AFM, transmission electron microscopy TEM, and field emission scanning electron microscopy FESEM were used to measure barrier layer surface roughness, step coverage of TaN in via holes, and the grain sizes of TaN barrier layers, respectively. Results and Discussions Figure 1 gives the cumulative failure distribution of EM lifetime for typical Cu interconnection lines failed after 19 to 50 h stress for EM test. The interconnect schemes of top view and side view are presented in the inset. The cumulative failure distribution is plotted by measurement of each sample s TTF and then calculates the TTF distribution percentage for all samples. With the distribution, we can obtain the values of t 0.1 time for 0.1% of lines to fail and t 50 time for 50% of lines to fail and maximum current density J max with Black s law. 10 These data are commonly used for Cu interconnects Figure 1. Cumulative distributions of Cu dual damascene interconnect passed square and failed circle after h EM stress. Inset: top and side view of the test structure schemes.

G783 Table I. Time to failure (TTF) for various step coverage percentages. Sigma, t 50,t 0.1,andJ max are standard deviation, time for 50% and 0.

49 6.20 7.72 J max A/cm 2 3.72E + 05 8.22E + 05 1.68E + 06 1.87E + 06 reliability evaluation. 10,11 As seen, the t 0.

Clearly, Cu voids were found in the corner and via sidewall approaching the bottom, which possess the feature of thinner TaN barrier layer caused by poor step coverage.

2 G783 Table I. Time to failure (TTF) for various step coverage percentages. Sigma, t 50,t 0.1,andJ max are standard deviation, time for 50% and 0.1% of the line to failure and maximum current density, respectively. Step Coverage Results 22.6% 23.7% 31.3% 34.9% Sigma t 50 hours t 0.1 hours J max A/cm E E E E + 06 reliability evaluation. 10,11 As seen, the t 0.1 and t 50 of lines are far less than that of passed samples see Table I for details. TEM failure analysis for the opened Cu interconnects in EM test is presented in Fig. 2a. Clearly, Cu voids were found in the corner and via sidewall approaching the bottom, which possess the feature of thinner TaN barrier layer caused by poor step coverage. However, the corner also has issues of difficult deposition and high stress thus enhancing formation of large void. Additionally, from other structures we can find the similar results Fig. 2b-d. We have attributed four failure mechanisms with schematic diagrams to illustrate the EM failure as follows. First, during the EM testing, current crowding effect and current flow induced heating on via hole generate thermal stresses its directions and magnitudes for various layers are indicated in Fig. 3 with arrows. Under a constant testing temperature, the thermal stress is larger than the intrinsic stress and becomes dominant. Its magnitude can be calculated with 12 T = T 0 T * * E 1 where T,T 0,T,, and E are thermal stress, stress free temperature, EM testing temperature, the difference of thermal expansion coefficient, and the Young s modulus, respectively. The thermal expansion coefficient CTE /the young s modulus of Cu, TaN, and FSG are C 1 /125, C 1 /457, and C 1 /80, respectively. 13 Transferring these data into Eq. 1, one can find that Cu possesses the largest thermal stress and the smallest for FSG, thus generating an unbalanced stress upon the TaN Figure 3. Schematic models illustrating unbalanced thermal stress induced EM failure in the sidewall of copper via for a thin and b thick TaN barrier. Figure 2. TEM cross-sectional images of four failed samples after h EM testing. Void always found in via sidewall and bottom corner. Figure 4. Vacancies formation due to tensile stress caused by unbalanced thermal expansion coefficient induced EM failure in the sidewall of copper via for a thin and b thick TaN barrier.

G784 Figure 5. AFMs, the measured surface roughness R surface of TaN barrier, and model illustrating heat dissipation flow path for a thin and b thick TaN barrier, respectively.

However, the same phenomenon was not found for a thick and conformal TaN barrier layer Fig. 3b because it is strong enough to resist the cracking. Second, as shown in Fig.

3 G784 Figure 5. AFMs, the measured surface roughness R surface of TaN barrier, and model illustrating heat dissipation flow path for a thin and b thick TaN barrier, respectively. barrier layer to be broken at the weakest point. Simultaneously, the Cu atoms energized by heat diffuse into FSG through the broken barrier and create a void in via hole as shown in Fig. 3a. However, the same phenomenon was not found for a thick and conformal TaN barrier layer Fig. 3b because it is strong enough to resist the cracking. Second, as shown in Fig. 4, the difference of thermal expansion coefficient between TaN layer and Cu layer also causes a tensile stress to the Cu layer and bends the layers outbound directions and toward ends under the high-temperature EM testing, especially for thinner TaN barrier layer. The heat-enhanced tensile stress then assists the diffusion of Cu atoms, thus creating small vacancies in the Cu/TaN interface during EM testing. At the same time, these vacancies transport along with the interface and coalesce into voids in via hole as reported previously. 14 Third, because via is formed by reactive ion etch RIE which always causes a very rough surface after etching, 15,16 the thin TaN film cannot cover the rough surface of via and confirmed by AFM analysis. Figure 5 gives the AFM micrographs and the measured surface roughness R surface for a thin and b thick TaN barrier layers, respectively. The thin TaN barrier layer with R surface = nm is 137% rougher over the thick one with R surface = nm. The rough TaN surface touches the Cu layer with less area, thus retarding the heat dissipation 17 of the Cu through TaN barrier layer, then the accumulated heat aggravates the EM failure as illustrated in the insets of Fig. 5. Finally, as reported previously, 18 the grain size of the deposited TaN film is strongly affected by strain stress. On the other hand, AFM Fig. 5 shows that the thicker the film is, the smoother is the Figure 6. FESEM top views of TaN barrier layer for a thin and b thick TaN barrier, respectively. Inset: Models illustrating Cu atom diffusion through grain boundary.

G785 Figure 7. TEM cross-sectional micrographs of TaN diffusion barrier layers in Cu dual damascene interconnect for step coverage a 23.7% and b 34.9%. film morphology.

4 G785 Figure 7. TEM cross-sectional micrographs of TaN diffusion barrier layers in Cu dual damascene interconnect for step coverage a 23.7% and b 34.9%. film morphology. We also found that the smoother film morphology offers little stress to degrade the growing grain. 19 Therefore, the thick and conformal TaN posses larger grains and can be certified by the FESEM micrographs for thin and thick TaN barrier layers presented in Fig. 6a and b, respectively. It has been reported that EM flux through the Cu-barrier-dielectric interface dominates all possible EM flux diffusion paths, including grain boundaries, metalbarrier interfaces, and dielectric-barrier interfaces in Cu dual damascene, which strongly depends on the grain size of barrier layer. 20,21 Hence, the Cu atoms diffuse through fewer grain boundaries for a thick TaN barrier layer and attain higher EM performance. Furthermore, we found that the major factor to affect thickness of the TaN barrier layers in via the sidewall is the TaN sputtering process with various step coverage percentages. Figure 7 gives the TEM cross-section micrographs of a poor step coverage 23.7% and b conformal step coverage 34.9% of TaN barrier layer in via hole, respectively. The corresponding TTF of EM testing for various percentages are shown in Fig. 8 and the results are summarized in Table I. The TTF t 0.1 and t 50 of Cu interconnects in the EM test is proportional to the step coverage percentages of TaN barrier layer and increases rapidly from step coverage 22.6% to 34.9%. On the other hand, 10% increasing in step coverage results in more than Figure 8. EM lifetime distributions of Cu dual damascene interconnect including via with various TaN barrier sidewall step coverage. 100% improvement for maximum current density J max. This implies that high step coverage of TaN barrier layer would be the most important factor for dual damascene Cu interconnects reliability performance. Conclusion We have studied the EM lifetime of Cu interconnects in detail by AFM, SEM, and TEM analysis and found that it strongly depends on the step coverage of TaN barrier layer in via holes. Additionally, we confirm that the EM failure mechanisms are attributed to the unbalanced thermal stress, thermal expansion between copper and TaN, and TaN surface morphology, including surface roughness and grain size effects. Currently, enhancing the TaN thickness is believed to help the EM performance of Cu dual damascene interconnection but it also increases the resistance of via holes. However, our findings showed that enhancing the step coverage by maintaining via sidewall thickness uniformity should become an important process integration subject for sub-0.13 m and beyond technologies. Acknowledgments The authors thank the members of Taiwan Semiconductor Manufacturing Company, Limited, for technical support and valuable discussions. The National Science Council supported this work under contract no. NSC E National Cheng Kung University assisted in meeting the publication costs of this article. References 1. C. Bruynseraede, Zs. Tokei, F. Iacopi, G. P. Beyer, J. Michelon, and K. Maex, in IEEE 43rd Annual Int. Reliability Physics Symposium, IEEE, p C. M. Tan, A. Roy, A. V. Vairagar, and S. G. Mhaisalkar, IEEE Trans. Device Mater. Reliab., 5, J. B. Lai, J. L. Yang, Y. P. Wang, S. H. Chang, R. L. Hwang, and C. S. Hou, in Symposium on VLSI Technology System Applications, IEEE, p A. H. Fischer, A. V. Glasow, S. Penga, and F. Ungar, in Proceedings of the IEEE 2002 International Inteerconnect Technology Conference, IEEE, p T. Suzuki, S. Ohtsuka, A. Yamanouse, T. Hosoda, Y. Matsuoka, K. Yanai, H. Matsuyama, H. Mori, N. Shimizu, T. Nakamura, S. Suatani, K. Shono, and H. Yagi, in Proceedings of the IEEE 2002 International Interconnect Technology Conference, IEEE, p K. Ishikawa, T. Iwasaki, T. Fujii, N. Nakajima, M. Miyauchi, T. Ohshima, J. Noguchi, H. Aoki, and T. Saito, in Proceedings of the IEEE 2003 International Interconnect Technology Conference, IEEE, p T. C. Wang, T. E. Hsieh, M. T. Wang, D. S. Su, C. H. Chang, Y. L. Wang, and J. Y. Lee, J. Electrochem. Soc., 152, K. Yoshida, T. Fujimaki, K. Miyamoto, T. Honma, H. Kaneko, H. Nakazawa, and

5 G786 M. Morita, Tech. Dig. - Int. Electron Devices Meet., 2002, M. Traving, G. Schindler, G. Steinlesberger, W. Steinhogl, and M. Engelhardt, in Advanced Metallization Conference 2004, IEEE, p K. Banerjee, A. Mehrotra, W. Hunter, K. C. Saraswat, K. E. Goodson, and S. S. Wong, in IEEE 38th Annual Int. Reliability Physics Symposium, IEEE, p C. Y. Chang and S. M. Sze, ULSI Technology, McGrawn-Hill, New York Y. J. Park, K. D. Lee, and W. R. Hunter, in IEEE 43rd Annual Int. Reliability Physics Symposium, IEEE, p S. Orain, J-C. Barbe, X. Fedrspiel, P. Legallo, and H. Jaoduen, in IEEE 5th International Conference on Thermal and Mechanical Simulation and Experiments in Micro-Systems, IEEE, p E. T. Ogawa, J. W. McPherson, J. A. Rosai, K. J. Dicherson, T. C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonified, and J. C. Ondrusek, in IEEE 40th Annual Int. Reliability Physics Symposium, IEEE, p S. B. Kim, H. Seo, Y. Kim, and H. Jeon, J. Korean Phys. Soc., 41, K. S. Chen, A. A. Ayón, X. Zhang, and S. M. Spearing, J. Microelectromech. Syst., 11, T. Y. Chiang, K. Banerjee, and K. C. Saraswat, IEEE Electron Device Lett., 23, D. P. Field, J. M. Yanke, E. V. Mcgowan, and C. A. Michaluk, J. Electron. Mater., 34, C. Y. Lin, Y. K. Fang, S. F. Chen, C. S. Lin, T. H. Chou, S. B. Hwang, J. S. Hwang, and K. I. Lin, J. Non-Cryst. Solids, 352, C. D. Hartfield, E. T. Ogawa, Y. J. Park, and T. C. Chiu, IEEE Trans. Device Mater. Reliab., 4, E. T. Ogawa, K. D. Lee, V. A. Blaschke, and P. S. Ho, IEEE Trans. Reliab., 51,

Electromigration behavior of 60 nm dual damascene Cu interconnects

JOURNAL OF APPLIED PHYSICS 102, 093516 2007 Electromigration behavior of 60 nm dual damascene Cu interconnects Jung Woo Pyun, a Won-Chong Baek, Lijuan Zhang, b Jay Im, and Paul S. Ho Microelectronics Research