Slip Formation in 300-mm Polished and Epitaxial Silicon Wafers Annealed by Rapid Thermal Annealing

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1 Journal of the Korean Physical Society, Vol. 46, No. 4, April 2005, pp Slip Formation in 300-mm Polished and Epitaxial Silicon Wafers Annealed by Rapid Thermal Annealing Kyu-Chul Cho and Hyeong-Tag Jeon Department of Materials Science & Engineering, Hanyang University, 17 Haengdang-Dong, Seoungdong-Gu, Seoul Jea-Gun Park Nano-SOI Process Laboratory, Hanyang University, 17 Haengdang-Dong, Seoungdong-Gu, Seoul (Received 2 December 2004) The mechanism of slip generation in 300-mm polished and epitaxial wafers after rapid thermal annealing (RTA) was investigated. In an RTA system with three supporting pins arranged symmetrically, slip was produced above 1150 C for a polished wafer and above 1100 C for a p/p epitaxial wafer. The length and the density of slip for the p/p epitaxial wafer were both much higher than those for the polished wafer. The deposition of a low-temperature thermal oxide on the backside of the epitaxial wafer was effective for reducing slip formation. The slip generation in both types of wafers strongly depended on the annealing temperature and the annealing time; that is, higher annealing temperatures and longer annealing times in RTA led to longer slip with higher density. PACS numbers: 81, 65 Keywords: Slip, Dislocation, RTA, Epitaxial, 300 mm, XRT I. INTRODUCTION The transition from 200-mm to 300-mm polished silicon and to epi-silicon epitaxial wafers is currently a major issue in the semiconductor industry. To meet the industry s requirements, the wafer size must be increased in order to reduce the manufacturing cost, and the wafer must have fewer defects, such as crystal-originated particles (COPs) on the surface and oxygen precipitates near the surface [1]. For these reasons, the standard wafer size is being increased from 200 to 300 mm, and the epitaxial wafer has been proposed as an alternate candidate for achieving a perfect wafer with no COPs or oxygen precipitates in the devices active regions. By increasing the wafer diameter from 200 to 300 mm, however, the gravitational and thermal stresses are drastically increased, leading to slip generation during heat treatment [2]. The presence of slip dislocations in a wafer is detrimental because they cause wafer warpage, resulting in pattern misalignment and substrate leakage from devices [3, 4]. The thermal-stress-induced slip strongly depends on the temperature variation within a wafer and the ramp-up and the ramp-down rates. While rapid thermal annealing (RTA) is likely to generate slip [5], it is an parkjgl@hanyang.ac.kr; Fax: essential process in ULSI technology for dopant activation after implantation, donor killing, and film densification [6 8]. Particularly, an additional high-temperature RTA of a 300-mm wafer prior to device fabrication has been recently proposed for extreme proximity gettering for advanced semiconductor devices [9]. In this study, we mainly focused on the effects of the annealing temperature and time on slip formation in 300-mm polished and epitaxial silicon wafers, and we compared the polished and epitaxial wafers in terms of slip performance after RTA. In addition, we examined the influence of the ramp-up and the ramp-down rates on slip formation. II. EXPERIMENT The samples used in this experiment were divided into three groups. The first group contained polished wafers grown by using the Czochralski method, which were p- type, 10 Ω-cm, 300-mm-diameter silicon wafers with an interstitial oxygen concentration of 12.5 ppma (ASTM F ). The second and third groups contained epitaxial wafers. The thickness of the p/p- epitaxial layer, the resistivity, and the diameter were 4 m, 10 Ω-cm, and 300 mm, respectively. The epitaxial layer was grown by using the edge-ring support method at 1100 C for

2 Journal of the Korean Physical Society, Vol. 46, No. 4, April 2005 min with a ramp-up/-down rate of 5 C/sec. The wafers in the second and third groups were identical other than a 4000-Å low-temperature thermal oxide (LTO) film on the backsides of the wafers in the third group. The LTO film was deposited on some of the epitaxial wafers in order to investigate whether the deposition of a compressive film on the backside would decrease the slip generation in a 300-mm epitaxial wafer [10]. The wafers in all three groups were subjected to RTA. The RTA system used in this experiment had an inner-symmetric arrangement with three supporting pins at 0.7r, where r is the radius of a 300-mm wafer. Five different sets of experiments were performed to examine the dependencies of slip formation on the annealing temperature, the annealing time, the ramp-up rate, and the ramp-down rate in a nitrogen ambient. First, the RTA temperature was varied from 1000 to 1250 C with ramp-up and ramp-down rates of 50 C /s and an annealing time of 60 seconds. In the second and third experiments, the annealing time was varied from 10 to 50 seconds at 1100 C and 1200 C, respectively, with a ramp-up and ramp-down rate of 50 C/s. For the fourth experiment, the ramp-up rate was varied from 20 to 80 C/s at 1200 C for 60 seconds with a fixed ramp-down rate of 50 C/s. Finally, the ramp-down rate was varied from 20 to 80 C/s at 1200 C with a fixed ramp-up rate of 50 C/s and an annealing time of 60 seconds. Slip was characterized by X-ray topography analysis. To evaluate the degree of slip formation, we carefully measured the slip length and the area of the slip. Since the measurement of the dislocation density is very difficult, the slip areas were estimated from dislocation densities obtained by computer image processing. We regarded larger slip areas as leading to higher dislocation densities. III. EXPERIMENTAL RESULTS AND DISCUSSION The slip length at the edge of a wafer increases with the annealing temperature. In a RTA system, the temperature is uniform from the wafer center to a specific diameter and then drastically drops near the wafer edge, although heat is uniformly irradiated on the wafer. The radial temperature drop produces a dramatic increase in the thermal tensile stress near the edge [11]. Slip is generated when a dramatic increase in the thermal tensile stress exceeds the yield stress for plastic deformation, which is greater than 1.0 MPa in a 300-mm wafer [12]. It is intuitive that the thermal tensile stress induced by a dramatic temperature drop near the edge of a wafer increases with the wafer diameter. In the RTA system used in this experiment, a wafer s weight is concentrated on three supporting pins. Slips begin to be produced at the pins because of the RTA-induced thermal stress combined with the gravitational stress. Figure 1 shows X-ray topography (XRT) images of Fig. 1. X-ray topography (XRT) images of wafers treated by rapid thermal annealing (RTA). The wafers were annealed at each temperature for 60 seconds with a ramp-up and rampdown rate of 50 C/s. RTA-treated wafers for various annealing temperatures. In the case of the polished wafers, slip began to occur at about 1150 C and was produced at both the edges and at the three supporting-pin positions along the <110> directions in the {111} planes. On the other hand, for the p/p- epitaxial wafers with and without a LTO film on the backside, slip began to occur at about 1100 C in the same positions as in the polished wafers. Figure 2 shows the area of dislocation as a function of annealing temperature for the wafers shown in Fig. 1. The area of dislocation, corresponding to the slip density, increased exponentially with the RTA temperature. Although the slip lengths were similar in all three groups (see Fig. 1), the areas of dislocation were much higher in the epitaxial wafers than in the polished wafers. In addition, the areas of dislocation in the epitaxial wafers without LTO films were a little higher than those in the wafers with LTO films. This result indicates that depositing a LTO film on the backside of a wafer is somewhat effective in reducing slip generation in RTA treatment of 300-mm wafers. To predict the slip length after the RTA treatment, we tried to calculate it in a 300-mm polished wafer according to the theory of heat conduction and thermal radiation. Generally, the stresses causing slip generation are gravitational and thermal, resulting from a wafer s own weight and the radial temperature difference between the wafer center and edge, respectively. While the

3 Slip Formation in 300-mm Polished and Epitaxial Silicon Wafers Annealed Kyu-Chul Cho et al Fig. 2. Area of dislocation as a function of the annealing temperature for the wafers shown in Fig. 1. Fig. 3. Measured and simulated slip lengths of the polished wafers thermal stress depends on the furnace and the heating method, the gravitational stress strongly depends on the method used to support the wafer. To simplify the calculation, however, we neglected the gravitational stress at the edge of the wafer, since it rapidly decreases with increasing distance from a supporting pin [10]. The temperature distribution in a wafer uniformly irradiated on its surface is described by the Equation [5] T (r) = T 0 H 0λ K I 0 (r/λ) I 1 (a/λ) (1) where H 0, K, a, I 0, and I 1 are the radiation rate from the surface of the wafer at T 0, the thermal conductivity at T 0, the wafer radius, and modified Bessel functions of the first kind of orders zero and one, respectively. The parameter λ gives a measure of the extension of the cooler region at the wafer edge and is defined as [5] λ = [Kh/(8σεT 3 0 )] 1/2 (2) where h, σ and ε are the wafer thickness, the Stefan- Boltzman constant, and the silicon emissivity, respectively. At the edge of the wafer, the maximum thermal stresses according to the radial temperature distribution given by Eq. 1 can be expressed by the following Equation [5]: τ max = τ max θθ αeh 0λ 2 K ( 1 λ 2 a ) (3) where a. is the thermal expansion coefficient and E is Young s modulus. Then, the resolved shear stress τ s (in MPa) at the edge of the wafer is given as τ s = τ max θθ cos λ cos ϕ (4) where cos λ cos ϕ is the Schmidt factor and is equal to 0.408, which corresponds to the slip system S 1 given in Ref. 4. The dislocation velocity (ν) is defined as [13] ν(τ, T ) = ν 0 τ s exp[ U kt ] (5) Fig. 4. XRT images of RTA-treated wafers annealed at 1100 C for 60 seconds with a ramp-up and ramp-down rate of 50 C/s. where ν 0 (m 3 /MN/s) is and U (ev) is the activation energy of the dislocation velocity [14]. The slip length can be calculated from the dislocation velocity times the duration of the thermal process. Figure 3 shows the simulated and measured slip lengths for the polished wafers as a function of annealing temperature for the wafers shown in Fig. 1. Note that the measured slip lengths correspond to the maximum values of

4 Journal of the Korean Physical Society, Vol. 46, No. 4, April 2005 Fig. 5. XRT images of RTA-treated wafers annealed at 1200 C for 60 seconds with a ramp-up and ramp-down rate of 50 C/s. Fig. 7. XRT images of RTA-treated wafers annealed at 1200 C for 60 seconds with a ramp-up rate of 50 C/s. Fig. 6. Area of dislocation as a function of the annealing time for the wafers shown in Fig. 5. each temperature. The simulated slip lengths increased with the RTA temperature and were consistent with the experimental data. This result indicates that the RTA induced stress is mainly associated with thermal stress induced by the radial temperature difference between the wafer center and edge. Figure 4 shows XRT images of wafers annealed at 1100 C with various annealing times. As we have already seen from Fig. 1, the polished wafers showed no slip at this temperature. Both types of epitaxial wafers (with and without LTO), however, showed little or no slip until after 20 seconds of annealing at 1100 C, which we believe to be the slip-producing temperature, according to Fig. 1. Figure 5 shows XRT images of wafers annealed at 1200 C with various annealing times. The polished wafers showed no slip at 10 seconds and only one small area of slip near a pin at 20 seconds, while the epitaxial wafers exhibited slip at all annealing times from 10 to 50 seconds. Based on these results, as illustrated by Figs. 4 and 5, we can achieve RTA without slip generation at 1100 C and 1200 C for epitaxial and polished wafers, respectively, if we decrease the annealing time to 10 seconds. Figure 6 shows the area of dislocation as a function of annealing time for RTA at 1200 C. The epitaxial wafers showed a clear correlation between the annealing time and the area of dislocation; i.e., a longer annealing time meant a larger area of dislocation. As with the annealing-temperature dependency of the area of dislocation, the wafers with LTO films had lower areas of dislocation. Figures 7 and 8 show XRT images of wafers treated with various ramp-up and ramp-down rates in RTA at 1200 C for 60 seconds. Figure 9 shows the areas of dislocation for the wafers shown in Figs. 7 and 8. As can be observed from these figures, none of the three

5 Slip Formation in 300-mm Polished and Epitaxial Silicon Wafers Annealed Kyu-Chul Cho et al types of wafers exhibited any dependency of slip generation on the ramp-up or the ramp-down rate. The area of dislocation was, thus, independent of the ramp-up and the ramp-down rates. This means that slip generation during RTA is determined by the annealing temperature and time, or more specifically, by the highest temperature during the thermal process and the duration at that temperature. Similar to the annealing-temperature and annealing-time dependencies, the deposition of a LTO film on the backside of a wafer led to less severe dislocation performance than in the non-lto wafers. IV. CONCLUSION Fig. 8. XRT images of RTA-treated wafers annealed at 1200 C for 60 seconds with a ramp-down rate of 50 C/s. Rapid thermal annealing (RTA) of 300-mm wafers induced heavy slip at the three supporting pin positions and the wafer edge. The length and the density of slip strongly depended on the annealing temperature and the annealing time; i.e., higher annealing temperature and longer annealing time led to higher slip length and density. On the other hand, the length and the density of slip did not exhibit strong dependencies on the ramp-up and the ramp-down rates in RTA at high temperatures. In particular, the slip length and density were much higher for p/p- epitaxial wafers than for polished wafers. This suggests that the additional heat treatment in an epitaxial reactor at 1100 C for 30 min introduced residual stresses in the wafers. Thus, the achievement of extreme proximity gettering in the 300-mm p/p- epitaxial wafer would be much more difficult for advanced semiconductor devices because of easier production of slip. The mechanism by which p/p- epitaxial wafers produce greater slip than polished wafers needs to be studied further. In addition, we need more to verify that the slip length in a polished wafer after RTA treatment can be successfully predicted by using a model. ACKNOWLEDGMENTS This work was supported by the Korea Ministry of Science and Technology through the National Research Laboratory (NRL) Program. We also thank Sumitomo Mitsubishi Silicon Corporation for their help in performing the experiment. REFERENCES Fig. 9. Area of dislocation as a function of the (a) rampup rate and the (b) ramp-down rate for the wafers shown in Figs. 7 and 8, respectively. [1] J. G. Park and K. D. Kwack, J. Korean Phys. Soc. 38, 841 (2001). [2] R. Takeda, P. Xin, J. Yoshikawa, Y. Kirino, Y. Matsushita, Y. Hosoki, N. Tsuchiya and O. Fujii, J. Electrochem. Soc. 144, L280 (1997).

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