PROTOCOL DEVELOPMENT FOR TESTING SOLDER RELIABILITY IN COMBINED ENVIRONMENTS

Transcription

1 PROTOCOL DEVELOPMENT FOR TESTING SOLDER RELIABILITY IN COMBINED ENVIRONMENTS John McMahon 1, Joseph Juarez 2, Polina Snugovsky 1, Jeffrey Kennedy 1, Milea Kammer 2 Ivan Straznicky 3, David Hillman 4, David Adams 4, Stephan Meschter 5, Subramaniam Suthakaran 1, Russell Brush 1, Doug Perovic 6 1 Celestica, 2 Honeywell, 3 Curtiss Wright, 4 Rockwell Collins, 5 BAE Systems, 6 University of Toronto ABSTRACT This paper describes a proposed method for investigating solder joint reliability in a combined environment of vibration and thermal cycle testing. Since combined environmental testing is an evolving concept, no default approach or standard test protocol currently exists. The need to develop such a protocol arises from the fact that materials may behave differently under combined stress conditions; exhibit different failure modes and impact the overall reliability. Combined environmental testing would therefore provide the closest approximation to actual field conditions and the best means of evaluating the performance capability of solder joints. In developing this protocol, consideration was given to obtain relevant information from both a reliability perspective (number of cycles to failure) as well as micro-structural stand point (at time of failure). Further, in combining the two conditions, time to failure had to be weighed against the overall expected time of the test; when performed alone, vibration testing is often completed within a single day, while thermal cycle testing can take up to six months to complete. Phase one of this project will include developing and refining the test protocol. Phase two will then use this protocol to evaluate, characterize and compare various low melt, Bi-containing alloys against currently used SAC35 and Sn-Pb solders. Keywords: Accelerated thermal cycling, Reliability testing, Weibull analysis. INTRODUCTION This paper describes a proposed method for investigating solder joint reliability in a combined environment of vibration and thermal cycle testing for Sn-Pb, SAC35, and SAC Bismuth solder alloys. In the literature review, failure criteria, thermal, and vibration levels are examined to define some guideline for the protocol. Combined protocol results will be effected by recrystallization of lead-free solder joints confounding Accelerated Thermal Cycling (ATC) results let alone adding vibration (Mayyas, Yin, Borgesen, 29) 1. It has been reported that for ATC and vibration applied separately, sequencing is of consequence and may affect combined environments (Perkins, Sitaraman, 28) 2. The development of a protocol for combined environment testing requires preliminary investigation over a wide range of temperatures, which will generate a wide range of failure times. It is essential to understand the relative effects of the various design variables as well as the interactions between them before we can move forward with combined environment testing. The authors have established a three phase approach intended to generate relationships between the multiple sources of variation as a roadmap to a combined environment test plan. The sample sizes and alloy / surface finish combinations under study are shown in Table 1. Phase 1a focuses on isothermal Sweep and Overstress at the boundary temperatures and at important intermediate temperatures to understand the range of failure times, the relative energy required to generate failures and to confirm consistent failure modes at all temperatures. Phase 1b will consist of isothermal and constant strain range harmonic testing at each of the Phase 1a temperatures. Phase 2 is currently intended to consist of combined thermal cycling and constant strain range harmonic testing over two separate temperature ranges. Table 1: Test Plan Planned Test Test Temp. SAC35 SnPb Violet ENIG OSP ENIG ENIG -55 C 1 1 1a 25 C 2 1 Sweep & 75 C 1 1 Overstress 125 C 1 1 1b Accelerated Life Test 2 Combined -55 C C C C C to 125 C C to 75 C LITERATURE REVIEW The main objective of this review is to identify a combined thermal and vibration test protocol appropriate for comparing Sn-Pb, Sn-Ag-Cu35, and Bismuth containing tin-silver alloys. (Juarez, Snugovsky, et al, 215) 3 study Sn- Pb, Sn-Ag-Cu35, and Bismuth containing tin-silver alloy performance applying ATC at 55 C to 125 C with 3-min dwells and 1 C/min ramps for 3, cycles using IPC- 971A failure criteria. Vibration testing is performed separately applying 2G and 5G at room temperature. (Shirazi, Yin, et al, 215) 4 in their recent SAC thermal cycling work also use a IPC-971 failure criteria for resistances surpassing 3 ohms for more than 2 nanoseconds for ATC both at -4C to 125C and C to 8C with 15-min dwells and 1 C/min ramps but without vibration. In (IPC-971A, 26) 5 which supersedes IPC- 971 includes an appendix B: Guidelines for Thermal Cycle Requirements for Pb-free Solder Joints recommendations in

2 the indicated sections of IPC-971 for testing Pb-free solder joints. The appendix also contains 14 references to substantiate the thermal cycling recommendations. There is a caution in the article though regarding limited data and insight into determining acceleration factors and acceleration models for Pb-free solder. Over the last 1 years there has been increased research and publications in thermal cycling reliability of SAC solders and the review article (Shnawah, et al, 212) 6 and its references examine SAC solder joint reliability from high to low silver contents and indicate that SAC35 solder alloys lead to better performance for aerospace and military applications compared to SAC15. Combined thermal-vibe for Sn-Pb has been studied by (Liguore and Followell, 1995) 7 using 5 isothermal temperatures between -29C and 93C at.1,.15, and.3 g 2 /Hz with a 5 Hz bandwidth around the first resonant frequency. (Qi, Osterman, and Pecht, 28) 8 apply thermal cycling -5C/+15C at a power spectral density (PSD) level of.1 g 2 /Hz over 1-1 Hz use a failure criteria based on (IPC-SM-785, 1992) 9. Qi, et al, go on to say that while significant study has been conducted on temperature cycling reliability, vibration and vibration combined with temperature cycling has received much less attention, in addition their literature search shows only four papers on combined thermal-vibe using Sn-Pb had been found. Next we examine SAC35 and Sn-Pb solder alloys in vibration only and combined thermal and vibration. (Zhou, Al-Bassyiouni, Dasgupta, 21) 1 examine harmonic vibration and random vibration at room temperature; for the harmonic testing an appropriate vibration level was chosen about the first resonance frequency after performing an Over Stress test; and for random vibration the excitation level was increased from.1 g 2 /Hz to.4 g 2 /Hz in 4 equal increments for 13 hours each over a frequency range of 1Hz to 5Hz. Also, (Woodrow, 27) 11 conducted random vibration step stress testing and modeling of Sn-Pb, SAC, SAC Bismuth, and Sn-Cu. Seven levels of random vibration (.67 g 2 /Hz to.536 g 2 /Hz in increments of 2 Grms but jumps to 28 Grms at the 7 th step) were applied between 5 Hz and 1 Hz. An Analysis Tech 256STD Event Detector set to a 3 ohm threshold. (Eckert, Muller, et al, 29) 12 combine thermal and vibration using IPC971 failure criteria; the test is done using 6 min long cycles between -4C and +125C combined with 15 minutes of vibration at the temperature dwells. The maximum random vibration was.1 g 2 /Hz over a frequency range between 1 Hz and 1 khz. Whether the researchers explicitly defined their failure criteria or not the main resultant is S-N curves or strain estimates and cycles to failure. The most commonly used failure criteria is IPC-971A. The application of vibration is at the temperature dwells and for 15 minutes at the extreme temperatures. (Eckert, Muller, et al, 29) 12 suggest 2 minute dwells and applying vibration after 5 minutes of temperature settling. (Zhou, Al- Bassyiouni, Dasgupta, 21) 1 share that there is less dispersion in the harmonic durability results, therefore; since no combined test data exists for Bismuth containing lower melt SAC alloys, harmonic testing is the starting point. EXPERIMENTAL In this paper we will cover the isothermal Sweep and Step stress testing of the ENIG leg of Phase 1A. PHASE 1A TESTING Phase 1A, has three primary objectives. First, it is intended to develop predictive relationships between the test temperature, the resonance frequency (RF) of the Unit Under Test (UUT), the driving G level of the table, the response G level of the UUT and the micro-strain registered at the midpoint of the span. Second, it is intended to develop a relationship between test temperature and cycles to failure in the primary technologies on the test vehicle or a similar relationship based on the work / energy absorbed by the solder joints. Third, it is intended to compare the relative effects of ENIG and OSP surface finishes on the various parameters and isothermal step stress performance. Vibration testing is inherently more complex than accelerated thermal cycling (ATC) because the material properties of the UUT will degrade over the course of the test altering its response to the mechanical driving force. As damage accumulates in the unit softens causing drift in both RF and the limits for the half power band. This damage accumulation requires that the experimenters monitor the response and adjust the input energy to maintain constant conditions over the course of the test. This requirement for adjustment is further complicated because all of the relevant materials used in the manufacture of electronic assemblies have fundamental mechanical properties that vary with temperature. Another complexity is that failing devices cannot be removed at the time of failure. as removal will so radically change the mechanical system further testing is impossible. Therefore, investigators must choose between physical failure analyses of the structure at time of failure or continued testing to provide more failure data. To properly define a combined environment test plan we must first understand the isothermal performance of a material set over the temperature range of interest. The first challenge was to produce mechanically uniform material for testing. The test vehicle design provided by Honeywell and has been used extensively in mechanical testing. The units for all of Phase 1 were built together in one group using the three alloys shown in Table 1. at a Curtiss Wright facility.

3 PLCC PLCC BGA_2 BGA_1 BGA_1 BGA_2 Figure 1: Test vehicle & tech types Since repeatability and accuracy are critical all units were stored in a dry room and steps were taken to insure that the thermal history of all of the units varied only by the thermal requirements of the assembly alloy. Note that all of the results for Phase 1A testing are for SAC-35 alloy solder. Strain gauges were mounted at locations defined by the solder mask or by the vias in the footprint of the component of interest. The location of the thermocouple and the response accelerometer were also defined in the test specification. The resistance monitoring cables are hand soldered to the PTH barrels located along the free edge of the unit and all cables: resistance, strain, Thermocouples (TC) and accelerometers are strain relieved with Capton tape or flexible RTV. Table 2: Test Equipment Equipment Information Chamber Thermotron, F-42-CHV chamber, Vibration Ling Dynamic Systems 8 poundforce vertical shaker, Table Jaguar Jaguar software to operate table and Software record the accelerometer data Strain System Vishay System 6 Strain system. Record strain values during first minute, 13 th minute and 26 th minute. Scan rate of 5Hz STD-256 system. Cycle time 2 seconds, scan rate 2 seconds. Fail point 3 ohms. Maximum Event occurrence limit disabled. Software Detector records the cycle count when a component resistance exceeds 3 ohms. Temperature Monitoring Fluke 73 Agilent 3852A system. Monitor the ambient temperature and the board temperature every minute. Hand held multimeter to verify component fails Figure 2: Thermal test chamber & vibration table The Jaguar software system provides control for the electrodynamic shaker table using feedback from the control accelerometer on the table and collects data from both the table and the (UUT). At 2 second intervals the system records, Time (sec), Frequency (Hz.), Control (g), Response (g), and phase angle. All of the comparative and accumulated measurements are calculated from these channels in post processing. The two rosettes and 6 linear strain gauges attached to the UUT generate 12 micro-strain channels of data which are collected by a separate, Vishay 6 system. Strain channels must be collected at a minimum of 5 Hz requiring that stain data is sampled at intervals to reduce the size of the data files. For the Phase 1A testing we collected strain data for the 1 st, 13 th and 26 th minute of each step. The average positive and negative peak strain values were calculated over these one minute intervals and the range between average peak values was assigned to the test interval. The ambient chamber temperature and the surface temperature of the UUT were monitored by an Agilant 3852A system which recorded data every 1 minute. The component chains were fully in-situ monitored using an STD-256 event detector. The equipment scans all channels at two second intervals and saves data every 2 seconds. Maximum occurrence limits were disabled for this testing and the software records each cycle when the chain resistance exceeds 3 Ohms. Resistance chains that recorded 3 Ohm events during the course of a step were verified at the end of the step with a Fluke 73 multi-meter.

4 Figure 3: Fully instrumented UUT. TEST METHOD The step stress procedure utilized in Phase 1A incorporates multiple dwells of 1 cycles at 1G increments until at least the four devices exposed to the highest strain levels have failed. The test is terminated at the end of the step that includes the 4 th failure. The four devices are the two PLCC 84 devices and the two BGA 1156 devices closest to the centerline of bending. These devices are coded as tech types PLCC and BGA1 respectively and are labeled in Figure 1. The detailed procedure is as follows: The assembled board with sensors attached is mounted on the vibration table in a custom built fixture (components down, to allow easy electrical confirmation of failed components). The cables are led outside the chamber and all connections to monitor and control systems are made and confirmed. The chamber is closed, the temperature monitor equipment is engaged and the chamber is brought to test temperature and allowed to soak until the unit has stabilized. A sine sweep is performed at 1G and 4 octaves per minute between 1 Hz and 2 Hz to identify the resonant frequency and the half power band limits. These limits are then recorded by the software as control limits for the 1 cycle dwell at 1G. This sine sweep and limit definition procedure is repeated at each subsequent step dwell. The micro-strain collection system is started at the initiation of each dwell and records strain values at 5 Hz for 6 second periods at the defined intervals. At the termination of the dwell the vibration log file, strain log file and event detector log file are saved to record the parametric and failure data collected before initiating the next dwell. The process was repeated until the primary tech type failures were recorded. Sine sweep plots highlighting input and response G levels over the range are displayed in Figures 4, 5 & 6. These three plots display the typical differences that can be encountered between boards and temperatures. Compare Figure 4 SN T3-5 at 1G and 125 to Figure 5: SN T3-51 at 1G and - 55 to Figure 6 which is SN T3-51 at -55 at 5G. The respective values of RF and response Gpk are & 18.72, & , & for Figure 4, Figure 5 and Figure 6 respectively. The differences in shape and the intensity of a second resonance frequency are also obvious upon examination of the plots. Figure 4: T3-5 Sine 1 Gpk 4 Oct/min at 125 Figure 5: T3-51 Sine 1 Gpk 4 Oct/min at -55 Figure 6: Sine 5 Gpk 4 Oct/min at -55 Strain levels recorded from sine sweeps provide a view that are more readily understood by those used to manufacturing strain audits. Figure 7 displays the results from a sine sweep at.5gpk input and 4 Oct/min. The pattern is typical for all of the sweeps recorded in this test phase.

5 Equation 1 Micro-strain = RF(Hz) Glevel Figure 7: Micro-strain (ue) vs. Time (s) TEST RESULTS It should be noted that even after our considerable efforts to insure that all assemblies had been exposed to very similar thermal histories and processing one of the boards had a significantly different RF than the other three. Certainly test temperature and frequency are related, the colder temperatures increase Young s modulus (E) in both the board resin and the solder which in turn increase the RF. However, SN T3-43 exhibited an RF value just over 8% of the average of the three other units in this test. Inspection of the support and constraint system after test leads us to the conclusion that manufacturing variation must be the cause. One likely cause is orientation on the master panel at the board fabrication shop. A typical E value for an FR4 Epoxy PWB in the fill direction would be 32 ksi which is approximately 85% of the E value (375 ksi) in grain direction. Board manufacturers regularly rotate some images on the master panel to better utilize the material. Table 3: RF and Micro-strain Test Temp. 1G ue 2G ue SN RF(Hz) T T T T The lower RF value results in higher displacement and micro-strain values from the same driving G level. The highlighted row in Table 3 shows the effect on micro-strain. This difference in micro-strain in turn produces a reduced life time in cycling. Analysis of test records indicates that the only direct predictors of micro-strain are RF and driving G level. Test temperature has an influence because it influences the RF value but RF is the predictor of the strain range (distance from peak to peak at the maximum displacement point at the center of the span. The defining relationship calculated from average recorded values over the first two steps of each trial is displayed in Equation 1 and accounts for 67.75% of the predicted variation and will be used as a first estimate for calculating the required input G level to produce consistent strain levels over the subsequent 1B test phase. Preliminary analysis indicates that failure for both of the primary technology types follow the same pattern over the temperature range. Cycles to failure for the BGA_1 (Figure 8) and the PLCC (Figure 9) tech. types are similar. The PLCC type exhibits smaller differences between locations that are symmetric to the centerline of displacement. However, the dominant trend is clear, survival time increases as temperature decreases suggesting that the improved mechanical properties of the solder more than compensate for the increased stress imposed by the harder and stiffer laminate properties. Cycles to Failure Figure 8: BGA1 cycles to failure by T ( ) Cycles to Failure Figure 9: PLCC cycles to failure By T( ) Tech = BGA_1 25 However, cycles to failure does not account for the differences in cycle energy imposed by step stress testing. A single cycle of 1G at 25 is not equivalent to a cycle of 3G at 25 or 5G at 25. The amount of stress imposed on the solder is related to the number of cycles and also to the magnitude of each cycle. In this testing displacement is not measured but strain at the maximum displacement position is measured. As a first estimate of the energy absorbed by 5 Test_Temp Tech = PLCC Suspended 25 5 Test_Temp

6 the solder we have calculated the number of cycles multiplied by the strain range of each cycle. This accumulated value is displayed in Figures 1 and 11 as Micro-strain*cycles. While this cannot be considered a direct engineering unit, for planning purposes it may represent a better first approximation of the relative work to failure. Micro-strain * Cycles to Failure Tech = BGA_1 Figure 1: BGA_1 microstrain*cycles to failure by T( ) The conversion to this unit does have a smoothing effect on the data. On this scale there is a rank order change for BGA_1 devices that correlates better with test temperature. For PLCC devices the curve is smoother but there is no change in position. It should also be noted that since frequency is essentially constant during the test, strain rate increases with strain range. At 5 Hz a cycle range of 1 ue results in a strain rate of 5, ue/sec, while a cycle range of 4 ue would be 2, ue/sec Test_Temp Table 4 is an attempt to illustrate the amount of the actual accumulated damage that resulted in electrical failure relative to the amount of damage evident in the micrographs. Note that this table does not reflect the magnitude of the strain associated with those cycles and since the amplitude of the cycle s increases with each step, even these percentages are probably a low estimate of the proportion of damage. Table 4: Cycles to Fail & Cycles to Failure Analysis SN T3-51 T3-41 T3-43 T3-5 Device Test T ( ) Cycles Fail Cycles X-sect. Fail /X-sect U9 PLCC % U1 BGA_ % U1 BGA_ % U11 BGA_ % U19 PLCC % U1 BGA_ % U9 PLCC % U11 BGA_ % There were electrical failures on tech types other than PLCC and BGA_1 but those events are not documented in this work. The BGA_1 devices on unit T3-41 tested at 25 failed at distinctly different intervals. U1 (Figure 12) recorded a failure at 229 cycles while U11 (Figure 13) did not fail until 438 cycles, almost 2X the nominal cycles. The fracture surfaces are not noticeably different despite that fact that strain magnitude, which increases with time, is not taken into account. There are spheres in both devices with very straight crack paths and those which meander through recrystallized grain boundary networks. Tech = PLCC 7 Micro-strain * Cycles to Failure Suspended Ball 6 Ball 18 Figure 12: T BGA_1 (U1) N f = 229K Test_Temp Ball 6 Ball 8 Figure 11: PLCC microstrain*cycles to failure by T( ) Each failure was electrically confirmed to the component level at the end of the step where failure was recorded in the data. Unfortunately components cannot be removed prior to the termination of mechanical test. Representative components from the BGA_1and PLCC tech types were sectioned at the end of test. Some of these samples have accumulated significant additional damage after electrical failure. Figure 13: T BGA_1 (U11) N f = 438 The PLCC devices on T3-41 and T3-46 both tested at 25 survived to 271K, 347K, 382K & 45K. All of these devices have similar looking crack paths that initiate in the solder fillet travel very close to the lead interface in the bulk solder. A typical image of the solder condition at test termination is shown in Figure 14.

7 Figure 17: T C BGA_1 (U1) N f = 18K Figure 14: T C PLCC Nf = 45K Unit T3-51 tested at -55 had the longest times to failure. The BGA_1 device at U1 was the longest survivor of the test phase for this tech type. The solder spheres shown in Figure 15 are typical of the first row of the device closest to the centerline of bending. There are a mix of failure surfaces all close to the BGA interface which had a smaller area than the board side interface. There is evidence that on some of the solder joint cracks grew from both the inside and outside of solder and were joined by a more significant event once they had significantly weakened the joint. (Figure 15) The PLCC device at U9 displayed in Figure 16 shows a crack path in the bulk solder very close to the lead interface. The percentage and dimension of unmated surfaces is lower here than in the other samples. This was expected for harder solder that lasted relatively longer into the test. (94%) However, there is no way for us to isolate the point of first failure in these tests. This surface could be associated with a pin that went even further into the cycle count before failing. Figure 18: T C PLCC (U19) N f = 173K The devices on the T3-5 unit all show wide crack paths with significant wide spaces and or open surfaces. This is indicative of significant damage after failure and may include loose grains which have lodged between the surfaces to hold them open. (Figure 19) Alternatively the residual stress in the part may open the cracks when a significant number of joints have been separated. The PLCC crack path in Figure 2 displays more tearing and open space than those tested at cooler temperatures suggesting that this characteristic is dependent on the relative strength of the solder. Figure 19: T C BGA_1 (U11) N f = 111K Figure 15: T C BGA_1 (U1) N f = 458K Figure 2: T C PLCC (U9) N f = 147K Figure 16: T C PLCC (U9) N f = 656K The U1 BGA_1 device on Unit T3-43 exhibits wandering crack paths and multiple side branches indicating recrystallization in the area around the crack path. (Figure 17) The PLCC device shows the crack path evident in all of the tests but relatively more large spaces than tests at colder temperatures. (Figure 18) CONCLUSIONS Test procedures and data collection systems for isothermal step stress testing have been validated and refined for longer term testing. Step stress testing of units with resonance frequencies near 5 Hz can generate solder fatigue failure modes at a step length of 1K cycles and step increments of 1G. A First estimate of the relationship between micro-strain, resonance frequency and driving G level has been established.

8 Units from the process lot tested at -55 are expected to absorb 2.25 times the energy to failure as units tested at 25 and 6 times as much energy as units tested at 125. FUTURE WORK The project team intends to complete the OSP leg of the Phase 1A testing early in Q2 of 216 and move into Phase 1B, which is isothermal low cycle fatigue testing at controlled strain ranges. ACKNOWLEDGEMENTS This work is funded by the Refined Manufacturing Acceleration Process (ReMAP) and member companies. The authors would like to acknowledge the contribution of several Celestica employees. Eva Kosiba was key to much of the assembly and early planning for this project. We would also like to acknowledge Kamran Sodaei, Parisa Najafi and Amit Prajapati for their contributions to the testing and failure analysis of these samples. Solder Joints Using an Incremental Damage Superposition Approach, IEEE Transactions on Advanced Packaging, Volume 31, No. 3, August IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments, November Y. Zhou, M. Al-Bassyiouni, A. Dasgupta, Harmonic and Random Vibration Durability of SAC35 and Sn37Pb Solder Alloys, IEEE Transactions on Components and Packaging Technologies, Volume 33, Number 2, June 21, pp T. Woodrow, Modeling of the JCAA/JG-PP Lead-Free Solder Project Vibration Test Data, IPC/JEDEC Global Conference on Lead Free Reliability Testing, Boston, MA, April 1-11, T. Eckert, W. H. Muller, N. F. Nissen, H. Reichl, Modeling Solder Joint Fatigue in Combined Environmental Reliability Tests with Concurrent Vibration and Thermal Cycling, IEEE th Electronic Packaging Technology Conference, pp REFERENCES 1. A. Mayyas, L. Yin, P. Borgesen, Recrystallization of Lead-free Solder Joints-Confounding the Interpretation of Accelerated Thermal Cycling Results, Proceedings of the ASME 29 International Mechanical Engineering Congress & Exposition, November 13-19, Lake Buena Vista, Florida, USA. 2. A. Perkins, S.K. Sitaraman, A Study into the Sequencing of Thermal Cycling and Vibration Tests, IEEE 28 Electronics Components & Technology Conference. 3. J. M. Juarez, P. Snugovsky, E. Kosiba, Z. Bagheri, S. Suthakaran, M. Robinson, J. Heebink, J. Kennedy, M. Romansky, Manufacturing and Reliability Screening of Lower Melting Point, Pb-Free Alloys Containing Bismuth, Journal of Microelectronics and Electronic Packaging, Volume 12, Number 1, pp. 1-28, First Quarter S. Shirazi, L. Yin, S. Khasawnch, L. Wentlent, P. Borgesen, Effects of Solder Joint Dimensions and Assembly Process on Acceleration Factors and Life in Thermal Cycling of SnAgCu Solder Joints, IEEE 215 Electronics Components & Technology Conference. 5. IPC-971A, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments, February D. S. Shnawah, M. F. M. Sabri, I. A. Badruddin, A review of thermal cycling and drop impact reliability of SAC solder joint in portable electronic products, Microelectronics Reliability Volume 52, pp. 9-99, S. Liguore, D. Followell, Vibration fatigue of Surface Mount Technology (SMT) Solder Joints, IEEE 1995 Proceedings Annual Reliability and Maintainability Symposium. 8. H. Qi, M. Osterman, M. Pecht, Modeling of Combined Temperature Cycling and Vibration Loading on PBGA