SEER for Hardware Electronics and Systems Extended Capabilities

Transcription

1 SEER for Hardware Electronics and Systems Extended Capabilities Keith Garland Andrew Langridge Bletchley Conference

2 SEER for Hardware Client for Microsoft Project Keith Garland Galorath International 2

3 Introduction Looking at origin of plug-in SEER for Hardware Estimate Plug-in Process Steps Demonstration Summary 3

4 Pedigree - SEER for Software SEER for Software Client for Microsoft Project Released now for 5 years 20-30% of SEM Users also use the client plug-in for MS Project. Used worldwide by Cost Analyst and Programme Managers 4

5 Originating Tool: SEER for Hardware Galorath s hardware lifecycle cost estimation tool 5

6 The SEER-H Client Process 1st, 1st, Create Create a SEER-H project 3rd, 3rd, Within Within Project, invoke invoke the the SEER-H Client Client 2 nd nd Plan Plan Button Within Within Project Finally, A plan plan is is laid laid out out in in Project 6

7 SEER-H Client Step-by-Step Within the SEER-H Client Step 1: Select a SEER for Hardware Project SEER-H project files may be directly imported with no additional steps required. Step 2: Select a planning scheme A scheme represents a collection of processes, each specific to the type of SEER- H element being exported. 7

8 SEER-H Client Step-by-Step Step 3: Choose a resource assignment This determines the labor categories into which SEER-H effort estimates will be placed. Or create a custom resource assignment Finely detailed custom labor assignments may be created within the H Client and saved for future use. 8

9 SEER-H Client Step-by-Step Step 4: Select SEER-H element types You may specify precisely which SEER-H elements are laid out. Example: You may not need to include site elements if you are just laying out a development plan Hit PLAN The H Client invokes SEER-H to obtain estimates and then begins laying out the plan in Project. 9

10 The Resultant Plan 10

11 Plans Are Laid Out Using Custom or Standard Templates Custom templates can be defined to capture A very wide variety of processes Specific phases and activities of interest Dependencies among tasks 11

12 Templates allow you to control What is included in your plan Development only Acquisition (development & production) Life cycle cost System level costs The level of detail High level phases Detailed tasks Milestones You may include additional items, not estimated by SEER-H Travel expense Special training 12

13 Demo Time! 13

14 Summary SEER-H client harnesses the powerful estimating engine of Galorath Incorporated's SEER-H, with its sensitivity to the wide variety of factors which influence hardware development projects. Easily produce detailed plans from existing SEER-H projects Allows users to select the planning template and resource assignment Or create a custom resource assignment using the SEER-H Client's built-in resource scheme editor 14

15 Integrated Circuits Pro A plug in for SEER for HARDWARE, ELECTRONICS & SYSTEMS (SEER-H) Andrew Langridge Galorath International 15

16 Introduction to Integrated Circuits Pro Overview What Integrated Circuits Pro Estimates Inputs Reports Key Features 16

17 Overview SEER for Hardware, Electronics & Systems estimates the cost of printed circuit board development and production Memory, off the shelf chips, resistors, capacitors, and other components are included in the SEER-H estimate SEER-H always had a way of calculating design and recurring cost of custom ICs through custom Chip Usage parameter The Integrated Circuits Pro add-on estimates the specific costs of development and production of custom ASICs and FPGA development costs. The ASIC and FPGA costs are fully integrated into the SEER-H cost reports Only estimates the Firmware cost; any embedded software needs to be estimated in another package such as SEER for Software (SEER-SEM) 17

18 Development Three years of extensive research into current industry practices in Space, Ground and Air (Military and Commercial applications) Engaged leading experts in integrated circuit technology and commercial practices to shape model architecture and ensure reasonable approach Interviews of current customer base to determine industry need. 18

19 Technologies included SEER-Integrated Circuit Pro will estimate development and production costs for: Standard Cell ASIC s (most prevalent type) FPGA s ( to 65nm technology) (development cost only) Will add structured cell, MCM and others in following revisions. ASIC processes estimated CMOS BiCMOS SOI GaAs SiGe 19

20 Setting Up a Work Element 20

21 FPGA inputs 21

22 ASIC Inputs (1) 22

23 ASIC inputs (2) 23

24 Input Philosophy As is traditional in SEER models, the majority of initial inputs are made based on knowledgebase settings Others, such as Design Team Size, Defect Density, Mask Steps, etc., are made for you as defaults but with your option to override Still others accept partial information from suppliers if it is available and use it to override internal calculations. Examples: Front End Design NRE Price Back End Design NRE Price Mask Set Unit Price Wafer Yield % Unit Packaged Die Price Unit Package Price, etc. 24

25 FPGA Reports 25

26 ASIC Reports 26

27 Benefits Seamless operation within SEER for HARDWARE, ELECTRONICS & SYSTEMS (SEER-H) Results integrated into standard SEER-H charts and reports Separate parameter input screens for ASICs and FPGAs Two dedicated detail reports ASICs FPGAs Estimates ASIC production as prices from external foundry suppliers, not internal production costs All CER coefficients and other key data stored in a database to facilitate model updates Accounts for effects of various mixes of logic gate types on the die 27

28 Demo Time 28

29 Summary New IC is an optional add-on the new SEER-H v7 Replaces old standalone SEER-IC Supplements SEER-H PCB estimates for development and production Custom ASICs FPGAs Thoroughly researched for three years and (still) on going 29

30 For More Information Please contact Galorath International Ltd. Tel:+44 (0)