Dallas Semicoductor DS80C320 Microcontroller
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1 Construction Analysis Dallas Semicoductor DS80C320 Microcontroller Report Number: SCA Global Semiconductor Industry the Serving Since N. 75th Street Scottsdale, AZ Phone: Fax: Internet:
2 INDEX TO TEXT TITLE PAGE INTRODUCTION 1 MAJOR FINDINGS 1 TECHNOLOGY DESCRIPTION Assembly 2 Die Process 2-3 ANALYSIS RESULTS I Package and Assembly 4 ANALYSIS RESULTS II Die Process 5-7 ANALYSIS PROCEDURE 8 TABLES Overall Quality Evaluation 9 Package Markings 10 Wirebond Strength 10 Die Material Analysis (EDX and WDX) 10 Horizontal Dimensions 11 Vertical Dimensions 11 - i -
3 INTRODUCTION This report describes a construction analysis of the Dallas Semiconductor DS80C320 Microcontroller. Five devices packaged in 44-pin Plastic Leaded Chip Carriers (PLCCs) were received for the analysis. Devices were date coded MAJOR FINDINGS Questionable Items: 1 Metal thinned up to 85 percent 2 at some contact edges (Figure 17). No cap or barrier metals were used and this amount of thinning of metal that is only of 0.45 microns nominal thickness should be discussed with the manufacturer. Special Features: An SRAM array and a MROM array were employed on the device. Somewhat unusual CMOS process having no reflow glass (uses SOG), and relatively deep S/D diffusions and active loads. Large polycide interconnect areas. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application. 2 Seriousness depends on design margins
4 TECHNOLOGY DESCRIPTION Assembly: Devices were packaged in 44-pin plastic leaded (PLCC) chip carriers. The die was mounted to the paddle using a silver epoxy die attach. Die separation was by sawing. Wirebonding was by the thermosonic ball bond method using 1.1 mil O.D. gold wire. Lead-locking provisions (anchors and holes) at all pins. Die Process : Devices were fabricated using a selective oxidation, twin-well CMOS process in a P substrate. No epi was used. No die coat was present. Passivation consisted of a layer of nitride over a thick layer of silicon-dioxide. Metallization consisted of a single layer of dry-etched metal. The metal layer consisted of aluminum and did not use a cap or barrier. Standard contacts were used (no plugs). Pre-metal dielectric consisted of a layer of phosphosilicate glass (PSG) over densified oxides and covered with a layer of SOG. The glass was not reflowed
5 TECHNOLOGY DESCRIPTION (continued) A single layer of polycide was used (tungsten-silicide). It was used to form all gates on the die and the word lines in both memory arrays. It was also used as a layer of interconnect. Direct poly-to-diffusion (buried) contacts were not used. Definition of the poly was by a normal dry etch. Fairly deep implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. Oxide sidewall spacers on the gates were left in place. Local oxide (LOCOS) isolation. A slight step was present in the oxide at the edge of the well boundaries indicating a twin-well process was used. SRAM array: A 6T SRAM cell design. Metal was used to form the bit lines. Poly was used to form the word/select lines, storage gates and pull-up devices. Long active P-channel loads were employed. MROM arrays: Metal formed the bit lines and poly formed the word lines. The array was programmed at the field oxide (diffusion) level (see Figures 29 and 30). Redundancy fuses were not present
6 ANALYSIS RESULTS I Package and Assembly: Figures 1-9 Questionable Items: 1 None. Special Features: None. General Items: Devices were packaged in 44-pin plastic leaded (PLCC) chip carriers. Overall package quality: Good. No significant defects were noted on the external or internal portions of the package. No cracks or voids were noted in the plastic. Leadframe: The leadframe was constructed of copper. External tinning consisted of tin-lead (SnPb) while internal plating consisted of silver (Ag). No gaps were noted at lead exits. Die dicing: Die separation was by sawing of normal quality. No large cracks or chips were present. Die attach: A silver epoxy of normal quality was used to attach the die to the header. No significant voids were noted in the die attach. Wirebonding was by the thermosonic ball bond method using 1.1 mil O.D. gold wire. Bonds were well formed and placement was good. Wirepull strengths were normal with no bond lifts (see page 10). 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application
7 ANALYSIS RESULTS II Die Process: Figures 10-32b Questionable Items: 1 None. Special Features: An SRAM array and a MROM array were employed on the device. Somewhat unusual CMOS process having no reflow glass (uses SOG), and relatively deep S/D diffusions and active loads. Large polycide interconnect areas. General Items: Fabrication process: Devices were fabricated using a selective oxidation, twin-well CMOS process in a P substrate. No epi was used. Design implementation: Die layout was clean and efficient. Alignment was good at all levels. No damage or contamination was found. Die coat: No die coat was present. Overlay passivation: A layer of nitride over a layer of silicon-dioxide. Overlay integrity test indicated defect-free passivation. Edge seal was good as it extended into the scribe lane to seal the metallization. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application. 2 Seriousness depends on design margins
8 ANALYSIS RESULTS II (continued) Metallization: A single layer of metal consisting of aluminum. No cap or barrier metals was used. Metal patterning: The metal layer was patterned by a dry etch of normal quality. All contacts were completely surrounded by aluminum. Metal defects: No voiding, notching, or neckdown was noted in the metal layer. No silicon nodules were noted following the removal of the aluminum layer. Metal step coverage: Worst case aluminum thinning was 85 percent at contact edges. MIL-STD allows up to 70 percent metal thinning for contacts of this size, but in this case the metal already seems to be unusually thin normally, and no cap or barriers are present. Typical aluminum thinning was 60 percent. Pre-metal dielectric: A layer of SOG over a layer of phosphosilicate glass over densified oxides was used under the metal. No reflow was performed. This is a somewhat unusual structure but no problems were found. Contact defects: None. No significant over-etching of the contacts was noted and no pitting or silicon mound growth was present. Polysilicon: A single layer of polycide (tungsten- silicide) was used to form all gates on the die and for interconnect (crossunders). Slots were noted within some of the large poly crossunders (Figures 32a and 32b). Direct poly-to-diffusion (buried) contacts were not used. Poly links are inactive and appear to have been a mask modification (Figure 21). Definition was by a dry etch of normal quality. Diffusions: Fairly deep implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. Oxide sidewall spacers were used at all gates and left in place. No silicide was present on the diffusions
9 ANALYSIS RESULTS II (continued) Local oxide (LOCOS) isolation was used. No problems were noted. The slight step present in the oxide at the well boundary indicates a twin-well process was employed. SRAM array: Two blocks of SRAM memory were present. A 6T SRAM cell design was employed. Metal was used to form the bit lines. Poly was used to form the word/select lines, storage gate and pull-up devices. Cell pitch was relatively large 12.2 x 22.8 microns. MROM array: Two separated blocks of MROM arrays were present on the device. Metal formed the bit lines and poly formed the word lines. No problems of any sort were noted in the SRAM nor MROM arrays. Both arrays were programmed at the field oxide (diffusion) level (see Figures 29 and 30). Special items: ESD tests were performed on Sample 4 and revealed that all pins passed pulses of +4000V. - Latch-up tests were performed on Sample 5 and revealed that no pin latched-up
10 PROCEDURE The devices were subjected to the following analysis procedures: External inspection ESD and Latch-up tests X-ray Package section Decapsulate Internal optical inspection SEM of passivation and assembly features Passivation integrity test Wirepull test Passivation removal SEM inspection of metal Metal removal Delayer to silicon and inspect poly/die surface Die sectioning (90 for SEM) * Die material analysis Measure horizontal dimensions Measure vertical dimensions * Delineation of cross-sections is by silicon etch unless otherwise indicated
11 OVERALL QUALITY EVALUATION: Overall Rating: Normal to Poor * DETAIL OF EVALUATION Package integrity Package markings Die placement Wirebond placement Wire spacing Wirebond quality Die attach quality Dicing quality Die attach method Dicing method Wirebond method N N N N N N N N Silver epoxy Sawn Thermosonic ball bonds using 1.1 mil gold wire. Die surface integrity: Toolmarks (absence) G Particles (absence) G Contamination (absence) G Process defects (absence) G General workmanship N Passivation integrity G Metal definition N Metal integrity NP * Contact coverage G Contact registration G * Metal thinning up to 85 percent on metal that is only 0.45 micron thick. G = Good, P = Poor, N = Normal, NP = Normal/Poor - 9 -
12 PACKAGE MARKINGS (TOP) DALLAS DS80C B3-QCG (BOTTOM) KOREA 478AA WIREBOND STRENGTH Wire material: Die pad material: 1.1 mil O.D. gold aluminum Sample # 1 # of wires pulled: 15 Bond lifts: 0 Force to break - high: 17g - low: 15g - avg.: 15.8g - std. dev.: 0.9 DIE MATERIAL ANALYSIS (EDX and WDX) Overlay passivation: Metallization: Pre-metal dielectric: Polycide: A layer of nitride over a layer of silicon- dioxide. Aluminum (Al). A phosphosilicate glass (PSG) containing 3.6 wt. % phosphorus. No boron was detected. Topped with a layer of SOG. Tungsten (W) silicide. WDX analysis
13 HORIZONTAL DIMENSIONS Die size: 4.8 x 4.8 mm (191 x 191 mils) Die area: 23 mm 2 (36,481 mils 2 ) Min pad size: 0.08 x 0.08 mm (3.3 x 3.3 mils) Min pad window: 0.07 x 0.07 mm (2.7 x 2.7 mils) Min pad space: 0.15 mm (5.8 mils) Min metal width: 0.85 micron Min metal space: 1.3 micron Min metal pitch: 2.15 microns Min contact: 1.0 micron Min poly width: 0.85 micron Min poly space: 1.0 micron Min gate length - (N-channel): * 0.85 micron - (P-channel): 0.85 micron SRAM cell size: 278 microns 2 SRAM cell pitch: 12.2 x 22.8 microns MROM cell size: 14 microns MROM cell pitch: 3.5 x 4 microns VERTICAL DIMENSIONS Die thickness: 0.45 mm (17.8 mils) Layers: Passivation 2: 0.5 micron Passivation 1: 1 micron Metal: 0.45 micron Pre-metal dielectric: 0.5 micron (avg.) Oxide on poly: 0.15 micron Poly: 0.4 micron Local oxide: 0.5 micron N+ S/D: 0.35 micron P + S/D: 0.3 micron N-well: 5 microns P-well: 5 microns * Physical gate length
14 INDEX TO FIGURES PACKAGING AND ASSEMBLY Figures 1-9 DIE LAYOUT AND IDENTIFICATION Figures 10-11a PHYSICAL DIE STRUCTURES Figures 12-32b COLOR DRAWING OF DIE STRUCTURE Figure 24 SRAM MEMORY CELLS Figures MROM MEMORY CELLS Figures INPUT PROTECTION CIRCUIT Figure 31 GENERAL CIRCUIT LAYOUT Figure 32 POLY DESIGN FEATURES Figures 32a and 32b - ii -
15 PIN 44 = VCC PIN 22 AND 23 = GND Figure 1. Package photographs and pinout of the Dallas Semiconductor DS80C320. Mag. 3x.
16 PIN 1 top view side view Figure 2. X-ray views of the package. Mag. 3x.
17 LEADFRAME PLASTIC PACKAGE DIE HEADER Figure 3. Package section views illustrating general package construction. Mag. 13x.
18 LEADFRAME PLASTIC PACKAGE Mag. 20x Cu LEADFRAME Mag. 100x PLASTIC PACKAGE PLASTIC PACKAGE SnPb TINNING Mag. 300x Cu LEADFRAME Figure 4. Optical and SEM views of lead forming and lead plating.
19 DIE SECTIONING ARTIFACT Cu PADDLE Mag. 65x DIE Ag -EPOXY DIE ATTACH Cu PADDLE Ag PLATING Mag. 500x Figure 5. Optical package section views of die dicing and die attach.
20 DIE DIE ATTACH ETCHED DURING DECAPSULATION Mag. 120x EDGE OF PASSIVATION Mag. 1000x Figure 6. SEM views of dicing and die edge seal. 60.
21 123 DIE EDGE METAL SCRIBE LANE Mag. 1400x PASSIVATION 2 PASSIVATION 1 Mag. 6500x Figure 7. SEM views of the edge seal. LOCAL OXIDE
22 Au BOND DIE Figure 8. Optical section view of a typical ball bond. Mag. 800x. Au Mag. 600x PAD Au Mag. 500x LEADFRAME Figure 9. SEM views of typical wirebonds. 60.
23 PIN 2 Figure 10. Whole die photograph of the Dallas Semiconductor DS80C320. Mag. 32x.
24 Mag. 200x Mag. 320x Figure 11. Identification markings from the die surface.
25 Mag. 320x Mag. 320x Mag. 500x Figure 11a. Additional die markings from the surface.
26 PASSIVATION 2 PASSIVATION 1 Mag. 6500x STEP METAL N-WELLS METAL PASSIVATION 2 PASSIVATION 1 POLY GATE Mag. 6500x STEP P+ N-WELL PASSIVATION 2 PASSIVATION 1 METAL SOG Mag. 13,000x P+ POLY GATE Figure 12. SEM section views illustrating general device structure.
27 Mag. 2500x Mag. 12,000x Figure 13. SEM views of overlay passivation coverage. 60.
28 PASSIVATION 2 PASSIVATION 1 METAL Mag. 26,000x PASSIVATION 1 METAL PRE-METAL GLASS Mag. 40,000x Figure 14. SEM section views of metal line profiles.
29 METAL Mag. 1600x METAL Mag. 3200x METAL Mag. 6500x Figure 15. Topological SEM views illustrating metal patterning. 0.
30 METAL Mag. 3200x METAL Mag. 5200x METAL Mag. 26,000x Figure 16. Perspective SEM views illustrating metal coverage. 60.
31 PASSIVATION 1 metal-to-p+, Mag. 28,000x METAL P+ POLY THINNING metal-to-n+, Mag. 30,000x METAL N+ GATE OXIDE PASSIVATION 1 METAL metal-to-poly, Mag. 26,000x POLY LOCAL OXIDE Figure 17. SEM section views of metal contacts.
32 POLY Mag. 2500x POLY Mag. 5000x POLY N+ Mag. 5000x P+ Figure 18. Topological SEM views illustrating poly patterning. 0.
33 Mag. 4000x ACTIVE LOAD DEVICE POLY Mag. 7000x POLY Mag. 17,000x DIFFUSION Figure 19. SEM views illustrating poly coverage. 60.
34 PASSIVATION 1 POLY SILICIDE METAL P-channel, Mag. 26,000x P+ S/D GATE OXIDE PASSIVATION 1 METAL POLY SILICIDE PRE-METAL GLASS N-channel, Mag. 26,000x N+ S/D GATE OXIDE METAL PRE-METAL GLASS SILICIDE SIDEWALL SPACER glass etch, Mag. 40,000x SOG POLY Figure 20. SEM section views illustrating typical gates.
35 POLY LINKS Mag. 10,000x POLY Mag. 20,000x Figure 21 Topological SEM views of poly links. 0.
36 PRE-METAL GLASS POLY SILICIDE LOCAL OXIDE BIRDSBEAK GATE OXIDE Figure 22. SEM section view of a local oxide birdsbeak. Mag. 40,000x. METAL PASSIVATION 1 PRE-METAL GLASS LOCAL OXIDE Mag. 26,000x STEP AT WELL BOUNDARY Mag. 800x N-WELL P-WELL P SUBSTRATE Figure 23. SEM and optical views illustrating the well structure.
37 W SILICIDE SIDEWALL SPACER SOG PSG PASSIVATION 2 Dallas Semiconductor DS80C320,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, P-WELL POLY N+ S/D LOCAL OXIDE P SUBSTRATE METAL N-WELL Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate Figure 24. Color cross section drawing illustrating device structure. PASSIVATION 1 P+ S/D
38 BIT LINES metal WORD LINES unlayered Figure 25. Topological SEM views of the SRAM array. Mag. 1600x, 0.
39 metal unlayered Figure 26. Perspective SEM views of the SRAM array. Mag. 2000x, 60.
40 BIT LINES metal WORD LINES unlayered Figure 27. Detailed SEM views of the SRAM array. Mag. 4000x, 60.
41 BIT LINES metal WORD BIT unlayered BIT GND WORD 6P 5P BIT 1N 2N BIT 4N 3N Figure 28. Topological SEM views of an SRAM cell along with the schematic. Mag. 4000x, 0.
42 METAL BIT LINE metal POLY WORD LINES POLY ON GATE OXIDE DIFFUSIONS POLY ON LOCAL OXIDE poly Figure 29. Topological SEM views of an MROM array on the DS80C320. Mag. 5000x, 0.
43 METAL metal, Mag. 6000x POLY GATES poly, Mag. 6000x DIFFUSION POLY (ON LOCAL OXIDE) poly, Mag. 10,000x POLY GATE Figure 30. Perspective SEM views of the MROM array. Mag. 6000x, 60.
44 metal unlayered Figure 31. Optical views of input protection. Mag. 320x.
45 Figure 32. Optical views of typical circuit layout. Mag. 500x.
46 SLOTS POLY Mag. 320x SLOTS POLY Mag. 800x Figure 32a. Optical views of poly interconnect.
47 POLY SLOT Mag. 1000x POLY Mag. 2000x Figure 32b. Perspective SEM views of poly interconnect. 60.
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