Dallas Semicoductor DS80C320 Microcontroller

Size: px
Start display at page:

Download "Dallas Semicoductor DS80C320 Microcontroller"

Transcription

1 Construction Analysis Dallas Semicoductor DS80C320 Microcontroller Report Number: SCA Global Semiconductor Industry the Serving Since N. 75th Street Scottsdale, AZ Phone: Fax: Internet:

2 INDEX TO TEXT TITLE PAGE INTRODUCTION 1 MAJOR FINDINGS 1 TECHNOLOGY DESCRIPTION Assembly 2 Die Process 2-3 ANALYSIS RESULTS I Package and Assembly 4 ANALYSIS RESULTS II Die Process 5-7 ANALYSIS PROCEDURE 8 TABLES Overall Quality Evaluation 9 Package Markings 10 Wirebond Strength 10 Die Material Analysis (EDX and WDX) 10 Horizontal Dimensions 11 Vertical Dimensions 11 - i -

3 INTRODUCTION This report describes a construction analysis of the Dallas Semiconductor DS80C320 Microcontroller. Five devices packaged in 44-pin Plastic Leaded Chip Carriers (PLCCs) were received for the analysis. Devices were date coded MAJOR FINDINGS Questionable Items: 1 Metal thinned up to 85 percent 2 at some contact edges (Figure 17). No cap or barrier metals were used and this amount of thinning of metal that is only of 0.45 microns nominal thickness should be discussed with the manufacturer. Special Features: An SRAM array and a MROM array were employed on the device. Somewhat unusual CMOS process having no reflow glass (uses SOG), and relatively deep S/D diffusions and active loads. Large polycide interconnect areas. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application. 2 Seriousness depends on design margins

4 TECHNOLOGY DESCRIPTION Assembly: Devices were packaged in 44-pin plastic leaded (PLCC) chip carriers. The die was mounted to the paddle using a silver epoxy die attach. Die separation was by sawing. Wirebonding was by the thermosonic ball bond method using 1.1 mil O.D. gold wire. Lead-locking provisions (anchors and holes) at all pins. Die Process : Devices were fabricated using a selective oxidation, twin-well CMOS process in a P substrate. No epi was used. No die coat was present. Passivation consisted of a layer of nitride over a thick layer of silicon-dioxide. Metallization consisted of a single layer of dry-etched metal. The metal layer consisted of aluminum and did not use a cap or barrier. Standard contacts were used (no plugs). Pre-metal dielectric consisted of a layer of phosphosilicate glass (PSG) over densified oxides and covered with a layer of SOG. The glass was not reflowed

5 TECHNOLOGY DESCRIPTION (continued) A single layer of polycide was used (tungsten-silicide). It was used to form all gates on the die and the word lines in both memory arrays. It was also used as a layer of interconnect. Direct poly-to-diffusion (buried) contacts were not used. Definition of the poly was by a normal dry etch. Fairly deep implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. Oxide sidewall spacers on the gates were left in place. Local oxide (LOCOS) isolation. A slight step was present in the oxide at the edge of the well boundaries indicating a twin-well process was used. SRAM array: A 6T SRAM cell design. Metal was used to form the bit lines. Poly was used to form the word/select lines, storage gates and pull-up devices. Long active P-channel loads were employed. MROM arrays: Metal formed the bit lines and poly formed the word lines. The array was programmed at the field oxide (diffusion) level (see Figures 29 and 30). Redundancy fuses were not present

6 ANALYSIS RESULTS I Package and Assembly: Figures 1-9 Questionable Items: 1 None. Special Features: None. General Items: Devices were packaged in 44-pin plastic leaded (PLCC) chip carriers. Overall package quality: Good. No significant defects were noted on the external or internal portions of the package. No cracks or voids were noted in the plastic. Leadframe: The leadframe was constructed of copper. External tinning consisted of tin-lead (SnPb) while internal plating consisted of silver (Ag). No gaps were noted at lead exits. Die dicing: Die separation was by sawing of normal quality. No large cracks or chips were present. Die attach: A silver epoxy of normal quality was used to attach the die to the header. No significant voids were noted in the die attach. Wirebonding was by the thermosonic ball bond method using 1.1 mil O.D. gold wire. Bonds were well formed and placement was good. Wirepull strengths were normal with no bond lifts (see page 10). 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

7 ANALYSIS RESULTS II Die Process: Figures 10-32b Questionable Items: 1 None. Special Features: An SRAM array and a MROM array were employed on the device. Somewhat unusual CMOS process having no reflow glass (uses SOG), and relatively deep S/D diffusions and active loads. Large polycide interconnect areas. General Items: Fabrication process: Devices were fabricated using a selective oxidation, twin-well CMOS process in a P substrate. No epi was used. Design implementation: Die layout was clean and efficient. Alignment was good at all levels. No damage or contamination was found. Die coat: No die coat was present. Overlay passivation: A layer of nitride over a layer of silicon-dioxide. Overlay integrity test indicated defect-free passivation. Edge seal was good as it extended into the scribe lane to seal the metallization. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application. 2 Seriousness depends on design margins

8 ANALYSIS RESULTS II (continued) Metallization: A single layer of metal consisting of aluminum. No cap or barrier metals was used. Metal patterning: The metal layer was patterned by a dry etch of normal quality. All contacts were completely surrounded by aluminum. Metal defects: No voiding, notching, or neckdown was noted in the metal layer. No silicon nodules were noted following the removal of the aluminum layer. Metal step coverage: Worst case aluminum thinning was 85 percent at contact edges. MIL-STD allows up to 70 percent metal thinning for contacts of this size, but in this case the metal already seems to be unusually thin normally, and no cap or barriers are present. Typical aluminum thinning was 60 percent. Pre-metal dielectric: A layer of SOG over a layer of phosphosilicate glass over densified oxides was used under the metal. No reflow was performed. This is a somewhat unusual structure but no problems were found. Contact defects: None. No significant over-etching of the contacts was noted and no pitting or silicon mound growth was present. Polysilicon: A single layer of polycide (tungsten- silicide) was used to form all gates on the die and for interconnect (crossunders). Slots were noted within some of the large poly crossunders (Figures 32a and 32b). Direct poly-to-diffusion (buried) contacts were not used. Poly links are inactive and appear to have been a mask modification (Figure 21). Definition was by a dry etch of normal quality. Diffusions: Fairly deep implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. Oxide sidewall spacers were used at all gates and left in place. No silicide was present on the diffusions

9 ANALYSIS RESULTS II (continued) Local oxide (LOCOS) isolation was used. No problems were noted. The slight step present in the oxide at the well boundary indicates a twin-well process was employed. SRAM array: Two blocks of SRAM memory were present. A 6T SRAM cell design was employed. Metal was used to form the bit lines. Poly was used to form the word/select lines, storage gate and pull-up devices. Cell pitch was relatively large 12.2 x 22.8 microns. MROM array: Two separated blocks of MROM arrays were present on the device. Metal formed the bit lines and poly formed the word lines. No problems of any sort were noted in the SRAM nor MROM arrays. Both arrays were programmed at the field oxide (diffusion) level (see Figures 29 and 30). Special items: ESD tests were performed on Sample 4 and revealed that all pins passed pulses of +4000V. - Latch-up tests were performed on Sample 5 and revealed that no pin latched-up

10 PROCEDURE The devices were subjected to the following analysis procedures: External inspection ESD and Latch-up tests X-ray Package section Decapsulate Internal optical inspection SEM of passivation and assembly features Passivation integrity test Wirepull test Passivation removal SEM inspection of metal Metal removal Delayer to silicon and inspect poly/die surface Die sectioning (90 for SEM) * Die material analysis Measure horizontal dimensions Measure vertical dimensions * Delineation of cross-sections is by silicon etch unless otherwise indicated

11 OVERALL QUALITY EVALUATION: Overall Rating: Normal to Poor * DETAIL OF EVALUATION Package integrity Package markings Die placement Wirebond placement Wire spacing Wirebond quality Die attach quality Dicing quality Die attach method Dicing method Wirebond method N N N N N N N N Silver epoxy Sawn Thermosonic ball bonds using 1.1 mil gold wire. Die surface integrity: Toolmarks (absence) G Particles (absence) G Contamination (absence) G Process defects (absence) G General workmanship N Passivation integrity G Metal definition N Metal integrity NP * Contact coverage G Contact registration G * Metal thinning up to 85 percent on metal that is only 0.45 micron thick. G = Good, P = Poor, N = Normal, NP = Normal/Poor - 9 -

12 PACKAGE MARKINGS (TOP) DALLAS DS80C B3-QCG (BOTTOM) KOREA 478AA WIREBOND STRENGTH Wire material: Die pad material: 1.1 mil O.D. gold aluminum Sample # 1 # of wires pulled: 15 Bond lifts: 0 Force to break - high: 17g - low: 15g - avg.: 15.8g - std. dev.: 0.9 DIE MATERIAL ANALYSIS (EDX and WDX) Overlay passivation: Metallization: Pre-metal dielectric: Polycide: A layer of nitride over a layer of silicon- dioxide. Aluminum (Al). A phosphosilicate glass (PSG) containing 3.6 wt. % phosphorus. No boron was detected. Topped with a layer of SOG. Tungsten (W) silicide. WDX analysis

13 HORIZONTAL DIMENSIONS Die size: 4.8 x 4.8 mm (191 x 191 mils) Die area: 23 mm 2 (36,481 mils 2 ) Min pad size: 0.08 x 0.08 mm (3.3 x 3.3 mils) Min pad window: 0.07 x 0.07 mm (2.7 x 2.7 mils) Min pad space: 0.15 mm (5.8 mils) Min metal width: 0.85 micron Min metal space: 1.3 micron Min metal pitch: 2.15 microns Min contact: 1.0 micron Min poly width: 0.85 micron Min poly space: 1.0 micron Min gate length - (N-channel): * 0.85 micron - (P-channel): 0.85 micron SRAM cell size: 278 microns 2 SRAM cell pitch: 12.2 x 22.8 microns MROM cell size: 14 microns MROM cell pitch: 3.5 x 4 microns VERTICAL DIMENSIONS Die thickness: 0.45 mm (17.8 mils) Layers: Passivation 2: 0.5 micron Passivation 1: 1 micron Metal: 0.45 micron Pre-metal dielectric: 0.5 micron (avg.) Oxide on poly: 0.15 micron Poly: 0.4 micron Local oxide: 0.5 micron N+ S/D: 0.35 micron P + S/D: 0.3 micron N-well: 5 microns P-well: 5 microns * Physical gate length

14 INDEX TO FIGURES PACKAGING AND ASSEMBLY Figures 1-9 DIE LAYOUT AND IDENTIFICATION Figures 10-11a PHYSICAL DIE STRUCTURES Figures 12-32b COLOR DRAWING OF DIE STRUCTURE Figure 24 SRAM MEMORY CELLS Figures MROM MEMORY CELLS Figures INPUT PROTECTION CIRCUIT Figure 31 GENERAL CIRCUIT LAYOUT Figure 32 POLY DESIGN FEATURES Figures 32a and 32b - ii -

15 PIN 44 = VCC PIN 22 AND 23 = GND Figure 1. Package photographs and pinout of the Dallas Semiconductor DS80C320. Mag. 3x.

16 PIN 1 top view side view Figure 2. X-ray views of the package. Mag. 3x.

17 LEADFRAME PLASTIC PACKAGE DIE HEADER Figure 3. Package section views illustrating general package construction. Mag. 13x.

18 LEADFRAME PLASTIC PACKAGE Mag. 20x Cu LEADFRAME Mag. 100x PLASTIC PACKAGE PLASTIC PACKAGE SnPb TINNING Mag. 300x Cu LEADFRAME Figure 4. Optical and SEM views of lead forming and lead plating.

19 DIE SECTIONING ARTIFACT Cu PADDLE Mag. 65x DIE Ag -EPOXY DIE ATTACH Cu PADDLE Ag PLATING Mag. 500x Figure 5. Optical package section views of die dicing and die attach.

20 DIE DIE ATTACH ETCHED DURING DECAPSULATION Mag. 120x EDGE OF PASSIVATION Mag. 1000x Figure 6. SEM views of dicing and die edge seal. 60.

21 123 DIE EDGE METAL SCRIBE LANE Mag. 1400x PASSIVATION 2 PASSIVATION 1 Mag. 6500x Figure 7. SEM views of the edge seal. LOCAL OXIDE

22 Au BOND DIE Figure 8. Optical section view of a typical ball bond. Mag. 800x. Au Mag. 600x PAD Au Mag. 500x LEADFRAME Figure 9. SEM views of typical wirebonds. 60.

23 PIN 2 Figure 10. Whole die photograph of the Dallas Semiconductor DS80C320. Mag. 32x.

24 Mag. 200x Mag. 320x Figure 11. Identification markings from the die surface.

25 Mag. 320x Mag. 320x Mag. 500x Figure 11a. Additional die markings from the surface.

26 PASSIVATION 2 PASSIVATION 1 Mag. 6500x STEP METAL N-WELLS METAL PASSIVATION 2 PASSIVATION 1 POLY GATE Mag. 6500x STEP P+ N-WELL PASSIVATION 2 PASSIVATION 1 METAL SOG Mag. 13,000x P+ POLY GATE Figure 12. SEM section views illustrating general device structure.

27 Mag. 2500x Mag. 12,000x Figure 13. SEM views of overlay passivation coverage. 60.

28 PASSIVATION 2 PASSIVATION 1 METAL Mag. 26,000x PASSIVATION 1 METAL PRE-METAL GLASS Mag. 40,000x Figure 14. SEM section views of metal line profiles.

29 METAL Mag. 1600x METAL Mag. 3200x METAL Mag. 6500x Figure 15. Topological SEM views illustrating metal patterning. 0.

30 METAL Mag. 3200x METAL Mag. 5200x METAL Mag. 26,000x Figure 16. Perspective SEM views illustrating metal coverage. 60.

31 PASSIVATION 1 metal-to-p+, Mag. 28,000x METAL P+ POLY THINNING metal-to-n+, Mag. 30,000x METAL N+ GATE OXIDE PASSIVATION 1 METAL metal-to-poly, Mag. 26,000x POLY LOCAL OXIDE Figure 17. SEM section views of metal contacts.

32 POLY Mag. 2500x POLY Mag. 5000x POLY N+ Mag. 5000x P+ Figure 18. Topological SEM views illustrating poly patterning. 0.

33 Mag. 4000x ACTIVE LOAD DEVICE POLY Mag. 7000x POLY Mag. 17,000x DIFFUSION Figure 19. SEM views illustrating poly coverage. 60.

34 PASSIVATION 1 POLY SILICIDE METAL P-channel, Mag. 26,000x P+ S/D GATE OXIDE PASSIVATION 1 METAL POLY SILICIDE PRE-METAL GLASS N-channel, Mag. 26,000x N+ S/D GATE OXIDE METAL PRE-METAL GLASS SILICIDE SIDEWALL SPACER glass etch, Mag. 40,000x SOG POLY Figure 20. SEM section views illustrating typical gates.

35 POLY LINKS Mag. 10,000x POLY Mag. 20,000x Figure 21 Topological SEM views of poly links. 0.

36 PRE-METAL GLASS POLY SILICIDE LOCAL OXIDE BIRDSBEAK GATE OXIDE Figure 22. SEM section view of a local oxide birdsbeak. Mag. 40,000x. METAL PASSIVATION 1 PRE-METAL GLASS LOCAL OXIDE Mag. 26,000x STEP AT WELL BOUNDARY Mag. 800x N-WELL P-WELL P SUBSTRATE Figure 23. SEM and optical views illustrating the well structure.

37 W SILICIDE SIDEWALL SPACER SOG PSG PASSIVATION 2 Dallas Semiconductor DS80C320,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, P-WELL POLY N+ S/D LOCAL OXIDE P SUBSTRATE METAL N-WELL Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate Figure 24. Color cross section drawing illustrating device structure. PASSIVATION 1 P+ S/D

38 BIT LINES metal WORD LINES unlayered Figure 25. Topological SEM views of the SRAM array. Mag. 1600x, 0.

39 metal unlayered Figure 26. Perspective SEM views of the SRAM array. Mag. 2000x, 60.

40 BIT LINES metal WORD LINES unlayered Figure 27. Detailed SEM views of the SRAM array. Mag. 4000x, 60.

41 BIT LINES metal WORD BIT unlayered BIT GND WORD 6P 5P BIT 1N 2N BIT 4N 3N Figure 28. Topological SEM views of an SRAM cell along with the schematic. Mag. 4000x, 0.

42 METAL BIT LINE metal POLY WORD LINES POLY ON GATE OXIDE DIFFUSIONS POLY ON LOCAL OXIDE poly Figure 29. Topological SEM views of an MROM array on the DS80C320. Mag. 5000x, 0.

43 METAL metal, Mag. 6000x POLY GATES poly, Mag. 6000x DIFFUSION POLY (ON LOCAL OXIDE) poly, Mag. 10,000x POLY GATE Figure 30. Perspective SEM views of the MROM array. Mag. 6000x, 60.

44 metal unlayered Figure 31. Optical views of input protection. Mag. 320x.

45 Figure 32. Optical views of typical circuit layout. Mag. 500x.

46 SLOTS POLY Mag. 320x SLOTS POLY Mag. 800x Figure 32a. Optical views of poly interconnect.

47 POLY SLOT Mag. 1000x POLY Mag. 2000x Figure 32b. Perspective SEM views of poly interconnect. 60.

Motorola MPA1016FN FPGA

Motorola MPA1016FN FPGA Construction Analysis Motorola MPA1016FN FPGA Report Number: SCA 9711-561 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781

More information

Lattice isplsi1032e CPLD

Lattice isplsi1032e CPLD Construction Analysis Lattice isplsi1032e CPLD Report Number: SCA 9612-522 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925

More information

Motorola MC68360EM25VC Communication Controller

Motorola MC68360EM25VC Communication Controller Construction Analysis EM25VC Communication Controller Report Number: SCA 9711-562 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

UMC UM F-7 2M-Bit SRAM

UMC UM F-7 2M-Bit SRAM Construction Analysis UMC UM 613264F-7 2M-Bit SRAM Report Number: SCA 9609-511 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM

Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM Construction Analysis Mosel Vitelic MS62256CLL-70PC 256Kbit SRAM Report Number: SCA 9703-499 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Rockwell R RF to IF Down Converter

Rockwell R RF to IF Down Converter Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

SGS-Thomson M28C K EEPROM

SGS-Thomson M28C K EEPROM Construction Analysis SGS-Thomson M28C64-121 64K EEPROM Report Number: SCA 9710-559 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM

Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM Construction Analysis Micron Semiconductor MT5C64K16A1DJ 64K x 16 SRAM Report Number: SCA 9412-394 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:

More information

SGS-Thomson M17C1001 1Mb UVEPROM

SGS-Thomson M17C1001 1Mb UVEPROM Construction Analysis SGS-Thomson M17C1001 1Mb UVEPROM Report Number: SCA 9612-518 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780

More information

DEC SA-110S StrongARM 32-Bit Microprocessor

DEC SA-110S StrongARM 32-Bit Microprocessor Construction Analysis DEC SA-110S StrongARM 32-Bit Microprocessor Report Number: SCA 9704-535 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Maximum MAX662 12V DC-DC Converter

Maximum MAX662 12V DC-DC Converter Construction Analysis Maximum MAX662 12V DC-DC Converter Report Number: SCA 9512-445 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

NKK NR4645LQF Bit RISC Microprocessor

NKK NR4645LQF Bit RISC Microprocessor Construction Analysis NKK NR4645LQF-133 64-Bit RISC Microprocessor Report Number: SCA 9707-547 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9870

More information

NEC 79VR5000 RISC Microprocessor

NEC 79VR5000 RISC Microprocessor Construction Analysis NEC 79VR5000 RISC Microprocessor Report Number: SCA 9711-567 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Analog Devices ADSP KS-160 SHARC Digital Signal Processor

Analog Devices ADSP KS-160 SHARC Digital Signal Processor Construction Analysis Analog Devices ADSP-21062-KS-160 SHARC Digital Signal Processor Report Number: SCA 9712-575 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,

More information

Xilinx XC4036EX FPGA

Xilinx XC4036EX FPGA Construction Analysis Xilinx XC4036EX FPGA Report Number: SCA 9706-544 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925

More information

Micron Semiconductor MT4LC16M4H9 64Mbit DRAM

Micron Semiconductor MT4LC16M4H9 64Mbit DRAM Construction Analysis Micron Semiconductor MT4LC16M4H9 64Mbit DRAM Report Number: SCA 9705-539 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone:

More information

Oki M A-60J 16Mbit DRAM (EDO)

Oki M A-60J 16Mbit DRAM (EDO) Construction Analysis Oki M5117805A-60J 16Mbit DRAM (EDO) Report Number: SCA 9707-545 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Lattice 3256A-90LM PLD

Lattice 3256A-90LM PLD Construction Analysis PLD Report Number: SCA 9705-538 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781 e-mail: ice@ice-corp.com

More information

SGS-Thomson L4990 Controller

SGS-Thomson L4990 Controller Construction Analysis SGS-Thomson L4990 Controller Report Number: SCA 9710-560 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM

Hitachi A 64Mbit (8Mb x 8) Dynamic RAM Construction Analysis Hitachi 5165805A 64Mbit (8Mb x 8) Dynamic RAM Report Number: SCA 9712-565 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone:

More information

Intel Pentium Processor W/MMX

Intel Pentium Processor W/MMX Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:

More information

Xilinx XC4036XL-1C FPGA

Xilinx XC4036XL-1C FPGA Construction Analysis Xilinx XC4036XL-1C FPGA Report Number: SCA 9709-553 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781

More information

National Semiconductor LM2672 Simple Switcher Voltage Regulator

National Semiconductor LM2672 Simple Switcher Voltage Regulator Construction Analysis National Semiconductor LM2672 Simple Switcher Voltage Regulator Report Number: SCA 9712-570 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,

More information

VTC VM365830VSJ Pre-Amp

VTC VM365830VSJ Pre-Amp Construction Analysis VTC VM365830VSJ Pre-Amp Report Number: SCA 9708-549 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781

More information

Altera EPM7128SQC EPLD

Altera EPM7128SQC EPLD Construction Analysis Altera EPM7128SQC160-15 EPLD Report Number: SCA 9712-569 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Motorola PC603R Microprocessor

Motorola PC603R Microprocessor Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Integrated Circuit Engineering Corporation. DRAMs

Integrated Circuit Engineering Corporation. DRAMs DRAMs As generally known, the focus of technology in this product category continues to be complex vertical polysilicon structures to reduce cell area. This not only pushes the limits of deposition and

More information

Integrated Circuit Engineering Corporation EPROM

Integrated Circuit Engineering Corporation EPROM EPROM There was lots of discussion and many technical papers covering the promises of EPROM (typically Flash) at the IEDM conference last December, but here as in the other memory areas, not much in the

More information

Renesas M5M40R326 32Mbit DRAM Memory Structural Analysis

Renesas M5M40R326 32Mbit DRAM Memory Structural Analysis August 13, 2004 Renesas M5M40R326 32Mbit DRAM Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,

More information

9/4/2008 GMU, ECE 680 Physical VLSI Design

9/4/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter II CMOS Manufacturing Process 1 Dual-Well Trench-Isolated CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 p-well poly n-well SiO 2 n+ p-epi p+ p+ 2 Schematic Layout

More information

Chapter 2 Manufacturing Process

Chapter 2 Manufacturing Process Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS

More information

Silicon Wafer Processing PAKAGING AND TEST

Silicon Wafer Processing PAKAGING AND TEST Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)

More information

Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1

Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated

More information

Chapter 4 : ULSI Process Integration (0.18 m CMOS Process)

Chapter 4 : ULSI Process Integration (0.18 m CMOS Process) Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)

More information

Manufacturing Process

Manufacturing Process Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30, 2002 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten

More information

ECE 659. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Manufacturing.

ECE 659. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Manufacturing. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 0, 00 1 CMOS Process 1 A Modern CMOS Process gate-oxide TiSi AlCu Tungsten

More information

Manufacturing Process

Manufacturing Process CMOS Manufacturing Process CMOS Process 1 A Modern CMOS Process gate-oxide TiSi AlCu Tungsten SiO n+ p-well p-epi poly n-well p+ SiO p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V DD

More information

CMOS Manufacturing Process

CMOS Manufacturing Process CMOS Manufacturing Process CMOS Process A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V

More information

Lecture 200 BiCMOS Technology (12/12/01) Page 200-1

Lecture 200 BiCMOS Technology (12/12/01) Page 200-1 Lecture 200 BiCMOS Technology (12/12/01) Page 200-1 LECTURE 200 BICMOS TECHNOLOGY (READING: Text-Sec. 2.11) INTRODUCTION Objective Illustrate BiCMOS technology Outline Introduction Physical process illustration

More information

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters

More information

10 Manor Parkway, Suite C Salem, New Hampshire

10 Manor Parkway, Suite C Salem, New Hampshire Micro-Precision Technologies (MPT) is an independent manufacturer of hybrid integrated circuits, multichip modules, and high-precision thick film substrates for the military, medical, avionics, optoelectronics,

More information

CMOS Manufacturing process. Design rule set

CMOS Manufacturing process. Design rule set CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital

More information

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing CS/ECE 5710/6710 CMOS Processing Addison-Wesley N-type Transistor D G +Vgs + Vds S N-type from the top i electrons - Diffusion Mask Mask for just the diffused regions Top view shows patterns that make

More information

Beam Leads. Spider bonding, a precursor of TAB with all-metal tape

Beam Leads. Spider bonding, a precursor of TAB with all-metal tape Beam Leads The vast majority of chips are intended for connection with thermosonic bonds: all other methods require some modification to the wafer. As early as 1972, Jordan described three gang-bonding

More information

EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 FABRICATION OF MOS CIRCUITS 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer

More information

CMOS FABRICATION. n WELL PROCESS

CMOS FABRICATION. n WELL PROCESS CMOS FABRICATION n WELL PROCESS Step 1: Si Substrate Start with p- type substrate p substrate Step 2: Oxidation Exposing to high-purity oxygen and hydrogen at approx. 1000 o C in oxidation furnace SiO

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Processing Technology Topics CMOS Processing Technology Semiconductor Processing How do we make a transistor? Fabrication Process Wafer Processing Silicon single crystal

More information

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative

More information

ECE321 Electronics I

ECE321 Electronics I ECE321 Electronics I Lecture 19: CMOS Fabrication Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Miller Effect Interconnect

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3)

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Charlie C. Megia Golden Altos Corporation 402 South Hillview Drive, Milpitas, CA 95035 cmegia@goldenaltos.com

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

Manufacturing Process

Manufacturing Process Manufacturing Process 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process 3 Single-crystal ingot

More information

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO

More information

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Semiconductor Manufacturing Technology. IC Fabrication Process Overview Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you

More information

EE 330 Lecture 9. IC Fabrication Technology Part 2

EE 330 Lecture 9. IC Fabrication Technology Part 2 EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this

More information

1 Thin-film applications to microelectronic technology

1 Thin-film applications to microelectronic technology 1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.

More information

EE 434 Lecture 9. IC Fabrication Technology

EE 434 Lecture 9. IC Fabrication Technology EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and

More information

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width Microelectronics Introduction to the IC technology M.Rencz 11 September, 2002 9/16/02 1/37 Integrated circuits Development is controlled by the roadmaps. Self-fulfilling predictions for the tendencies

More information

Packaging and Ball Bonding Gold wire makes contact from bonding pads on chip to package Gold wire is formed into ball to make contact Uses an

Packaging and Ball Bonding Gold wire makes contact from bonding pads on chip to package Gold wire is formed into ball to make contact Uses an Packaging and Ball Bonding Gold wire makes contact from bonding pads on chip to package Gold wire is formed into ball to make contact Uses an ultrasonic process & heat Process called "Ball Bonding" Wedge

More information

Fabrication and Layout

Fabrication and Layout Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1,

More information

Lecture 22: Integrated circuit fabrication

Lecture 22: Integrated circuit fabrication Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................

More information

We are moving to 155 Donner Lab From Thursday, Feb 2 We will be able to accommodate everyone!

We are moving to 155 Donner Lab From Thursday, Feb 2 We will be able to accommodate everyone! -Spring 006 Digital Integrated Circuits Lecture 4 CMOS Manufacturing Process Design Rules EECS141 1 Good News! We are moving to 155 Donner Lab From Thursday, Feb We will be able to accommodate everyone!

More information

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 33 Problems in LOCOS + Trench Isolation and Selective Epitaxy So, we are discussing

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last

More information

JOINT INDUSTRY STANDARD

JOINT INDUSTRY STANDARD JOINT INDUSTRY STANDARD AUGUST 1999 Semiconductor Design Standard for Flip Chip Applications ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Semiconductor Design Standard for Flip Chip Applications About

More information

This Appendix discusses the main IC fabrication processes.

This Appendix discusses the main IC fabrication processes. IC Fabrication B B.1 Introduction This Appendix discusses the main IC fabrication processes. B.2 NMOS fabrication NMOS transistors are formed in a p-type substrate. The NMOS fabrication process requires

More information

Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs

Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs Improvement of Laser Fuse Processing of Fine Pitch Link Structures for Advanced Memory Designs Joohan Lee, Joseph J. Griffiths, and James Cordingley GSI Group Inc. 60 Fordham Rd. Wilmington, MA 01887 jlee@gsig.com

More information

FABRICATION of MOSFETs

FABRICATION of MOSFETs FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the

More information

ASIM-X MEMS-Specific Design Rules

ASIM-X MEMS-Specific Design Rules ASIM-X MEMS-Specific Design Rules Version 2 Revised April 5, 2006. This is a beta version, subject to change. Revised by G. K. Fedder, Carnegie Mellon University. 1 Process Overview ASIM-X, an acronym

More information

Chapter 3 CMOS processing technology

Chapter 3 CMOS processing technology Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),

More information

TOWARD MEMS!Instructor: Riadh W. Y. Habash

TOWARD MEMS!Instructor: Riadh W. Y. Habash TOWARD MEMS!Instructor: Riadh W. Y. Habash Students are presented with aspects of general production and manufacturing of integrated circuit (IC) products to enable them to better liaise with and participate

More information

EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING. A. Jalar, M. F. Rosle and M. A. A.

EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING. A. Jalar, M. F. Rosle and M. A. A. EFFECTS OF THERMAL AGING ON INTERMETALLIC COMPOUNDS AND VOIDS FORMATION IN AuAl WIRE BONDING A. Jalar, M. F. Rosle and M. A. A. Hamid School of Applied Physics, Faculty of Science and Technology, Universiti

More information

UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules

UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules 2. CMOS Fabrication, Layout, Design Rules Last module: Introduction to the course How a transistor works CMOS transistors This module: CMOS Fabrication Design Rules CMOS Fabrication CMOS transistors are

More information

EE BACKEND TECHNOLOGY - Chapter 11. Introduction

EE BACKEND TECHNOLOGY - Chapter 11. Introduction 1 EE 212 FALL 1999-00 BACKEND TECHNOLOGY - Chapter 11 Introduction Backend technology: fabrication of interconnects and the dielectrics that electrically and physically separate them. Aluminum N+ Early

More information

Cost of Integrated Circuits

Cost of Integrated Circuits Cost of IC Design 1 Cost of Integrated Circuits NRE (Non-Recurrent Engineering) costs fixed design time and effort, mask generation independent of sales volume / number of products one-time cost factor

More information

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Frank Grano, Felix Bruno Huntsville, AL Dana Korf, Eamon O Keeffe San Jose, CA Cheryl Kelley Salem, NH Joint Paper by Sanmina-SCI Corporation EMS, GTS

More information

Lecture 1A: Manufacturing& Layout

Lecture 1A: Manufacturing& Layout Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1 The Manufacturing Process For a great tour through the IC manufacturing

More information

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation. Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed

More information

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY CHAPTER - 4 CMOS PROCESSING TECHNOLOGY Samir kamal Spring 2018 4.1 CHAPTER OBJECTIVES 1. Introduce the CMOS designer to the technology that is responsible for the semiconductor devices that might be designed

More information

Destructive Physical Analysis (DPA) Program Methodology

Destructive Physical Analysis (DPA) Program Methodology Destructive Physical Analysis (DPA) Program Methodology DPA: Introduction Destructive Physical Analysis (DPA) is a comprehensive quality assessment for workmanship on Printed Circuit Board Assemblies (PCBAs).

More information

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding Chapter 4 Fabrication Process of Silicon Carrier and Gold-Gold Thermocompression Bonding 4.1 Introduction As mentioned in chapter 2, the MEMs carrier is designed to integrate the micro-machined inductor

More information

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services. ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services.   ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant CX Thin Fil s Resistors Attenuators Thin-Film Products Thin-Film Services www.cxthinfilms.com ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant www.cxthinfilms.com sales@cxthinfilms.com +1 (401) 461-5500

More information

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Advanced Packaging Business Development Asia Introduction to Fan-Out WLP Introduction World of mobile gadgetry continues to rapidly evolve

More information

Qualification and Performance Specification for High Frequency (Microwave) Printed Boards

Qualification and Performance Specification for High Frequency (Microwave) Printed Boards Qualification and Performance Specification for High Frequency (Microwave) Printed Boards Developed by the High Speed/High Frequency Board Performance Subcommittee (D-22) of the High Speed/High Frequency

More information

Automotive Electronics Council Component Technical Committee

Automotive Electronics Council Component Technical Committee ATTACHMENT 1 AEC - Q100-001 REV-C WIRE BOND SHEAR TEST Acknowledgment Any document involving a complex technology brings together experience and skills from many sources. The Automotive Electronics Counsel

More information

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding

More information

Fairchild Semiconductor Application Note June 1983 Revised March 2003

Fairchild Semiconductor Application Note June 1983 Revised March 2003 Fairchild Semiconductor Application Note June 1983 Revised March 2003 High-Speed CMOS (MM74HC) Processing The MM74HC logic family achieves its high speed by utilizing microcmos Technology. This is a 3.5

More information

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION. Universiti Kebangsaan Malaysia UKM Bangi,Selangor, Malaysia

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION. Universiti Kebangsaan Malaysia UKM Bangi,Selangor, Malaysia CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION W. Shualdi 1, W. M. S. W. Suliman 1, A. Isnin 2 and N. A. Mohamad 2 1 Advanced Semiconductor Packaging (ASPAC) Research Laboratory Universiti

More information

Qualification Report. June, 1994, QTP# Version 1.1 CY7C46X/47X, MINNESOTA FAB MARKETING PART NUMBER DEVICE DESCRIPTION. Cascadable 32K x 9 FIFO

Qualification Report. June, 1994, QTP# Version 1.1 CY7C46X/47X, MINNESOTA FAB MARKETING PART NUMBER DEVICE DESCRIPTION. Cascadable 32K x 9 FIFO Qualification Report June, 1994, QTP# 92361 Version 1.1 CY7C46X/47X, MINNESOTA FAB MARKETING PART NUMBER CY7C460 CY7C462 CY7C464 CY7C470 CY7C472 CY7C474 DEVICE DESCRIPTION Cascadable 8K x 9 FIFO Cascadable

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MASW-007921 2mm 8-Lead Plastic Package QTR-0148 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax: (978)

More information

Working Around the Fluorine Factor in Wire Bond Reliability

Working Around the Fluorine Factor in Wire Bond Reliability Working Around the Fluorine Factor in Wire Bond Reliability Jeanne Pavio, Robert Jung, Craig Doering, Randal Roebuck, and Mario Franzone Texas Instruments Dallas, Texas Working Around the Fluorine Factor

More information

Qualification Report CASCADEABLE FIFOS. November 1995, QTP# Version 1.2 DEVICE DESCRIPTION MARKETING PART NUMBER. 1K x 9 Cascadeable FIFO

Qualification Report CASCADEABLE FIFOS. November 1995, QTP# Version 1.2 DEVICE DESCRIPTION MARKETING PART NUMBER. 1K x 9 Cascadeable FIFO Qualification Report November 1995, QTP# 94468 Version 1.2 CASCADEABLE FIFOS MARKETING PART NUMBER CY7C419 CY7C420/CY7C421 CY7C424/CY7C425 DEVICE DESCRIPTION 256 x 9 Cascadeable FIFO 512 x 9 Cascadeable

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MAAM-008819 2mm 8-Lead PDFN Plastic Package QTR-0147 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax:

More information

Isolation Technology. Dr. Lynn Fuller

Isolation Technology. Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041

More information

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates

More information

Complementary Metal Oxide Semiconductor (CMOS)

Complementary Metal Oxide Semiconductor (CMOS) Technische Universität Graz Institute of Solid State Physics Complementary Metal Oxide Semiconductor (CMOS) Franssila: Chapters 26,28 Technische Universität Graz Institute of Solid State Physics Complementary

More information