FRONT END PROCESSES - CLEANING, LITHOGRAPHY, OXIDATION ION IMPLANTATION, DIFFUSION, DEPOSITION AND ETCHING

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1 Manufacturing, Cleaning, Gettering - Chapter 4 FRONT END PROCESSES - CLEANING, LITHOGRAPHY, OXIDATION ION IMPLANTATION, DIFFUSION, DEPOSITION AND ETCHING Over the next several weeks, we ll study front end processes individually. Reference - ITRS Roadmap for Front End Processes (class website).

2 SEMICONDUCTOR MANUFACTURING - CLEAN ROOMS, WAFER CLEANING AND GETTERING- Chapter 4 Modern IC factories employ a three tiered approach to controlling unwanted impurities:. clean factories 2. wafer cleaning 3. gettering Year of Production Technology Node (half pitch) 250 nm 80 nm 30 nm 90 nm 65 nm 45 nm 32 nm 22 nm 8 nm MPU Printed Gate Length 00 nm 70 nm 53 nm 35 nm 25 nm 8 nm 3 nm 0 nm DRAM Bits/Chip (Sampling) 256M 52M G 4G 6G 32G 64G 28G 28G MPU Transistors/Chip (x0 6 ) ,000 Critical Defect Size 25 nm 90 nm 90 nm 90 nm 90 nm 90 nm 65 nm 45 nm 45 nm Starting Wafer Particles (cm -2 ) <0.35 <0.8 <0.09 <0.09 <0.05 <0.05 Starting Wafer Total Bulk Fe (cm -3 ) 3x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 Metal Atoms on Wafer Surface 5x0 9 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 x0 0 After Cleaning (cm -2 ) Particles on Wafer Surface After Cleaning (#/wafer) 2003 ITRS Front End processes - see class website Contaminants may consist of particles, organic films (photoresist), heavy metals or alkali ions. Fe Au Particles SiO 2 or other thin films Na Cu Photoresist Interconnect Metal N, P 2 Silicon Wafer

3 Example #: MOS V TH is given by V TH = V FB + 2φ f + 2ε S qn A (2φ f ) C O + qq M C O () If t ox = 0 nm, then a 0. volt V th shift can be caused by Q M = 6.5 x 0 cm -2 (< 0.% monolayer or 0 ppm in the oxide). Example #2: MOS DRAM BIT LINE ACCESS MOS TRANSISTOR WORD LINE - CHARGE STORED ON MOS CAPACITOR Refresh time of several msec requires a generation lifetime of τ = σv th N t 00 µsec (2) This requires N t 0 2 cm -3 or 0.02 ppb (see text). 3

4 0 7 Manufacturing, Cleaning, Gettering - Chapter 4 Level Contamination Reduction: Clean Factories Total Particles Per Cubic Foot ,000 0, Air quality is measured by the class of the facility Particle Size (µm) Factory environment is cleaned by: Hepa filters and recirculation for the air, Bunny suits for workers. Filtration of chemicals and gases. Manufacturing protocols. (Photo courtesy of Stanford Nanofabrication Facility.) 4

5 Level 2 Contamination Reduction: Wafer Cleaning Manufacturing, Cleaning, Gettering - Chapter 4 H 2 SO 4 /H 2 O 2 : to 4: C 0 min Strips organics especially photoresist HF/H 2 O :0 to :50 Room T min Strips chemical oxide DI H 2 O Rinse Room T NH 4 OH/H 2 O 2 /H 2 O ::5 to 0.05::5 SC C 0 min Strips organics, metals and particles DI H 2 O Rinse HCl/H 2 O 2 /H 2 O ::6 SC-2 DI H 2 O Rinse Room T C 0 min Room T Strips alkali ions and metals RCA clean is standard process used to remove organics, heavy metals and alkali ions. Ultrasonic agitation is used to dislodge particles. 5

6 Level 3 Contamination Reduction: Gettering 6 Manufacturing, Cleaning, Gettering - Chapter 4 Gettering is used to remove metal ions and alkali ions from device active regions. Period I A H.008 II A 3 Li 4 Be Na 2 Mg K 20 Ca Rb 38 Sr Cs Ba Fr Ra Noble Gases Alkali Ions 2 He III A IV A V A VI A VII A Deep Level Impurites in Silicon B C N O F Ne VIII Al Si P S Cl Ar III B IV B V B VI B VII B I B II B Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Ac Unp Unh Uns Shallow Acceptors Elemental Semiconductors For the alkali ions, gettering generally uses dielectric layers on the topside (PSG or barrier Si 3 N 4 layers). For metal ions, gettering generally uses traps on the wafer backside or in the wafer bulk. Backside = extrinsic gettering. Bulk = intrinsic gettering. Shallow Donors

7 PSG Layer Devices in near surface region Denuded Zone or Epi Layer 0-20 µm T ( C) Cu Au I Fe Intrinsic Gettering Region µ m Diffusivity (cm 2 sec - ) Si I Diffusivity As B, P Au S Cr Pt Ti Interstitial Diffusers 0-8 Dopants 0-20 Backside Gettering Region /T (Kelvin) Heavy metal gettering relies on: Metals diffusing very rapidly in silicon. Metals segregating to trap sites. 7

8 Temperature C Outdiffusion Nucleation Precipitation Stacking Fault O I OI V SiO2 I O I O I O I 500 [O I ] Time SiO 2 O I Diffusion (See Chapter 3 class notes) Trap sites can be created by SiO 2 precipitates (intrinsic gettering), or by backside damage (extrinsic gettering). SiO 2 precipitates (white dots) in bulk of wafer. In intrinsic gettering, CZ silicon is used and SiO 2 precipitates are formed in the wafer bulk through temperature cycling at the start of the process. 8

9 Modeling Particle Contamination and Yield Manufacturing, Cleaning, Gettering - Chapter 4 Particle Density µm Particle Diameter Probability of Particle Causing Yield Loss 75% of yield loss in modern VLSI fabs is due to particle contamination. Yield models depend on information about the distribution of particles. Particles on the order of µm are the most troublesome: larger particles precipitate easily smaller ones coagulate into larger particles Yields are described by Poisson statistics in the simplest case. Y = exp A C D O (3) where A C is the critical area and D O the defect density. This model assumes independent randomly distributed defects and often underpredicts yields. 9

10 Use of negative binomial statistics eliminates these assumptions and is more accurate. Y = + A C D C (4) O C where C is a measure of the particle spatial distribution (clustering factor). 0. Negative Binomial (C = 2) Chip Yeld 0.0 Negative Binomial (C = 0) 0.00 D O = cm -2 Poisson Chip Area (cm 2 ) 0

11 D o = 0.0 cm -2 D o = 0. cm -2 Vertical lines are estimated chip sizes (from the ITRS). Chip Yield 0. Do = cm -2 Note that defect densities will need to be extremely small in the future to achieve the high yields required for economic IC manufacturing Chip Area (cm 2 ) (See particle defect densities on page 2 of these notes.)

12 Modeling Wafer Cleaning Cleaning involves removing particles, organics (photoresist) and metals from wafer surfaces. Particles are largely removed by ultrasonic agitation during cleaning. Organics like photoresists are removed in an O 2 plasma or in H 2 SO 4 /H 2 O 2 solutions. The RCA clean is used to remove metals and any remaining organics. Metal cleaning can be understood in terms of the following chemistry. Si + 2H 2 O SiO 2 + 4H + + 4e (5) M M z+ + ze (6) If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate. Generally (6) is driven to the left and (5) to the right so that SiO 2 is formed and M plates out on the wafer. Good cleaning solutions drive (6) to the right since M + is soluble and will be desorbed from the wafer surface. 2

13 Oxidant/ Reductant Standard Oxidation Potential (volts) Oxidation-Reduction Reaction Mn 2+ /Mn.05 Mn Mn e SiO 2 /Si 0.84 Si + 2H 2 O SiO 2 + 4H + + 4e Cr 3+ /Cr 0.7 Cr Cr e Ni 2+ /Ni 0.25 Ni Ni e Fe 3+ /Fe 0.7 Fe Fe e H 2 SO 4 /H 2 SO H 2 O + H 2 SO 3 H 2 SO 4 + 2H + + 2e Cu 2+ /Cu Cu Cu e O 2 /H 2 O H 2 O O 2 + 4H + + 2e Au 3+ /Au -.42 Au Au e H 2 O 2 / H 2 O H 2 O H 2 O 2 + 2H + + 2e O 3 /O O 2 + H 2 O O 3 + 2H + + 2e The strongest oxidants are at the bottom (H 2 O 2 and O 3 ). These reactions go to the left grabbing e - and forcing (6) to the right. Fundamentally the RCA clean works by using H 2 O 2 as a strong oxidant. 3

14 PSG Layer Devices in near surface region Denuded Zone or Epi Layer Intrinsic Gettering Region Backside Gettering Region Aus Aui 3 Trapping * Trapping 3 * 2 Diffusion Modeling Gettering 0-20 µm 500+ µm 4 Manufacturing, Cleaning, Gettering - Chapter 4 Gettering consists of. Making metal atoms mobile. 2. Migration of these atoms to trapping sites. 3. Trapping of atoms. Step generally happens by kicking out the substitutional atom into an interstitial site. One possible reaction is: Au S + I Au i Step 2 usually happens easily once the metal is interstitial since most metals diffuse rapidly in this form. Step 3 happens because heavy metals segregate preferentially to damaged regions or to N + regions or pair with effective getters like P (AuP pairs). (See text.) In intrinsic gettering, the metal atoms segregate to dislocations around SiO 2 precipitates.

15 Summary of Key Ideas Manufacturing, Cleaning, Gettering - Chapter 4 A three-tiered approach is used to minimize contamination in wafer processing. Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing. The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues. Level control - clean factories through air filtration and highly purified chemicals and gases. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces. Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices. The bottom line is chip yield. Since "bad" die are manufactured alongside "good" die, increasing yield leads to better profitability in manufacturing chips. 5