Advanced Lithography Updates and Challenges for Metrology and Inspection

Transcription

1 Advanced Lithography Updates and Challenges for Metrology and Inspection Center for Semiconductor Research & Development Advanced Lithography Process Technology Dept. Tatsuhiko Higashiki

2 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 2

3 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 3

4 Rapid Increase of Information Volume Demand All information that is created, captured, replicated and/or consumed by all human on the planet. 1ZB=1,000,000,000,000,000,000,000=10^21B Pressed by IDC on Jan.24, 2013 All information is not fully stored, but partially stored. Need for larger-capacity memory in the future. 4

5 3D Roadmap of the Memory hp3xnm hp2xnm hp1xnm hp0xnm FG FG FG FG CG STI FG FG FG CG STI FG CG FG FG STI CP(Cross Point), etc BiCS 5

6 More than Moore Lithography Challenges ArF im NA>1~1.35 Light Source EUVL NA0.32 >0.4x? ArF im SADP More Moore hp56nm hp43nm hp32nm hp2xnm hp1xnm hp0xnm Tool Defect ML2 NIL Resist, Mask, Inspection, etc Cost EUVL+SADP EUVL+DSA ArF imsaqp/saop? Arf im SAQP+DSA NIL+DSA Performance & Economics ML2+DSA SADP : self-aligned double patterning SAQP : self-aligned quadruple patterning SAOP : self-aligned octuplet patterning 6

7 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 7

8 More than Moore Lithography Challenges ArF im NA>1~1.35 Light Source EUVL NA0.32 >0.4x? ArF im SADP More Moore hp56nm hp43nm hp32nm hp2xnm hp1xnm hp0xnm Tool Defect ML2 NIL Resist, Mask, Inspection, etc Cost EUVL+SADP EUVL+DSA ArF imsaqp/saop? Arf im SAQP+DSA NIL+DSA Performance & Economics ML2+DSA SADP : self-aligned double patterning SAQP : self-aligned quadruple patterning SAOP : self-aligned octuplet patterning 8

9 EUVL and SADP Complementally dteos 加工後 hp14nm Exposure was Realized by EUVL + SADP EUVL Resist 28nm Spacer Film 14nm Si ウェハ hp28nm Spacer hp14nm Y. Watanabe et al, Photomask Japan 2010(April) 9

10 EUV Collaboration Device & design Si Process Lithography Pattern Layout Tech. (OPC/DFM) Specification Design for Tools Mask process Resist process Advanced EUVL Mask Quality Mask Inspections Resist Quality High NA Exposure Suppliers Exposure Tool EDA Resist Material Mask Metrology and Inspection 10

11 EUV Source Roadmap HVM I HVM II HVM I 10 sources in operation 5 installed at Fabs 5 for development at Cymer / ASML HVM II 1 st source delivered Four in build EUV Source Power Roadmap Source Model HVM I HVM II HVM II HVM II Average Laser Power (kw) In-band CE (%) Clean EUV Power (W)

12 Current Situation of EUVL Light Source Let there be light and there was light "Fiat lux!" Et facta est lux. 12

13 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 13

14 More than Moore Lithography Challenges ArF im NA>1~1.35 Light Source EUVL NA0.32 >0.4x? ArF im SADP More Moore hp56nm hp43nm hp32nm hp2xnm hp1xnm hp0xnm Tool Defect ML2 NIL Resist, Mask, Inspection, etc Cost EUVL+SADP EUVL+DSA ArF imsaqp/saop? Arf im SAQP+DSA NIL+DSA Performance & Economics ML2+DSA SADP : self-aligned double patterning SAQP : self-aligned quadruple patterning SAOP : self-aligned octuplet patterning 14

15 MII s Nano-Lithography Solution Jet and Flash Imprint Lithography (J-FIL) 6025 photomask substrate Mask Step 1: Dispense drops Step 2: Lower imprint mask and fill pattern Planarization layer Substrate Mask Planarization layer Substrate Major Advantages Lower cost of ownership - No laser, no track, no lenses, no vacuum No resolution limit by optical projection system Step 3: Polymerize fluid with UV exposure Step 4: Separate mask from substrate Planarization layer Substrate Mask Planarization layer Substrate Step & Repeat or whole wafer imprinting 15

16 Template Wafer Resolution of NIL Printing Template Wafer hp16nm hp24nm Spot Beam VSB 1Month/Shot 1day/Shot Ref. T.Higashiki, ,SPIE

17 CDU Update of MII Tool Imprinted-shots Measured-Metric (12 sites/shot x 20 shots/wafer) CDU(on wafer) 0.5 nm(3σ) 17

18 Mix and Match Overlay X Y Raw Mean Raw 3sigma Mean + 3sigma Achieving less than 10nm 3sigma Mix and Match overlay Ref. T.Higashiki, ,SPIE

19 Counterme asure Example of Image Phenomenon Classification of Nanoimprint Defects 1.Non-fill 2.Template 3.Plug Defect Defect Defect Filling issue by remaining bubble Printed template defect Separation issue, pattern is torn off Template Improvement of the filling process Imprinted Pattern Improvement of template fabrication process Improvement of separation process and materials 19

20 Electrical Test for Overall Evaluation Test chip design Open Test snake pattern Short Test comb pattern 20

21 Yield Improving Imprint Electrical Yield Electrical Defect Testing: Yield vs. Line Length 100% 80% J-FIL 60% 40% 26nm HP 20% 0% Line Length (mm) Steady progress in electrical yield of imprint process. Results are encouraging and improving with mask replica defect improvements

22 Current Status of NIL Attribute Target Status Template Master CDU < 1.0nm 1.2nm Image Placement < 3nm(3σ) 2.5nm(3σ) Master Defectivity < 0.1/cm2 0-1/cm2 Replica Defectivity < 1/cm2 ~5/cm2 Imprint LER < 2nm 2nm CDU on Wafer <1.0nm 0.5nm Overlay Accuracy < 8nm 10nm Defectivity (Short Wafer Runs) < 0.1/cm2 ~2/cm2 Defectivity (Long Wafer Runs) < 1/cm2 50/cm2 Throughput >20 wph 10 wph 22

23 NIL Single Exposure by Mask Technology Revolution SADP Mask (Template) EUVL single NIL single Litho. Exposed Slimming Film depo. etching Requires 20nm hp and beyond High Resolution EB Writer and Resist New Etcher and Repairing New M&I etching Processed 23

24 Rinse Suction Developing Solution Suction Rinse EB writer : EBM8000 (NuFlare) New Infrastructure for NIL Template Scanning-type Developer : PGSD Proximity-Gap-Suction-Development System (Tokyo Electron) Scan product/ebm.html Slit and scan type development Narrow gap Suction slits for removing dissolution products Mask Dry Etching Equipment : ARES TM Mask Stage PGSD Nozzle (Shibaura Mechatronics) Scan Gap Sensor Special Structure for NIL template Developing Area Cross-sectional view Gap Mask Extreme high uniformity of developing solution supply Nearly zero loading effect caused by dissolution products 24

25 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 25

26 More than Moore Lithography Challenges ArF im NA>1~1.35 Light Source EUVL NA0.32 >0.4x? ArF im SADP More Moore hp56nm hp43nm hp32nm hp2xnm hp1xnm hp0xnm Tool Defect ML2 NIL Resist, Mask, Inspection, etc Cost EUVL+SADP EUVL+DSA ArF imsaqp/saop? Arf im SAQP+DSA NIL+DSA Performance & Economics ML2+DSA SADP : self-aligned double patterning SAQP : self-aligned quadruple patterning SAOP : self-aligned octuplet patterning 26

27 DSA(Directed Self Assembly) Change in Size Molecular Weight B polymer Spherical Cylindrical Bicontinuos Lamella A polymer Composition Change in Structure Hydrophilic Hydrophobic Chemical bond DSA Molecule Micro-Phase Separated Structures of Block-copolymer K. Asakawa, T. Hiraoka, Jpn. J. Appl. Phys. vol.41, 6112 (2002). 27

28 DSA for Dense Pattern BCP: block co-polymer Under layer with guide pattern Hydrophobic Acrylic styrene Coating Heating and phase separation BCP aligns with guide pattern 28

29 Grapho-Epitaxy & Chemo-Epitaxy Segalmann et al., Adv.Mater. 3,1152(2001) Nato et al., IEEE Trans. Magn.38,1949(2002) Chen et al.,appl.phys.lett.81,3657(2002) Chen et al.,adv.mater. 20,3155(2008) Rulz et al., Science, 321,936(2008) Tada, Macromol.41,9267(2008) 29

30 DSA for Contact Hole Process Flow of DSA Lithography BCP Coat Annealing BC P Hydrophilic Hydrophobic Development Guide DSA 100 nm 100 nm 100 nm 30

31 Guide Hole vs. DSA Hole Guide hole DSA hole Ave. CD 72.1nm Ave. CD 28.5nm 3sigma 7.6nm 3sigma 1.3nm Ref.Y.Seino, SPIE Advanced Lithography

32 Hole Open Yield n=1 93.3% 77.8% 91.1% 82.2% 77.8% 75.6% 100% 100% 100% 100% 100% 97.8% 88.9% 88.9% 80.0% 93.3% 97.8% 100% 100% 100% 100% 100% 100% 95.6% 91.1% 97.8% 100% 100% 100% 100% 100% 97.8% 100% 97.8% 71.1% 93.3% 100% 100% 100% 100% 100% 100% 100% 100% 100% 86.7% 95.6% 100% 100% 100% 100% 100% 100% 100% 100% 100% 71.1% 62.2% 88.9% 97.8% 100% 100% 100% 100% 100% 100% 95.6% 53.3% 57.8% 100% 100% 100% 100% 100% 100% 100% 75.6% 100%: 0hole 95.6% 100% 100% 97.8% 86.7% 96-99%: 1-2hole 89-95%: 3-5hole n= %: 6-13hole 95.6% 91.1% 77.8% 75.6% 84.4% <70%: >14hole 73.3% 97.8% 97.8% 100% 100% 100% 100% 93.3% 100% 77.8% 95.6% 100% 100% 100% 100% 100% 100% 100% 100% 84.4% 100% 100% 100% 100% 100% 100% 100% 100% 100% 68.9% 95.6% 100% 100% 100% 100% 100% 100% 100% 100% 100% 75.6% 86.7% 100% 100% 100% 100% 100% 100% 100% 100% 100% 86.7% 62.2% 100% 100% 100% 97.8% 100% 100% 97.8% 100% 100% 86.7% 57.8% 100% 100% 100% 100% 100% 100% 100% 80.0% 84.4% 95.6% 100% 100% 93.3% 70+-5nm: optimized Circle Guide hole CD >80nm: too large Ellipse % yield on 300mm wafer center! Ref.Y.Seino, SPIE Advanced Lithography

33 DSA OPC/DfM/APC Flow OPC EDA Tool DfM Model Condition (material/process) APC Layout Guide Data OPC Litho Simulation GDS DSA Simulation HotSpot result Judge Wafer Process FeedBack EDA Tool FeedForward 33

34 MINDMAP for Engineering Challenges of DSA Computational Lithography Guide Pattern Hole/ L&S Grapho/Chemo DFM/ DR 3D Etching Sim for DSA Etg Model TCAD System HW acceleration FPGA/ GPU Empirical Model OPC/DFM Tradeoff TAT/ accuracy Verification Compare to wafer v c Microphase separation : msec~sec order DSA Simulation Molecular design Microphase separation to design M&I : how? /what? Spec? Big Difference Exists!! v c Issues Prediction accuracy Sim TAT Verification Sim time step MD : nsec Coarse Graining : 100 nsec SCF : usec? more approx. model: Target 1min /10um 2 Root Causes Current status 5nm 5hr Model inadequateness MD/DPD/SCF Parameter uncertainty Solution R&D Collaboration with Univ/Institution,, about Model innovation Measurement, Computer science 34

35 Prediction Accuracy DSA Simulation Model Shroedinger's Equation etc Rigorous Model Impractical model (<0.25nm) Target (5nm) TAT (? years/10μm2) SCF DPD TAT (5h/10μm2) TAT (1m/10μm2) speed Model Self Consistent mean Field Dissipative Particle Dynamics methodology Based on statistical field theory Challenge Modeling of thermal fluctuations Based on Newton's motion equation Difficult to fit to a measured data 35

36 Example of DPD Simulation Top-down PS-b-PMMA Top Sidewall Bottom X-section 36

37 Metrology for DSA 3D Profile Tool TEM XSEM AFM CD-SAXS OCD Method Imaging tool Diffraction tool (image is derived from computation) Application Resolution Resolution Nondestructive Non-destructive Frequency analysis Simple model Non-destructive Monitor internal structure High throughput Concerns Destructive Sample damage Destructive Sample damage Only surface topography Resolution Only surface topography Target size Model complexity TEM, XSEM and SAXS are required for DSA material development. OCD is effective for process window analysis and SPC/APC 37

38 Challenges for DSA Lithography High performance DSA material Resolution LWR/LER Etching Long term stability Robust material and tool for environmental control such as surface energy stability, temperature, humidity, pressure and PH, etc. Defectivity, CD and overlay accuracy Development of molecular dynamics based DSA simulator More accurate simulation model BCP and related molecular design Microphase separation (2D/3D) DSA and guide patterning (litho/wet/dry) TAT vs accuracy trade-off DSA OPC/DFM technology Design rule verification Metrology & Inspection Metrology for 3D profile Inspection technology for 1xnmhp and beyond needs to overcome t-put vs accuracy/sensitivity trade-off. 38

39 Half pitch [nm] Key Challenges for Shrinking 40 Immersion SADP DRAM metal MPU metal Flash gate SAQP/SAOP?/EUVL /NIL/+DSA/ Year of production? Metrology & Inspection technologies should be prepared for NGL? 39

40 Contents Device Roadmap and Lithography Extendibility toward 1x nm hp and beyond with New Lithography EUVL NIL DSA Conclusion 40

41 Conclusion EUVL We are waiting EUVL for HV production. Light source performance is a significant concern. NIL NIL performance has been improving as alternative lithography for next generation devises to reduce process cost as well as pattern size. DSA DSA will be a complementary technology for all other lithography Next Challenges Single exposure NIL will be enabled by mask(template) technology revolution. Next generation lithography will depend on innovation of infrastructure technologies such as OPC, DFM, M&I, etching and cleaning. 41

42 2013/6/13 42