Robust Systems for Scaled CMOS and Beyond

Transcription

1 Robust Systems for Scaled CMOS and Beyond Subhasish Mitra Robust Systems Group Department of EE & Department of CS Stanford University Acknowledgment: Students & Collaborators

2 Robust System Design Perform correctly despite complexity & disturbances Complexity: detect & fix design bugs CMOS reliability limits: tolerate errors Beyond silicon-cmos: imperfection-immune logic 2

3 What s New? Existing approaches: inadequate, expensive Traditional Thinking New approach Design bugs Pre-silicon Post-silicon Reliability failures Avoid Tolerate at low cost Beyond silicon-cmos Material processing Imperfection-immune design 3

4 Outline Introduction CMOS reliability limits: tolerate errors Beyond silicon-cmos: imperfection-immune logic Conclusion 4

5 Technology Reliability Challenges System soft error rates increasing Fatal flip-flop errors Comb. logic Flipflop SRAM (no ECC) Soft error rates Early-life failures (ELF) Burn-in: difficult, expensive Circuit aging & variations Worst-case guardbands expensive 5

6 Low-Cost Resilience Circuit Failure Prediction New failure signature ultra low-cost Failure rate Burn-in difficult I ddq ineffective Soft Error Resilience BISER + LEAP: Errors reduced: 2,000X Circuit aging Guardbands expensive Early-life failures (ELF) Lifetime Wearout Time Software-orchestrated global optimization a MUST 6

7 BISER: Built-In Soft Error Resilience IN Combinational logic Latch D Q C A Weak keeper OUT D Q Clock C B C-element Redundant Latch (Scan Test & Debug reuse) 45nm: up to 1,000X fewer errors vs. D-flip-flop 7

8 Single Error Assumption Inadequate Single event multiple upsets increasing LEAP: Layout by Error Aware transistor Positioning 2,000X fewer errors vs. D-flip-flop 8

9 Optimized Resilience Essential Select application-critical Chip-level error rate 0.1 flip-flops 20% Optimize for cross-layer resilience Power cost % % flip-flops critical 0% % critical flip-flops protected with logic parity, BISER for rest 9

10 Low-Cost Resilience Circuit Failure Prediction New failure signature ultra low-cost Failure rate Burn-in difficult I ddq ineffective Soft Error Resilience BISER + LEAP: Errors reduced: 2,000X Circuit aging Guardbands expensive Early-life failures (ELF) Lifetime Wearout Time Software-orchestrated global optimization a MUST 10

11 New Gate-Oxide ELF Signature Delay fluctuations over time Before functional failure Demonstrated: 45, 32nm 28, 22, 15nm in progress Stress time ELF Delay fluctuations Functional Failure Enables On-line failure prediction 11

12 On-line Failure Prediction Failure Prediction Before errors appear Error Detection After errors appear + No corruption Corrupt data & states + Low cost High cost + Self-diagnostics Limited diagnostics How? On-line self-test and diagnostics 12

13 On-Line Self-Test and Diagnostics Task 1 Task 2 Task N Task N+1 Task N+2 Task M CASP On-line self-test & diagnostics OpenSPARC T2 SoC High on-line test coverage No visible system downtime Uncore very important 1% power, 1% area, 3% performance impact Ultra low-cost 13

14 Outline Introduction CMOS reliability limits: tolerate errors Beyond silicon-cmos: imperfection-immune logic Conclusion 14

15 Carbon Nanotube FET (CNFET) D Carbon Nanotube (CNT) Diameter (D) : nm S. Iijima 15

16 Ideal CNFET Inverter P+ doped Semiconducting CNTs Vdd Lithographic pitch Input Gates Output 4nm Gnd N+ doped Semiconducting CNTs 16

17 CNFETs: BIG Promise, BUT Major barriers for a decade Mis-positioned CNTs Metallic CNTs Processing alone inadequate Imperfection-immune design essential Collaborator: Prof. H.-S.P. Wong, Stanford 17

18 Mis-positioned CNTs: Incorrect Logic Vdd A C B D Wanted: A C + B D Got: A C + B D + A D A Out C B Gnd D Wanted: (A+C) (B+D) Got : B+D 18

19 Mis-positioned-CNT-Immune NAND 1. Grow CNTs 19

20 Mis-positioned-CNT-Immune NAND 1. Grow CNTs 2. Extended gate & contacts A Vdd B Out A CRUCIAL B Gnd 20

21 Mis-positioned-CNT-Immune NAND 1. Grow CNTs 2. Extended gate & contacts 3. Etch gate & CNTs 4. Dope P & N regions A Out A Vdd B B Gnd 21

22 Mis-positioned-CNT-Immune NAND 1. Grow CNTs 2. Extended gate & contacts 3. Etch gate & CNTs 4. Dope P & N regions A Out A Vdd B Etched region ESSENTIAL B Gnd 22

23 Mis-positioned-CNT-Immune NAND 1. Grow CNTs 2. Extended gate & contacts 3. Etch gate & CNTs 4. Dope P & N regions Graph algorithms All possible functions VLSI Processing & design A Out A B Vdd B Etched region ESSENTIAL Gnd 23

24 VMR: VLSI Metallic CNT Removal Metallic-CNT-immune design Sufficient: all possible logic designs VLSI processing & design 24

25 First Wafer-Scale Aligned CNT Growth Quartz wafer with catalyst Aligned CNT growth Quartz wafer 99.5% CNTs aligned Before transfer Quartz substrate After transfer SiO 2 /Si substrate 2 µm 2 µm 25

26 First Experimental Demonstrations Imperfection-immune circuits Arithmetic & storage VLSI Integration Wafer-scale & monolithic 3D Adder sum Conventional via, NOT TSV D-latch D-latch Multi-layer CNFET circuits 26

27 CNFET Variations Significant Energy penalty Very high Naïve transistor upsizing Metallic CNT induced Grown CNT density Others CNFET I on variations 0% No design change Low (0%) Unique layouts + Co-optimized processing Yield High (99%+) 27

28 Outline Introduction CMOS reliability limits: tolerate errors Beyond silicon-cmos: imperfection-immune logic Conclusion 28

29 Thanks to my Research Group 29

30 Thanks to our Sponsors Photo credits: Burn-in & test socket workshop, H. Dai, NEC, opensparc.net, Stanford 30

31 Concluding Remarks Derive failure signatures Utilize failure signatures Validate failure signatures Enable Nanotechnology Revolutions & A TRULY Better Tomorrow 31