Complementary Metal Oxide Semiconductor (CMOS)

Transcription

1 Technische Universität Graz Institute of Solid State Physics Complementary Metal Oxide Semiconductor (CMOS) Franssila: Chapters 26,28

2 Technische Universität Graz Institute of Solid State Physics Complementary Metal Oxide Semiconductor (CMOS) The dominant technology for microprocessors Low power dissipation through the use of n-type and p-type MOSFETs

3 CMOS inverter Dissipates little power except when it is switching E QV CV dd 2 dd

4 CMOS inverter in out Vdd p+ n+ n+ p+ p+ n p n+ inverter

5 CMOS inverter in out Vdd p+ n+ n+ p+ p+ n p n+

6 Gate delay Gate delay is limited by C gate V dd /I. Ring oscillator

7 Well formation Mask oxide Lithography Etching oxide Resist strip and cleaning Dopant predeposition (for instance cm 40keV) Drive-in (500 min C) Oxide etching p n

8 Shallow Trench Isolation (STI) Pad oxide (thermal) Mask nitride (LPCVD) Lithography Etching nitride/oxide/silicon Resist strip and cleaning Liner oxide (thermal) CVD oxide deposition CMP planarization of the oxide Nitride etching Oxide etching

9 Shallow Trench Isolation (STI)

10 Self-aligned fabrication p-si 100 wafer

11 Dry oxidation SiO 2 gate oxide p-si

12 photoresist polysilicon CVD: SiH 580 to 650 C TiN (CVD) μ cm Conductive diffusion barrier SiO 2 p-si

13 Implant polysilicon gate Expose resist Develop Etch poly and TiN Strip resist Implant source and drain TiN p-si SiO 2

14 Self-aligned fabrication polysilicon gate n+ n+ p-si

15 Spacer PECVD SiN x SiN x polysilicon gate n+ n+ p-si

16 Spacer Etch back to leave only sidewalls SiN x polysilicon gate n+ n+ p-si

17 Implant polysilicon gate n+ n+ p-si

18 Salicide (Self-aligned silicide) Transition metal (Ti, Co,W) is deposited (CVD). During a high temperature step is reacts to a silicide (TiSi 2 ). Not silicide is formed on nitride or oxide. polysilicon gate TiSi 2 (metal) n+ n+ p-si

19 CMOS Fransila

20 Gate dielectric Thinner than 1 nm: electrons tunnel Large dielectric constant desirable r (SiO 2 ) ~ 4 r (Si 3 N 4 ) ~ 7

21 The heat dissipation problem Microprocessors are hot ~ 100 C Hotter operation will cause dopants to diffuse When more transistors are put on a chip they must dissipate less power. Power per transistor decreases like L 2.

22 Constant E-field Scaling Gate length L, transistor width Z, oxide thickness t ox are scaled down. V ds, V gs, and V T are reduced to keep the electric field constant. Power density remains constant. L ~ 45 t ox : "Days of happy scaling"

23 Constant E-field scaling Z ox I V V 2L t 2 sat n G T ox L sl, Z sz, t st, V sv ox ox th th I sat si sat I sat gets smaller di Z g V V D ox m n G T dvg L tox Transconductance stays the same. Power per transistor decreases like L 2. Power per unit area remains constant. Maximum operating frequency remains constant.

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25 Equivalent oxide thickness (EOT) Si0 2 EOT t t high-k Si0 2 Scaling can continue using oxides too thick to tunnel if they have a higher dielectric constant.

26 High-k dielectrics

27 Subthreshold current For V G <V T the transistor should switch off but there is a diffusion current. The current is not really off until ~ 0.5 V below the threshold voltage. Weak inversion I D evg VT exp kt B Subthreshold swing: mv/decade

28 Short channel effects SOI: silicon on insulator

29 Smart Cut

30 Smart Cut STEM images of FZ-silicon implanted with 400 kev protons at a dose of cm -2.

31 TEM image of a 3 nm Si cap/ 15 nm SiGe 50% /10 nm strained SOI structure grown at CEA-Leti and used for p-sige MOSFET fabrication. strained%20silicon/04_biaxially%20strained%20si_sige_%28s%29soi%20heterostructure/_node.html

32 Dual stress liners Tensile silicon nitride film over the NMOS and a compressive silicon nitride film over the PMOS improves the mobility.

33 CMOS SOI Fransila

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37 Contact holes Tungsten CVD using the WF 6. Exceptionally good conformality. Adhesion/barrier layer such as Ti/TiN (CVD). Protects Si from attack by fluorine, ensures adhesion of W to the silicon dioxide. Marks the start of back end processes. The temperature cannot go higher than 450 C.

38 Back-end Metallization Cu ( = 1 cm) and Al ( = 3 cm) are used for wiring layers.

39 Multi-level Metallization Fransila

40 Copper must not diffuse into the silicon. Separate equipment is used for the back end of line.

41 Interconnect RC delay Low resistivity metal Low-k dielectrics low polarizability high porosity Smaller circuits: lower gate delay larger RC delay Fransila

42 Interconnects

43 IBM

44 Microprocessor

45 Intel Pentium 4 90 nm Intel Pentium D 65 nm Intel Core 2 Duo 45 nm Intel Atom Z6xx Series 45 nm Intel Core 2 Celeron 45 nm Intel Core i nm Intel Xeon 5600 Series 32 nm Intel Ivy bridge tri-gate 22 nm Intel Haswell FinFET 16 nm

46 SRAM Static random access memory No refresh circuitry needed.

47 Dynamic random access memory (DRAM) Read and refresh DRAM with a SRAM cell

48 DRAM 75:1 Silicon oxynitride SiO x N y dielectric

49 Flash memory Charge is stored on a floating gate nonvolatile

50 Intel Micron Flash Technologies (IMFT) Shallow Trench Isolation (STI) Control Gate (CG) Floating Gate (FG) Self-Aligned Doubled Patterning (SADP)

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52 Ferroelectric RAM FeRAM uses a Ferroelectric material like PZT to store information. Sometimes used in smart cards. nonvolatile To read, try to write a 0, if a current flows, it was a 1.

53 Ferroelectric RAM

54 Phase change memory Phase-change memory (PRAM) uses chalcogenide materials. These can be switched between a low resistance crystalline state and a high resistance amorphous state. GeSbTe is melted by a laser in rewritable DVDs and by a current in PRAM. nonvolatile

55 Phase change material Electron diffraction in a TEM of a GeSbTe alloy.