Impacts of Back Grind Damage on Si Wafer Thinning for 3D Integration

Transcription

1 Impacts of Back Grind Damage on Si Wafer Thinning for 3D Integration Tomoji Nakamura, Yoriko Mizushima, Young-suk Kim, Akira Uedono, and Takayuki Ohba Fujitsu Laboratories Ltd., University of Tsukuba Tokyo Institute of Technology

2 Outline 1. Background and motivation 2. Experimental - Thinning conditions and characterization 3. Subsurface damaged layers in thinned wafers - Impacts of coarse grinding thickness - Remaining damages after fine grinding - Subsurface structure after CMP 4. Impact of ultra-thinning on device characteristics 2

3 3D Integrations for More than Moore SiP 3D-IC TSV DRAM Flash memory DRAM Flash memory DRAM Flash memory DRAM Flash memory Memory controller DRAM Power Photonic engine CMOS logic DRAM Memory controller Controller Silicon Substrate with TSV interconnects and Si Waveguides Photonic/electronic Circuit Board Source: 2011 ITRS Exec. Summary Fig. 5 Moore s Law and More 3 3

4 Bumpless 3D-IC Structure with Ultra-thinned wafers Eliminating Bump Small Form Factor 10-mm Thinning Low aspect ratio for TSV processing Wiring length shortening RC delay mitigation Low power consumption T. Ohba: Microelectron. Eng

5 Wafer thickness (µm) Wafer Thinning by Grinding & Polishing Damaged layer (nm) Thinning Process Back grind Stress relief Mechanical Strength Back grind Coarse Fine CMP 0 Process time Back grind Stress relief Coarse / Fine CMP Grinder wheel CMP head Si wafer slurry Stress relief Fracture strength (GPa) Gettering ability: weaker Optimizing coarse- and fine-grinding, and CMP conditions are crucial. 5

6 Motivation Analyzing subsurface damaged layers caused by thinning; 1. Damages and defects dependence on removed Si thicknesses 2. Impacts of grinding & polishing conditions on the damages 3. Impacts of ultra-thinning on device characteristics 4. Features of the damaged layer; thickness, microstructure, defects, stress etc 6

7 Experimental: Sample Preparations Thinning conditions Grinding thickness (µm) Sample Wafer Coarse Fine Stress No. thickness grind grind relief Grinding & Polishing apparatus: DGP8761 Coarse grind Particle size #320 Fine grind #2000 Impacts of coarsegrind thickness on remaining damages Remaining damages after fine-grinding 7 7

8 Experimental: Damage Analyses Laser microscopy Surface roughness: Ra (due to grinding marks) μ-raman scattering analysis: 458 nm Ar + laser, 0.7 μmf Subsurface structural change: crystalline & amorphous peaks Elastic strains & stresses: TO phonon peak shifts Cross-sectional TEM Micro structures & defects in the subsurface: bright field images under the (110) zone axis Positron annihilation analysis Vacancy-type defects: S parameters in Doppler broadening spectra 8

9 Ra (µm) Grinding Thickness Dependence of Ra Coarse-Center Coarse-Edge Fine-Center Fine-Edge CMP-Center CMP-Edge Grinding thickness (µm) Y. Mizushima: JJAP2014 Ra; Surface roughness depends on the grinding abrasive condition Removed thickness dependence is smaller than in-plane variations 9

10 Raman intensity (arb. units) Raman Spectra from Coarse-grind Subsurface 10 5 TO Coarse grind: 125 mm TA 2LA 2LO 2TO TA LA LO # # # mixed crystalline amorphous T. Nakamura: 3DIC2013 Raman shift (cm -1 ) Three types of spectra: amorphous, crystalline, and mixed structure 10 10

11 X-TEM Observation of Coarse-grind Damage 1.0 mm Poly Si Coarse grind: 125 mm Stacking faults Amorphous Si Plane-view image 10 mm 200nm Dislocations T. Nakamura: 3DIC

12 Impacts of Coarse-grind Thickness Sample No. Thinning conditions Wafer thickness Grinding thickness (µm) Coarse grind Fine grind Stress relief Grinding & Polishing apparatus: DGP8761 Coarse grind Fine grin d Particle size #320 #

13 Subsurface Damage after Fine Grinding T. Nakamura: 3DIC2013 Coarse grind: 75 mm Fine grind: 50 mm Dark contrast layer 100 ~ 200 nm thick Interference fringes Distorted dislocation contrasts Almost original crystalline structure Coarse : 425 mm Fine : 50 mm 1.0 mm Amorphous Si SAD Amorphous Si 1.0 mm 13

14 Raman intensity (arb. units) Raman Spectra and Imaging of Subsurface TO mm (a) 140 cm -1 (b) 523 cm -1 amorphous (a.u.) (a.u.) 140 cm cm -1 Coarse grind: 75 mm Fine grind: 50 mm T. Nakamura: 3DIC Raman shift (cm -1 ) Amorphous and crystalline Si areas remain along grinding marks. 14

15 TO phonon peak shift: ω (cm -1 ) Ground Thickness Dependence of Peak Shift Ar + Laser: 458 nm Beam size: 0.7 mm Ground thickness No. 2 3 Coarse Fine ω was obtained from randomly chosen ten points Higher peak shifts are ascribed to compressive lattice strains Coarse-grind thickness dependences are smaller than the large variations Y. Mizushima: JJAP

16 Peak shift ω (cm -1 ) Raman Peak Distribution: (110) Cross-section backside FWHM (cm -1 ) Coarse: 75 μm / Fine: 50 μm Coarse: 425 μm / Fine: 50 μ m Peak shift due t o elastic strain 50 MPa Si Coarse: 75 μm / Fine: 50 μm Coarse: 425 μm / Fine: 50 μ m Peak broadening due to damage Ref. Si (011) Position (μm) Position (μm) Plastic-deformed damaged layer is localized within less than1 μm depth Damaged layer influences inside compressive strains ranging up to 15μm depth T. Nakamura: 3DIC

17 Raman Peak Distribution after CMP Peak shift ω (cm -1 ) 0.3 Coarse: 75 μm / Fine: 50 μm + CMP 1 μm + CMP 5 μm Compressive strains disappear after 1 μm CMP Position (μm) The elastic strains ranging up to about 15 μm depth are caused by plastic-deformed damaged layer ( < 1 μm thick) T. Nakamura: 3DIC

18 X-TEM Images of Backside Surface after CMP 200 nm CMP (stress relief): 1 μm Defective dark contrast layers disappear Atomically flat surface is observed after polishing only 1 μm thick T. Nakamura: 3DIC

19 Trapping of positrons by vacancy-type defects A freely diffusing e + may be localized in an open space because of the Coulomb repulsion from ion cores. E: incident positron energy : low momentum part Larger S parameter means larger size of vacancy-type defects

20 S parameter S parameter Depth Distributions of S Parameters Mean implantation depth of positrons (nm) Coarse: #675 μm Fine: 50 fit μm Coarse: #7425 μm Fine: 50 fit μm Fine: 50 #14 μm CMP: 1 fitμm Fine: 50 #16 μm CMP: 5 fitμm Coarse: 75 μm Fine: 50 μm Coarse: 425 μm Fine: 50 μm #5 #2 Fine: 50 μm #7 #3 CMP: 1 μm #14 # Positron energy (kev) Depth (nm) After fine grinding, vacancy-type defects range up to 0.1 μm depth S parameter distributions can distinguish defect density deference between 1- and 5- μm thick CMP samples. T. Nakamura: 3DIC

21 Defects induced by grinding of Si wafers The lifetime spectrum of a positron was measured at E = 2 kev and it was decomposed into two components. t 1 = 285 ± 9 ps t 2 = 490 ± 20 ps (I 2 = 11 ± 2 %) Vacancy (V or V 2 ) Vacancy cluster (V 18 ) Leipner et al., Physica B , 6 17 (2003) I 2 =20 % Fz-Si (P doped) was deformed at RT and 800 C up to 16% in an anisotro pic multi-anvil apparatus under a co nfining pressure of 5 GPa. Uedono et al., JAP 116, (2014) 460 ps 210 ps

22 Summary: Subsurface Damages 22 #320 grit grind #2000 grit grind CMP 5 μm 200 nm 2-3 nm 1. Coarse grinding damages cause the roughness and defects of less than 5 μm depth. 2. After fine grinding plastic-deformed damaged layer with less than 200 nm thick still remains. 3. CMP process enables to remove residual damages such as structural defects and lattice strains except vacancy-type defects.

23 Ultra-Thinning of 300mm Wafer with 2 Gb DRAM Light Transparence on 4mm thick DRAM Wafer Cross-section of 4mm DRAM Wafer Device Layer = 7mm thinned Si = 4mm Extremely thinned down wafer from 775 to 4-µm, that is about 0.5 % of its original thickness. Y. S. Kim: VLSI

24 Sequence of Wafer-on-a-Wafer (WOW) Process Total Si Thickness [mm] Temporary bonding & Thinning Glass handle wafer Front side 10 DRAM wafer Glass handle wafer DRAM wafer Permanent Bonding Temporary adhesive line 2 line 1 Glass handle wafer 4 De-bonding Wafer Probing Base wafer Glass handle wafer DRAM wafer Base wafer DRAM wafer Base wafer Permanent adhesive 3 line 1 line Distance from Wafer Center [mm] Si thickness [µm] Mesh size of grind wheel TTV [um] Coarse Fine #320 # Y. S. Kim: VLSI

25 Effect of Ultra-thinning on Device Characteristics Ion/Ioff Junction Leakage Ioff [A/mm] Cumulative Probability [%] Ioff [A/mm] Cumulative Probability [%] Device Node Thickness FRAM ~180nm 9mm Logic 45nm (Lg 35nm) 7mm DRAM 40nm (2Gb) 4mm FRAM Memory 35nm SRAM Device SEM Picture 9-mm Si BCB PZT 5mm ~7-mm NMOS PMOS Electrical Property 1E-5 1E-6 1E-7 1E-8 1E-9 Before thinning After thinning 1E Ion [ma/mm] NMOS 1E-5 1E-6 1E-7 1E-8 1E-9 Before thinning After thininng 1E Ion [ma/mm] PMOS Before After N+/P Before After P+/N Junction Leakage Current[A] Junction Leakage Current[A] VLSI2010 IEDM2009 VLSI

26 Acknowledgments This work was carried out at 3D development program in the WOW alliance and the WOW Research Center Corporation. ALLIANCE 26