Amorphous and Polycrystalline Thin-Film Transistors

Transcription

1 Part I Amorphous and Polycrystalline Thin-Film Transistors

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3 HYBRID AMORPHOUS AND POLYCRYSTALLINE SILICON DEVICES FOR LARGE-AREA ELECTRONICS P. Mei, J. B. Boyce, D. K. Fork, G. Anderson, J. Ho, J. Lu, Xerox Palo Alto Research Center, Palo Alto, CA M. Hack, R. Lujan, Xerox dpix, Palo Alto, CA ABSTRACT Distinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and shortchannel amorphous silicon thin film transistors have been demonstrated. INTRODUCTION Fabrication of high quality, large-area a-si films at low temperature by plasma enhanced chemical vapor deposition (PECVD) is well established and inexpensive. a-si:h material has been used for pixel switches and photo sensors in large area image arrays [1]. a- Si:H thin film transistors (TFTs) possess a low off-state current which makes them ideal pixel switches for high resolution imaging arrays. The carrier mobility of this material, however, is low. This drawback limits its application in high speed peripheral driver circuits. The development of low temperature poly-si by laser crystallization has brought attention to integration of large-area electronics with peripheral drivers. The field effect mobility of the poly-si TFT is two orders of magnitude higher than that of a-si TFTs. The high mobility makes poly-si TFTs attractive for the peripheral drive circuitry. However, poly-si TFTs have a considerably higher leakage current compared with a-si TFTs. A high leakage current through a pixel switch results in a poor dynamic range for an imaging system. In order to achieve a reasonable imaging dynamic range, the leakage current through the pixel switch has to be low enough to hold the charge on the pixel capacitor during one imaging frame time. This requirement becomes more stringent for a high resolution array, where the pixel capacitance is small. It is difficult for poly-si TFTs to meet this requirement for high resolution imaging arrays. A natural extension of a-si and poly-si technology is the combination of a-si and poly-si devices on the same substrate to improve the system reliability and to reduce the packaging cost for the large-area electronics. This goal can be approached by making a-si and poly-si TFTs on the same substrate separately or monolithically. The advantages of the monolithic fabrication are fewer processing steps and easier inter-device connections. Figure 1 shows a-si and poly-si TFTs fabricated by a monolithic process based on a modification of the a-si TFT fabrication process. The distance between the two devices is about 10 \im. Mat. Res. Soc. Symp. Proc. Vol Materials Research Society 3

4 Figure 1. Optical microscope photograph of an a-si TFT and a poly-si TFT built side by side by a monolithic fabrication process. The distance between the two devices is about lojim. Applications of the hybrid a-si and poly-si structure extend beyond the combination of a- Si and poly-si TFTs. For example, doped poly-si material has low resistivity which can be utilized for a-si TFT source and drain contacts [2]. In the conventional bottom-gate a-si:h TFT fabrication process, the channel region is defined by a self-aligned passivation island, formed by backside lithography. The source/drain contacts are formed by depositing doped a-si:h with subsequent patterning. Since it is difficult to selectively etch doped a-si over the intrinsic a-si, the top passivation island is utilized as the etch-stop to form the source/drain electrode. As a result, there are overlaps of the source/drain electrodes with the channel region, causing an additional parasitic capacitance between the gate and the source/drain electrodes. The high parasitic capacitance results in a feed-through voltage on the pixel electrode, producing image flicker and sticking in the display application. Also, the overlap introduces a variation of the parasitic capacitance among the pixels, resulting in non-uniform gray-level performance. The parasitic capacitance causes the cross talk during the readout process in the imaging application. In addition to the problem of the parasitic capacitance, the non-self-aligned stracture limits the scaling down of the channel dimension, which affects the pixel fill factor in both display and imaging applications. These problems can be solved by making a truly self-aligned a-si:h TFT with poly-si source and drain contacts. The stracture can be realized by forming self-aligned source/drain contacts with a pulsed laser doping technique. This paper describes the monolithic fabrication process for making a-si and poly-si TFTs on the same glass substrate and the laser doping process for making self-aligned a-si TFTs.

5 MONOLITHIC FABRICATION OF HYBRID a-si AND POLY-Si TFTs The monolithic fabrication process for the hybrid a-si and poly-si TFTs is based on the selective laser crystallization. Earlier work on monolithic fabrication was demonstrated on a staggered top-gate TFT structure by Sera, et al. in 1989 [3]. In general, the top-gate poly-si TFT has a higher mobility compared with the bottom-gate TFT [4]. However, the device performance of a top-gate a-si TFT is inferior to that of the bottom-gate TFTs, as described in reference 3. The attempt at making a simple modification of conventional a-si TFT technology for the hybrid device motivates the development of an inverse staggered (bottom-gate) TFT structure. An early demonstration of bottom-gate hybrid a-si and poly-si TFTs was reported by Shimizu, et al., in 1990 [5]. In their work, discrete a-si and poly-si TFTs were fabricated on the same crystalline Si wafer. A liquid crystal display with a-si pixel switches and poly-si peripheral circuits was reported by Tanaka in 1993 [6]. A challenge for the selective laser crystallization is related to the rapid hydrogen evolution from the hydrogenated a-si film. For the hybrid devices, high quality a-si films deposited by PECVD at low temperature are used in order to obtain high performance of a-si TFTs. The PECVD a-si film contains a large amount of atomic hydrogen (H), typically 7-10 at. %, which passivates Si dangling bonds and, therefore, reduces the defect density. Whereas H is essential to electrical performance of a-si devices, it causes film ablation during laser crystallization due to rapid hydrogen out-diffusion. Conventionally, a 450 C furnace anneal is performed for several hours to remove most of the H from the PECVD a-si:h films prior to laser crystallization to avoid film ablation. This anneal makes it impossible to fabricate high quality a-si:h devices due to H loss in the a-si devices at 450 C. There have been several reports on making hybrid a-si and poly-si TFTs by a selective laser crystallization process. The report by Shimizu et al. [5] describes an approach in which a- Si deposition was carried out at 450 C using disilane, resulting in a smaller amount of H (3 at. %) in the material. Because of the small hydrogen content in the starting material, the laser ablation was avoided during the selective crystallization. It is, however, detrimental for the a-si TFTs with a small amount of hydrogen. An alternative approach was reported by Tanaka et al. [6]. 25-?0- \300mJ/cm \ \ \ \ 1 a-si:h Glass Substrate "* - - Figure 2. Hydrogen outdiffusion per laser pulse as a function of the number of laser pulses. The a-si:h sample was irradiated by an excimer laser at 170 mj/cm 2, followed by laser irradiation at 300 mj/cm z mJ/cm 2 A Number of Pulses

6 In their work, the silicon film was thin (<50 nm), allowing thorough laser crystallization without hydrogen induced film ablation. A restriction in this process is a limit on the laser energy density for getting the optimized polycrystalline grain size. In our laboratory, we developed the three step laser process to gradually remove hydrogen and crystallize the film for poly-si TFTs [7]. As shown in Fig. 2, the amount of hydrogen out-diffusion can be controlled by adjusting the < " a-si:h (7% H) after 1st scan (4% H) 3ftor 3rd scan Depth (A) Figure 3. SIMS hydrogen depth profiles from an as deposited sample and samples irradiated in sequence at laser energy densities of 150, 300, and 374 mj/cm 2. Figure 4. Cross sections and planar views of samples after sequential laser processing at (a) 150 and (b) 300 mj/cm. (b)

7 increment in the laser energy density. In the three-step laser process, the first laser energy is slightly above the Si surface melting threshold. The amount of hydrogen is reduced from 7 atomic % to 4 atomic %, as shown in Fig. 3. The second laser energy density is near the meltthrough threshold, which removes the most of the hydrogen remaining in the film. The final laser scan produces poly-si films with large grains. Figure 4 shows cross-section and planar view TEM images of the films processed by the three-step process. After the first laser scan, the film is partially converted to microcrystalline Si with fine grains (Fig. 4a). The second scan at a energy density near the melt-through threshold produces columnar poly-si grains (Fig.4b). The average grain size, however, is small. The desired film crystallineaty is mainly determined by the last scan. 500 nm Figure 5. TEM planar view of poly-si films produced by the three-step laser process. The laser energy densities for the final step were (a) 425, (b) 445, (c) 465, and (d) 485 mj/cm2. Figure 5 shows the film crystallinity from samples processed by the three step laser crystallization at various laser energy densities for the last step. The grain size increases with increasing energy density up to a peak value of a few micrometers. The grain size decreases with further increases in the laser energy density. The transistor field effect mobility is conelated with the grain size. The large grain size results in a high mobility. At the optimized grain size, however, the film suffers from the damage at the interface between the Si film and the gate insulator below that results in non-uniform device performance and a significant leakage current through the gate insulator. Uniform device performance is obtained by choosing the laser energy density below the critical value. An alternative selective laser hydrogen removal process is described by Sameshima [8]. This process utilizes a laser beam with a staircase energy profile. With the staircase beam profile, the Sifilmreceives laser irradiations with gradually increasing the energy density. DEVICE PERFORMANCE OF HYBRID a-si AND POLY-Si TFTS Figure 6 describes the monolithic fabrication process for making a-si and poly-si TFTs on the same substrate. The process starts with gate electrode patterning, followed by PECVD

8 deposition of the dual dielectric of SiN and SiC>2 and a-si:h. Selective laser dehydrogenation/crystallization are then performed. The film is hydrogenated after the crystallization process to passivate the defects in the poly-si film. The source/drain contacts are made by doped a-si. The process is a modification of the conventional bottom-gate a-si fabrication. (a) (c) -N+a-Si:H Poly-Si TFT a-si:h TFT Figure 6. Fabrication process for hybrid a-si and poly-si TFTs. (a) PECVD deposition of the gate insulator and Si film; (b) Selective laser de-hydrogenation and crystallization; (c) The final device structure with source and drain contacts. The dual dielectric gate insulator is used to optimize the threshold voltage simultaneously for both a-si and poly-si TFTs. The TFT threshold voltage depends on the fixed charge in the dielectric film, the defect density and the doping level in the Si film, and the work function of the gate electrode. a-si TFTs with the SiN gate insulator shows superior performance over those with SiC>2. According to the defect pool model [9], the superior performance of a-si TFTs with a SiN gate insulator is attributed to the positive fixed charge in the nitride dielectric. The positive charges in the gate insulator result in, through equilibration reactions, lower defect densities located above the midgap of the a-si band gap. Therefore, the threshold voltage is small and positive. However, the threshold voltage of poly-si TFTs with a SiN gate insulator is negative. One of the simple approaches to obtain small and positive threshold voltages for both a-si and poly-si TFTs is to combine SiN and SiC>2 for the gate insulator. Figure 7 shows the transfer characteristics from a-si and poly-si TFTs fabricated on the same glass substrate. The gate insulator consists of a dual layer oxide and nitride dielectric. The performance of the poly-si TFT is uniform, though the mobility is lower than the maximum

9 mobility (-100 cm 2 /V sec) we are able to obtain with the monolithic fabrication process. The a- Si TFT exhibits a low leakage current. The leakage current is less than 1 fpj\im under a drain bias of 10 V, which is sufficiently low for the pixel switch. io*! * 1 _g 1 Poly-Si TFT W/L=60/15 \im H = 20cmW.s\,* ** v T =iv y*" V,=:10V * 1 10* 1 10' " " u ' ^ J / / ' / / / J J a-si TFT W/L=15/15 Jim \i =0.9 cmw.s v T - Gate Voltage (V) Figure 7 Transfer characteristics of a poly-si TFT and an a-si TFT fabricated by the selective laser de-hydrogenation and crystallization process. LASER DOPING FOR a-si TFT with POLY-Si SOURCE7DRAIN CONTACTS In general, laser doping is a process in which a laser pulse is employed to briefly melt a surface layer in a doping region. During this brief period, dopant species are introduced into the molten material. When the molten layer is solidified, the dopants are distributed and electrically activated in the layer. Laser doping experiments for material studies were conducted on 100 nm a-si films. The species for n-type doping is phosphorous. Figure 8 shows phosphorous depth profiles, measured by secondary ion mass spectrometry (SIMS) from samples doped at various laser energy densities. These data reveal that the doping level and depth are controlled by the laser melting process. The phosphorous diffusion coefficient in molten Si is about -10" 4 cm 2 /s [10], which is very fast compared with the solid phase diffusion rate (~10~ n cm 2 /s [11]). Since the temperature rise and fall in Si films during and after a pulsed laser irradiation is abrupt, effective dopant diffusion occurs primarily in the liquid phase. A higher laser doping energy results in a longer melt duration and deeper melting depth which leads to a higher doping level and deeper doping depth. Figure 9 shows the doping efficiency versus the laser doping energy density. The doping efficiency increases linearly with the energy when the laser energy exceeds the Si surface melting

10 threshold of about 200 mj/cm 2. With 300 mj/cm 2 laser doping energy density, the equivalent doping rate is about atom/em 2 per laser pulse. Since atoms/cm 2 is a typical dose required to form the TFT source/drain contacts, a few laser pulses are sufficient for making the device fabrication. Therefore, a high throughput doping process can be obtained by the laser doping technique mJ/cm 2Q0mJ/cm 250mJ/cirf 35OmJ/cirf Depth (JI m) Figure 8. SIMS data showing phosphorous depth profiles from 0.1 \im thick Si films doped by a pulsed laser at various laser energies with 100 pulses Laser Doping Energy density (mj/cm 2 ) Figure 9. Equivalent dose per laser pulse as a function of the laser doping energy density. The data were converted from SMS measurements. A self-aligned and short-channel TFT structure has been realized with the laser doping technique. Figure 10 shows the performance of a self-aligned a-si TFT with a channel length of 3\im. The device shows comparable field effect mobility compared with long channel devices, indicating that the source and drain contact resistance is low compared with the TFT channel resistance. In addition, the leakage current of the TFT is reasonably low for the pixel switch. For most applications, the pixel TFTs are operated in the linear region. The TFT contact resistance in the linear region was determined from the inverse of the output conductance as a function of the TFT channel length [12]. The contact resistance is the intersection of the device output resistance with zero channel length. Figure 11 shows a comparison of the contact resistance of the laser-processed self-aligned contacts and the conventionally doped a-si source/drain contacts. Since the self-aligned TFTs have similar channel properties and gate dielectrics as the conventional TFTs, the slopes of the straight line fit to the data from the two kind of devices are almost equal. The contact resistance, normalized to 1 Jim channel width, for the conventional contact and the laser processed contact are 16.2 and 0.76 MQ.jim respectively. The low contact resistance of the laser doped source/drain results in the high performance of the short-channel a-si TFTs. 10