Effect of Feature Dimensions/Spacing and Dielectric Thickness on CMP Process Performance

Transcription

1 Effect of Feature Dimensions/Spacing and Dielectric Thickness on CMP Process Performance Andrey Zagrebelny*, Steven Hedayati, Frederick Eisenmann, Yitzhak Gilboa, Cypress Semiconductor Inc. 1

2 Abstract Although pattern density-induced CMP process degradation is well known and documented, existing methods to characterize CMP performance are not catching up with the design rules used in sub 0.15 micron technologies. At the same time, feature dimensions and spacing (for a given pattern density) can also significantly alter local within-die uniformity affecting overall CMP process performance. In this work, features dimensions and spacing were evaluated using a mask designed with 0.1 micron design rules to reduce after-cmp residual oxide/nitride thickness for ILD and STI processes.there are three distinctive silicon dioxide-filling mechanisms that have been identified to affect subsequent CMP. The mechanisms can be identified in terms of minimum feature spacing (ILD), feature dimension (STI), pattern density, and the thickness of a dielectric deposited. The goal was to establish a model which will be used to generate design rules which will reduce the probability of CMP-related failures. 2

3 Pattern Density Dependencies Large blocks of individual structures tend to require longer polish times in comparison to isolated structures Wide ranges of pattern density across a die can cause poor within die uniformity Graph courtesy of Kathleen Perry, Applied Materials 3

4 Characteristic Post-Polish Oxide Variation measured locally with XSEM in X/Y directions Horizontal RESOX X RESOX, A Scribe line Die Edge Distance, um Local within Die post-polish oxide thickness variation leads to a un-manufacturable CMP process Y RESOX, A Vertical RESOX waffeled area Distance, um 4

5 Pattern Dependency Characterization: MIT Pattern Density Mask Set* MIT mask feature Transistor Isolation feature HDP Oxide Nitride Nitride THINBOX Silicon When features spacing are less than 1um, MIT mask does not provide an adequate characterization of local pattern density *B. Stine, et. al, IEEE Trans. on Semi. Manuf., Feb

6 Cypress CMP Characterization Structure on a Test Chip 1mm 1mm 0.25µ Metal Spacing Pattern Density Pattern Density Metal Spacing Location of CMP structure on the mask (hatched area) Linewidths, spacings, and pattern densities are more representative of actual product s Abiltity to electrically test VIA s to monitor ILD/IMD thicknesses 6

7 Oxide Deposition Profile Differences between Cypress Test Chip and MIT mask HDP oxide TEOS oxide EDO mask Nitride HDP Oxide TEOS IMD Si Metal HDP Oxide MIT mask Nitride Si Metal 7

8 Pattern Density Characterization: Design Rules and Spacing CMP τ λ min Conformal oxide filling CMP τ λ min Full conformal filling Filling void CMP τ λ min Non-conformal oxide filling 8

9 Correlation between Line Spacing and post-cmp Oxide extracted from Cypress CMP structure (continued) Metal spacing and NILD oxide thickness contribute to within die after-cmp RESOX variation There are three distinctive oxide-filling mechanisms that can affect after-cmp within die range - conformal fill, full conformal fill, and non-conformal fill. Oxide filling mechanism can be controlled by either the Metal spacing or NILD oxide thickness. Changing Metal spacing / NILD oxide thickness can effectively alter oxide pattern density for a given pattern density of Metal 9

10 Correlation between Line Spacing and post-cmp Oxide extracted from Cypress CMP structure TEOS Oxide HDP Oxide Oxide width as a function of metal width Thickness [A] 3000 Step Height 2500 Residual Oxide Line spacing[micron] Oxide CD micron Metal CD in micron 10

11 Pattern Density Considerations for CMP (ILD and STI) MIT mask has limited capability in determination of Pattern Density sensitivity at spacings less than 1 um Cypress CMP test structure provides pattern density sensitivity extraction method to address 0.1 um typical CD geometries Metal spacings controls oxide filling mechanism that affects polish process Smart dummy structures design that reduce PD range and behave like array with spacing that that equal to minimum 11