Development of a New-Generation RoHS IGBT Module Structure for Power Management

Transcription

1 Transactions of The Japan Institute of Electronics Packaging Vol. 1, No. 1, 2008 Development of a New-Generation RoHS IGBT Module Structure for Power Management Yoshitaka Nishimura*, Tatsuo Nishizawa*, Eiji Mochizuki**, Tomoaki Goto**, Yoshikazu Takahashi** and Shinobu Hashimoto*** *Fuji Electric Device Technology Co., Ltd., , Tsukama, Matsumoto, Japan **Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., , Tsukama, Matsumoto, Japan ***Nagoya Institute of Technology Showa-ku, Nagoya, Japan (Received September 3, 2008; accepted November 25, 2008) Abstract This paper describes the design considerations for a high electric power density IGBT module structure mounted with smaller, new-generation chips. We have investigated heat flow depending on the copper foil thickness of an alumina based direct-copper-bonding (DCB) substrate, junction temperature rise in relation to the chip arrangement, electromagnetic noise dominated by the cupper circuit pattern, and lead-free solder layer stress as affected by the coefficient of thermal expansion (CTE) of DCB. Low thermal resistance was obtained by using a 0.6 mm thick copper DCB substrate; consequently the CTE of the DCB increased to 16 ppm/k, which is nearly equal to that of the Cu base as a heat sink. The thick copper DCB substrate can lower the junction temperature of a small chip with a high electric power density and can improve the thermal cycling capability of the DCB substrate mounted with a lead-free solder on the Cu base. Moreover the thick copper circuit effectively reduces the electromagnetic noise generated on the DCB substrate. Thus we have successfully realized a high electric power density IGBT module structure. Keywords: IGBT Module, Thermal Management, Electromagnetic Noise, Thermal Cycling Capability, Lead Free Solder 1. Introduction Insulated gate bipolar transistor (IGBT) modules are widely used in power electronics applications such as automobiles and household appliances as well as industry[1] to realize energy savings with higher efficiency, smaller size, lower cost, higher reliability, and more environmental safety from acoustic and electromagnetic noise generation and lead usage. These various requirements will be satisfied not only by creating smaller IGBT chips with superior performance characteristics, but also by improving the module structure based on thermal, noise, and environmental management techniques. Although chip size reduction is an extremely effective way to realize smaller size and lower cost IGBT modules, the chip junction-to-case temperature rise, ΔTj-c, becomes more severe as the size decreases, as in the following equation: ΔTj-c = P IGBT Rth(j-c) (1) where P IGBT is the power dissipation of the chip and Rth(j-c) the thermal resistance from junction to case. If the chip size is decreased, the thermal resistance must be increased due to an increase in heat density, and then the junction temperature must be highly elevated even to maintain the same power dissipation as that of a large size chip. A field-stop junction structure on the back-surface, combined with a trench-gate structure on the device surface, has been shown to reduce power dissipation in smaller size chips.[2] On the other hand, an improved IGBT module structure for such a small, new-generation chip must be designed based on the following considerations: a) Reduce thermal resistance, by optimizing a directcopper-bonding (DCB) ceramic substrate with thick Cu foils. b) Reduce noise radiation below the level specified by the European standard EN ,[3, 4] by optimizing the P N current loop area on the DCB substrate. c) Change from lead-based solder to lead-free solder in 40

2 Nishimura et al.: Development of a New-Generation RoHS IGBT (2/8) order to comply with the European RoHS directive[5] while maintaining or increasing the thermal cycling capability. Thus we have experimentally investigated how the structural parameters of an IGBT module affect heat, noise, and reliability. The design considerations mentioned above and the experimental results obtained have been successfully applied to the development of a smaller, next-generation package structure which can manage an electrical power density higher than that of a conventional module. 2. Experimental Procedures 2.1 Thermal evaluation Steady-state thermal resistance analysis was carried out using FEM analysis (ADINA). Figure 1 shows the thermal analysis model. An analysis of IGBT chips energized by 80A DC was performed under the following steady state conditions: chip size of 9.25 mm, DCB ceramic size of t0.32 mm, copper circuit area size of mm, copper plate thickness of 0.25 mm and 0.6 mm, and copper base size of t3 mm. The thermal conductivity of the ceramic was changed from 18 to 170 W/m K. A heat measurement sample was produced in the same size as the FEM analysis model. Alumina (thermal conductivity: 28 W/m K) and aluminum nitride(thermal conductivity: 170 W/m K) were used for the DCB substrate. The thickness of the copper plate was 0.25 mm and 0.6 mm. Chip temperature measurements were carried out using an IR camera (AVIONICS TVS-8500). Carbon was applied to the measurement side of the sample and the rate of thermal radiation was set to be constant. Two or more chips are used in an actual IGBT module. This can be expected to affect the thermal interference among chips. We therefore investigated the effect of chip spacing on chip temperature. Figure 2 shows a threedimensional FEM analysis model. A steady-state thermal analysis on IGBT chips energized by 20A DC was performed under the conditions of: chip size of 6.4 mm 6.4 mm, DCB substrate size of 25 mm 25 mm, and copper base size of 35 mm 3 mm. Chip spacing was changed from 0.5 mm to 6 mm. 2.2 Noise evaluation Radiation noise was measured using a dipole antenna (ADVANTEST 3753B) and spectrum analyzer (ADVANTEST R3261A) at the frequency range of 30 to 230 MHz. The distance between the dipole antenna and IGBT module was 3m. 2.3 CTE measurements The coefficient of thermal expansion (CTE) of the copper circuit was measured by a laser displacement sensor (Keyence:LT-8100) at temperatures between 25 C and 300 C. 2.4 Thermal cycling test In thermal cycling tests, an IGBT module was put in a tank maintained at a constant temperature and the ambient temperature was changed from 40 C to 125 C. During thermal cycling, failure was analyzed by nondestructive observation of the solder joint with a scanning acoustic microscope (SAM) (the frequency of the ultrasonic transducer was a nominal 25 MHz ). 3. Results and Discussion 3.1 Heat dissipation design Figure 3 shows the structure and thermal conductivity of each component of the IGBT modules (Fuji Electric). The heat generated at the IGBT chips is conducted through the insulating ceramic substrate (DCB: Direct Bonding Copper) and the copper base, and dissipated by the radiation fins. Table 1 presents the characteristics of the ceramic used for the DCB substrate. The thermal conductivity of the ceramic material used as an insulating layer in the DCB substrate is 18 to 170 W/m K. Although alumina ceramic has lower thermal conductivity than aluminum nitride and silicon nitride, it is less expensive and more ductile; its CTE is closer to that of the copper base; and because temperature changes during operation cause less stress, it improves reliability. Con- Fig. 1 Thermal analysis model (single chip). Fig. 2 Thermal analysis model (multiple chips). 41

3 Transactions of The Japan Institute of Electronics Packaging Vol. 1, No. 1, 2008 Fig. 3 IGBT module structure and specifications. Table 1 Characteristics of ceramics used for insulating substrate Thermal Thermal Young s Ceramic Ceramics conductivity expansion modulus thickness coefficient W/m K 10 6 /K GPa mm Alumina Aluminium nitride Silicon nitride Copper base thickness 3 sequently, we studied how to improve the heat dissipation characteristics of IGBT modules made using alumina ceramic. The steady-state thermal resistance of a substance is expressed by: Rth = t (2) Sλ where t is the thickness of the substance through which heat flows, S is the cross-section area through which the heat passes, and λ is the thermal conductivity of the substance. Equation (2) suggests that reducing Rth is essential to improve heat dissipation. Figure 4 shows the cross-sectional structure and thermal conductivity of the IGBT modules. Alumina has a higher Rth than copper and solder because of its lower thermal conductivity, therefore the thermal conductivity of the ceramic layer is expected to have a larger effect on the chip temperature. Equation (2) shows that Rth can be reduced by increasing the crosssection area S of the ceramic layer which heat passes through. It may be possible to increase that area S by increasing the copper circuit thickness as shown in the drawing on the right in Fig. 2, because heat is conducted radially from chips. Accordingly, we performed an FEM analysis by varying the thermal conductivity of the ceramic layer and the thickness of the copper material, and examined the relationship between their values and the chip temperature. Figure 5 presents the thermal analysis results. With a copper thickness of 0.25 mm, when the thermal conductivity of a ceramic substrate is changed from 15 W/m K to 60 W/m K chip temperature falls by about 20 C. However, even if the thermal conductivity of the ceramic is increased Fig. 4 Cross-sectional structure of IGBT modules. 42

4 Nishimura et al.: Development of a New-Generation RoHS IGBT (4/8) Fig. 6 Chip temperature (steady state). Fig. 5 Relationship between thermal conductivity of ceramic, copper circuit thickness, and chip temperature. to 170 W/m K from 70 W/m K, chip temperature falls by only about 4 C. This implies that the thermal conductivity of the solder also has an effect; the heat resistance layer changes from the ceramic layer to the solder layer. The thermal conductivity of solder is 60 W/m K. Tin is the main ingredient in lead free solder material, and its thermal conductivity is 68 W/m K. Thus, we cannot expect a large improvement in the thermal conductivity of the solder material. Therefore, we conclude that the optimal value of the thermal conductivity of the ceramic substrate in a conventional IGBT module structure is 60 W/m K. Chip temperature is also reduced by increasing the thickness of the copper circuit from 0.25 mm to 0.6 mm. When the thermal conductivity of ceramic substrate is 20 W/m K, chip temperature is reduced by 10 C. However, when the thermal conductivity of the ceramic is 170 W/m K, the fall in chip temperature is about 6 C. This suggests that thickening the copper circuit has an effect when the thermal conductivity of the ceramic substrate is low. From these results, we would expect a ceramic material with thermal conductivity of 30 W/m K and copper circuit with thickness of 0.6 mm to achieve a chip temperature equivalent to that of an existing aluminum nitride substrate. Therefore, we performed a thermal assessment under the same conditions as the FEM analysis, using two test pieces: one made of alumina ceramic with thermal conductivity of 28 W/m K and a copper circuit with a thickness of 0.6 mm, and the other made of aluminum nitride ceramic with thermal conductivity of 170 W/m K and a copper circuit with a thickness of 0.25 mm. Figure 6 shows the temperature distribution on the chip surface after being energized by 80A DC for 5 minutes. By increasing the thermal conductivity of the alumina ceramic material to 28 W/m K and the copper circuit thickness to 0.6 mm, the difference in temperature between the new chip and the AIN substrate was decreased by approximately 3 degrees. This value is almost the same as the value calculated by the FEM analysis shown in Fig. 5. Packaging density has increased in recent years, with one package containing plural IGBTs in actual IGBT modules. This is expected to affect the thermal interference among chips, so we investigated the effect of chip spacing on chip temperature. Figure 7 shows the chip spacing and temperature distribution and Fig. 8 shows the relationship between the chip spacing and maximum chip temperatures. These figures show that as the chip spacing becomes smaller, the chip temperature rises. The temperature distribution conditions in Fig. 7 show that at the center of the products with chip spacing of 0.5 mm or 2 mm, the chip edges have the maximum temperature and their thermal interferences are high. This means that there is a trade-off between lower chip temperature and higher packaging density. The temperature distribution on the chip surface should be made as even as possible because an uneven temperature distribution may cause thermal runaway or decrease reliability. Since the central part of the chips reaches the maximum temperature in products with chip spacing of 4 mm or more and the thermal interference of the chips is smaller, products with higher density mounting should be designed with a chip spacing of at least 4 mm. Based on the above results, we optimized the new package to consider the effect of thermal interference. Figure 9 compares the results of the FEM analysis for the temperature distributions of the conventional and new packages. 43

5 Transactions of The Japan Institute of Electronics Packaging Vol. 1, No. 1, 2008 Fig. 9 Comparison of temperature distribution by FEM anal- ysis. forms to certain standards. It has been reported that oscilfig. 7 Temperature distribution of various chip spacing con- lation from a resonant closed loop circuit between IGBT figurations. module and snubber circuit constitutes a radiation source and is a mechanism by which noise radiation is generated in this frequency region.[6] Maxwell s equation for a distant field is expressed as: E = f 2 S I/r (3) where f is the frequency, I is current, S is current loop area, and r is distance; a distant field is dependent on the current closed loop area of the snubber circuit and switching element. Accordingly, in order to reduce the P N current loop area inside the package, we improved the DCB copper circuit pattern wiring configuration, and studied not only element characteristics in the conventional way, but also the package itself for the purpose of reducing noise. Figure 10 shows the P N current loop areas of the conventional and new package structures. We designed the new package so that the P N current loop area was reduced by 50% compared to the conventional package. Figure 11 Fig. 8 Relationship between chip spacing and chip tempera- gives the noise radiation results. The peak value of the ture. noise radiation was reduced by approximately 5 db. Consequently, the turn-on speed can be increased further, which is expected to reduce switching loss. In the conventional package, since the IGBT chips are con- 3.3 RoHS-compliant IGBT module structure centrated near the center of the package, the temperature Lead solder is used in IGBT modules, mainly as a solder of the central part of the chips is higher. On the other material. Major technical challenges in changing to lead- hand, the new package with optimal chip layout and chip free solder are ensuring reliability after changing the spacing provides an almost even temperature distribution solder material, and the higher temperature of devices and its Tj was reduced by up to 10 C. mounted with lead-free solders.[7] To address the higher 3.2 Noise characteristics temperature of mounted devices, we changed the material An inverter must be designed so that the level of noise to increase the heatproof temperature and also changed radiation in the frequency range of 30 MHz to 1 GHz con- the mounted device. Solder material is used in the follow- 44

6 Nishimura et al.: Development of a New-Generation RoHS IGBT (6/8) Fig. 10 Internal layout with lower noise. ( α2 α1) te 2 2 α = α1 + (t E + t E ) (4) where α 1 is the ceramic CTE, t 1 is ceramic thickness, E 1 Fig. 11 Comparison of noise radiation. a)conventional package structure; b)new package structure. ing parts in IGBT modules: (1) IGBT chips, joining areas of the copper circuit and (2) DCB substrate, joining areas of the copper base. As for (1), Fuji Electric has been using lead-free solder[8] since 1998 and has succeeded in improving power cycle reliability.[9] In this new package, we developed a DCB substrate that complies with the leadfree requirement. As shown in Fig. 1, there is a major difference in the CTEs of the ceramic material and copper base used in the DCB substrate. Consequently, the stress in the solder layers is concentrated during the heat cycle, causing fracture. In order to reduce stress, we propose a method for making a small CTE difference by using Cu Mo, ALSIC,[10] and Cu Cu2O[11] in the DCB substrate. These composite materials have low thermal conductivity and high cost as compared with copper. Therefore, they are used only for hybrid vehicles and electric railroad equipment that need high reliability. We investigated the CTE of a DCB substrate close to copper. The horizontal CTE in the complex which is a three-layer composite material of copper/ceramic/copper-like ceramic insulation board is expressed as the following equation. is the ceramic Young s module, α 2 is the copper CTE, t 2 is copper circuit thickness, and E 2 is the copper Young s module. Equation (4) and Table 1 show that increasing copper circuit thickness t 2 can increase the CTE of DCB substrate. The copper thickness was evaluated for its impact on the CTE on the DCB substrate surface. Figure 12 shows the results of measuring the CTE of the copper circuit surface with the alumina ceramic material (t = 0.32 mm) and copper circuits of various thicknesses. The CTE of the DCB substrate surface with a copper circuit of 0.25 mm was almost the same as that of alumina, /K. By increasing the copper circuit thickness to 0.4 mm, the CTE of the DCB substrate surface was increased to /K. This result shows that the difference in the CTEs of the copper circuit surface of the DCB substrate and the copper base can be decreased by increasing the copper circuit thickness to more than its usual value, 0.25 mm. We performed thermal cycle tests on the samples with a copper circuit thickness of 0.5 mm at temperatures ranging from 40 C to 120 C. Figure 13 shows the test results. In the conventional DCB substrates, cracks of approximately 1.5 mm occurred after 1000 cycles, whereas in the sample with a copper circuit thickness of 0.5 mm, no cracks were observed after 1000 cycles. This result shows that the resistance characteristics in the heat cycle test are improved by increasing the copper circuit thickness. Since a thicker solder means that less stress is generated per unit of thickness, the solder thickness underneath the DCB substrate is specified in order to ensure reliability. The results in Fig. 13 show that reliability was 45

7 Transactions of The Japan Institute of Electronics Packaging Vol. 1, No. 1, 2008 Fig. 12 CTE. Relationship between copper circuit thickness and Fig. 13 Relationship between copper circuit thickness and resistance characteristics in heat cycle test. Fig. 14 Temperature cycle test results after 300 cycles: solder thickness was two-thirds of that used in conventional products. improved by increasing the copper circuit thickness. We investigated the reliability of conventional packages and new packages in which solder thickness was reduced to two-thirds that of the conventional products. Figure 14 shows the thermal cycling test results. Solder cracks occurred at the corner of the conventional package after 300 cycles, whereas no cracks were observed in the new package in which the copper circuit thickness was increased to 0.6 mm. These results confirm the amount of lead-free solder in the new package can be reduced to two-thirds of that in conventional products. 4. Conclusion We have investigated a new IGBT module structure for power management, considering heat dissipation, electromagnetic noise reduction, and environmental resistance such as higher thermal cycling capability, with lead-free soldering. The design can reduce junction temperature to almost the same value as that on an aluminum nitride substrate by increasing the copper circuit thickness of the DCB substrate to 0.6 mm in thickness and by improving the thermal conductivity of the alumina material to 28 W/m K. Moreover, we investigated the effect of the chip layout on thermal interference and confirmed the most effective chip mount spacing is 4 mm or more. In the experiments, we confirmed a reduction of 10 degrees in the junction temperature, good performance in thermal cycling capability, and a 5 db noise reduction due to a decrease of 50% of the P N current loop area of Cu foil circuit, compared with the conventional package structure. Thus we have successfully developed a new IGBT package structure using a lead-free solder by increasing the copper circuit thickness on the alumina based-ceramic substrate. References [1] G. Majumdar, Trends of Intelligent Power Module, IEEJ Trans. 2007, pp [2] T. Laska, M. Munzer, F. Pfirch, C. Schaeffer and T. Schimidt, The Field Stop IGBT(FS IGBT)-A New Power Device Concept with a Great Improvement 46

8 Nishimura et al.: Development of a New-Generation RoHS IGBT (8/8) Potential, Proc. ISPSD 2000, pp [3] Y. Onozawa, M. Otsuki, N. Iwamuro, S. Miyashita, T. Miyasaka and Y. Seki, 1200-V Low-Loss IGBT Module With Low Noise Characteristics and High dic/dt Controllability, IEEE Transaction on Industry Applications, Vol. 43, No 2, 2007, pp [4] M. Otsuki, Y. Onozawa, M. Kirisawa, H. Kanemaru, K. Yoshihara and Y. Seki, Investigation on the short circuit capability of 1,200V trench gate field-stop IGBTs, Proc ISPSD 2002, pp [5] Directive 2002/95/EC of European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment, the Official Journal of European Union, L37, , p. 19. [6] S. Igarashi, S. Takizawa, K. Kuroki and T. Shimizu, Analysis and Reduction Methods of EMI Radiation Noise from Converter System, a publication of the Industry Applications Society, The Transactions of the Institute of Electrical Engineers of Japan. Vol. 118 D, No. 6, 1998, pp [7] S. Katsuaki, Current Status of Low Temperature Soldering, Journal of Japan Institute of Electronics Packaging, Vol. 9, No. 3, 2006, pp [8] M. Nagano, N. Hidaka, H. Watanabe, M. Shimoda and M. Ono, Effect of Additional Elements on Creep Properties of the Sn Ag Cu Lead Free Solder, Journal of Japan Institute of Electronics Packaging. Vol. 9, No. 3, 2006, pp [9] A. Morozumi, K. Yamada, T. Miyasaka, S. Sumi and Y. Seki, Reliability of Power Cycling for IGBT Power Semiconductor Modules, IEEE Transactions on Industry Applications. Vol. 39, No. 3, /06, pp [10] M. K. Premkumar, Al/SiC for power electronics packaging, Advanced Packaging Materials. Proceedings., 3rd International Symposium, 1997, pp [11] R. Saito,Y. Kondo, Y. Koike, K. Okamoto, T. Suzumura and T. Abe, Novel High Thermal Conductivity, Low Thermal Expansion Cu Cu2O Composite Base Plate Technology for Power Module Application, Proc ISPSD, 2001, pp