RECENTLY, a demand for transparent display applications

Transcription

1 3940 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011 Endurance Characteristics of Amorphous-InGaZnO Transparent Flash Memory With Gold Nanocrystal Storage Layer Jaeman Jang, Jae Chul Park, Dongsik Kong, Dong Myong Kim, Member, IEEE, Jang-Sik Lee, Member, IEEE, Byeong-Hyeok Sohn, Il Hwan Cho, Member, IEEE, anddaehwankim,member, IEEE Abstract The amorphous indium gallium zinc-oxide (a-igzo) thin-film transistor (TFT)-based nonvolatile transparent Flash memory devices were fabricated with gold (Au) nanocrystal storage layer. The performance and the reliability of transparent memory devices have been characterized by experiment and technology computer-aided design simulation. This memory device shows a large-enough memory window V = 4.7 V at the program/erase (P/E) voltage V PGM /V ERS = 35/ 35 V for the P/E time T PGM /T ERS = 3/25 s. The memory window was kept almost the same after 1050 P/E cycles; however, the center voltage of the memory window (V C ) was shifted in a negative direction. The cycling effect was explained by the change in the density of states (DOS) and the acceptor-like interface-trap density D ita (E) in the a-igzo channel layer with increasing P/E cycles. The main mechanism for the change in V C was found to be the accelerated injection of holes into the gate insulator due to the energy band bending during the erase operation. Index Terms Amorphous indium gallium zinc-oxide (a-igzo), density of states (DOS), nonvolatile memory, thin-film transistors (TFTs). I. INTRODUCTION RECENTLY, a demand for transparent display applications has been increasing in various respects. Transparent electronics offers an opportunity to develop optoelectronic devices for see-through display technologies and other applications [1]. A key element to realize transparent circuits is a transparent thin-film transistor (TFT) [2]. Therefore, studies on transparent oxide-tfts have attracted considerable attention Manuscript received June 9, 2011; revised July 21, 2011; accepted August 2, Date of current version October 21, This work was supported by the Mid-Career Researcher Program through the National Research Foundation grant funded by the Ministry of Education, Science, and Technology under Grant The review of this paper was arranged by Editor A. Schenk. J. Jang, D. Kong, D. M. Kim, and D. H. Kim are with the School of Electrical Engineering, Kookmin University, Seoul , Korea ( drlife@ kookmin.ac.kr). J. C. Park is with Samsung Advanced Institute of Technology, Yongin , Korea. J.-S. Lee is with the School of Advanced Materials Engineering, Kookmin University, Seoul , Korea. B.-H. Sohn is with the Department of Chemistry and the NANO Systems Institute, Seoul National University, Seoul , Korea. I. H. Cho is with the Department of Electronic Engineering, Myongji University, Yongin , Korea. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED with respect to display applications because of their capability for large-scale and low-cost fabrication at low temperature [3] [5]. Among many types of transparent oxide semiconductors (TOSs), the indium gallium-doped amorphous zinc oxide [amorphous indium gallium zinc-oxide (a-igzo)] is one of the most promising TOSs and offers many advantages over conventional amorphous/polycrystalline silicon in terms of its high mobility, high aspect ratio, and low processing temperatures [6] [10]. Most of the research in this field is focused on improving the electrical properties of TFTs with a-igzo films for the active layer [11], [12]. Meanwhile, the nanocrystal charge trap memory is also expected to be a promising next-generation storage device [13]. Nanocrystal Flash memory devices have advantages over the conventional memory devices with improved flexibility in the design through a controllable state-of-the-art process forming nanocrystal arrays. In particular, by adopting a conducting metal for nanocrystals, a metal nanocrystal memory has significant advantages with higher density for charge storage nodes, stronger coupling with the conduction channel, a wide range of available work function, and smaller energy perturbation due to a carrier confinement [13] [15]. We also note that there is a new approach to implement a transparent nonvolatile Flash memory device with TOSs for various innovative applications [16] [21]. This is because these memory device cells can be easily integrated into the display devices. Specifically, nonvolatile memory devices based on a- IGZO TFTs can be applied to flexible electronic devices because a-igzo thin films can be synthesized at low temperature [18] [21]. As a possible transparent nonvolatile memory in the nextgeneration, the nonvolatile nanocrystal Flash memory devices have been fabricated and characterized based on lowtemperature-processed controlled gold (Au) nanocrystals as a charge storage layer and the a-igzo film as an active layer [20], [21]. However, the memory characteristics of a-igzo memory with gold nanocrystals were introduced through previous works [20], [21]; the detailed analysis of reliability is not yet clarified. In this paper, the endurance characteristics and physical mechanisms of the Au nanocrystal-embedded a-igzo transparent memory device was explained through the extracted physical parameters of the a-igzo active layer including the subgap density of states (DOS) and the density of interface /$ IEEE

2 JANG et al.: ENDURANCE CHARACTERISTICS OF a-igzo TRANSPARENT FLASH MEMORY 3941 The three-dimensional structure of the Au nanocrystalembedded a-igzo-based transparent memory device with an inverted staggered type, which is the most commonly used for TFTs, is shown in Fig. 1. The memory device was fabricated with an a-igzo channel and the Au nanocrystal storage layer on the glass substrate. A brief fabrication procedure for the Au nanocrystalembedded a-igzo transparent memory devices is as follows. On a glass substrate, the first sputtered deposition at room temperature (RT) and the patterning of the molybdenum (Mo) gate are followed by plasma-enhanced chemical vapor deposition (PECVD) of the blocking oxide (T bot = 70 nm) at 300 C. In addition, the Au nanocrystal charge storage layer was formed. The synthesis of the charge trapping layer has been already reported in detail elsewhere [24], [25]. In brief, Au nanocrystals were synthesized using polystyrene-block-poly (4-vinyl pyridine) purchased from Polymer Source, Inc. Au as a metallic nanocrystal was selected since it not only has a suitable work function (5.5 ev) for such applications but also exhibits a low anneal temperature for nanocrystal formation, which is advantageous to the quality of underlying SiO 2 dielectrics. Combining advantages of both the metal nanocrystal and the high tunneling barrier, excellent data retention characteristics have been achieved without yielding the programming efficiency. Then, 30-nm-thick tunneling oxide (T top = 30 nm) was deposited onto the storage layer by PECVD. The a-igzo active layer (Ga 2 O 3 : In 2 O 3 : ZnO = 2:2:1 at.%) is then sputtered by the radio-frequency magnetron sputtering at RT in a mixed atmosphere of Ar/O 2 (100:1 at standard cubic centimeters per minute) and patterned by the wet etch process with diluted HF. For the formation of source/drain (S/D) electrodes, Mo is sputtered at RT and then patterned by dry etching. After N 2 O plasma treatment on the channel surface of the a-igzo active layer, a SiO 2 passivation layer is continuously deposited at 150 C by PECVD without a vacuum break. Finally, annealing in the furnace at 250 C is performed for 1 h in an N 2 atmosphere. The structural parameters of the Au nanoparticle-embedded transparent a-igzo TFT Flash memory are designed to be W IGZO = 5 µm for the width of the region between the gate and the a-igzo active, L IGZO = 15 µm for the length between the S/D and the a-igzo active, T IGZO = 60 nm for the thickness of the IGZO layer, L OV = 5 µm for the overlap between the gate and the S/D, the nanocrystal density per unit area N = cm 2, the diameter of nanocrystals D = 14 nm, and the distance between the nanocrystals S = 30 nm, as indicated in Fig. 1(a) (c). Fig. 1. Device structure of the Au nanoparticle-embedded transparent a-igzo TFT Flash memory. (a) Schematic top view; (b) cross-sectional view, A - A ; and (c) cross-sectional view, B - B. traps (D it ) by the multifrequency C V method (MFM) and the DOS-based amorphous oxide TFT simulations (DeAOTSs) [22], [23]. II. FABRICATION OF Au NANOCRYSTAL-EMBEDDED a-igzo TRANSPARENT MEMORY DEVICES III. CHARACTERIZATION OF ENDURANCE IN THE Au NANOCRYSTAL-EMBEDDED a-igzo TRANSPARENT MEMORY A. Program/Erase Operations The operation of the Au nanocrystal-embedded a-igzobased transparent memory was experimentally verified. The program/erase (P/E) characteristics are measured, and physical mechanisms are investigated combining the energy band diagrams. Memory operations of the Au nanocrystal were experimentally verified applying the same program operation to a-igzo TFT devices with and without the nanocrystal storage layer at the interface between the tunneling oxide and the insulating oxide. Fig. 2 show the transfer characteristics of a-igzo TFTs. The program was performed at the gate-to-source voltage V GS = 20 V and a stress time of 1 s keeping the source and the drain grounded. As shown in Fig. 2(a), the threshold voltage V T shift was not observed in the a-igzo TFT device without the Au nanocrystal storage layer even after programming. For the a-igzo TFT

3 3942 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011 Fig. 2. Transfer characteristics of the transparent memory device (a) without and (b) with the Au nanocrystal storage layer. The initial curve was measured without a P/E operation. The program states were achieved by applying bias stresses of 20 V to the gate for 100 ms and 1 s. device with the Au nanocrystal storage layer after the same program condition, on the other hand, V T was clearly shifted by V T = 3 V in a positive direction, as shown in Fig. 2(b). It is clear that the Au nanocrystal layer works as a storage layer for the transparent memory device implemented in a-igzo TFTs. B. Endurance Characteristics Fig. 3 shows the endurance characteristics of the Au nanocrystal-embedded oxide TFT Flash memory device. The program was performed at V PGM = 35 V for T PGM = 3s, and the erase operation was performed at V ERS = 35 V for T ERS = 25 s under photonic illumination from the backlight unit. Fig. 3(a) shows that the programmed and erased V T values were shifted with increasing the number of P/E cycles. The difference of the programmed and erased V T values (Memory window V = 4.7 V) was maintained constant after 1050 P/E cycles. The memory window was independent of the P/E cycles, as shown in Fig. 3(b). However, the center voltage of the memory window (V C ) was shifted by 12.7 V after repeated P/E cycles, and the shifted V T may cause errors during the READ operation. This phenomenon seems to be the same as the V T characteristics of the negative-bias illumination stress effect in a-igzo oxide TFTs [11], [12]. In this paper, the negative V T shift phenom- Fig. 3. Endurance characteristics of Au nanocrystal-embedded a-igzo transparent memory device. (a) Threshold voltage shift as a function of P/E states and P/E cycling. (b) Memory window ( V = V T_PGM V T_ERS ) change as function of the number of P/E cycling. enon with repeated P/E cycles is investigated by the extraction of DOS and D it after P/E cycles. C. Cycling-Dependent DOS and D it in the a-igzo Active Layer The physical parameters including DOS and D it were extracted by the MFM combined with the DeAOTS [22], [23]. The measured C V characteristics of the Au nanocrystalembedded a-igzo transparent Flash memory device are shown in Fig. 4. Fig. 4(a) and (b) show the frequency-dependent C V characteristics for the initial state before P/E cycling and after 1050 P/E cycles. The C V characteristics were measured at small-signal frequencies f = 10, 100, and 500 khz for the MFM technique. Fig. 5 shows the extracted subgap acceptor-like DOS g A (E) (in ev 1 cm 3 ) of the a-igzo active layer. Assuming an exponential distribution of the deep states, it can be modeled as g A (E) =g DA (E)+g ( TA (E) E EC = N DA exp kt DA ) +N TA exp ( E EC kt TA ). (1) We note that four characteristic parameters N TA, N DA, kt TA, and kt DA in g A (E) are not fitting parameters but physical and extractable parameters because they can be experimentally extracted [26] [28].

4 JANG et al.: ENDURANCE CHARACTERISTICS OF a-igzo TRANSPARENT FLASH MEMORY 3943 Fig. 4. Frequency-dependent C V characteristics measured by using LCR meter (HP 4284 A). (a) Before P/E cycling. (b) After P/E 1050 cycling. Fig. 5(a) and (b) show the subgap acceptor-like DOS at the initial state and after 1050 P/E cycles. The subgap acceptorlike DOS was increased with increasing the number of P/E cycles. In particular, we observed that the deep acceptor-like DOS g DA (E) was significantly increased after P/E cycles, and this results in a positive shift of V T with increasing P/E cycles. The shallow donor state (equivalent to the oxygen vacancy state, i.e., V O V 2+ O + 2e ) and the interface trap D it were extracted by the DeAOTS based on the acceptor-like DOS. Fig. 6 shows the P/E-cycle-dependent DOS and D it. The donorlike DOS g D (E) [the valence band tail state density g TD (E) and the shallow donor state density g OV (E);ineV 1 cm 3 ] and the interface-trap density D it (E) [the acceptor-like interfacetrap density D ita (E) and the donor-like interface-trap density D itd (E);ineV 1 cm 2 ] of the a-igzo films were presumably modeled as g D (E) =g TD (E)+g ( OV (E) ) EV E = N TD exp kt [ TD ( ) ] 2 EOV E + N OV exp kt OV kt D_it (2) D it (E) =D ita (E)+D ( itd (E) ) E EC = N A_it exp kt ( A_it ) EV E + N D_it exp. (3) Fig. 5. Extracted g A (E) for various combinations of f 1, f 2,andf 3.The acceptor-like DOS is confirmed to be immune to the range of frequency combinations in the multifrequency C V characterization (f 1, f 2, f 3 = 10, 100, 500 khz, respectively). Therefore, parameters N TD, kt TD, N OV, kt OV, E OV, N A_it, kt A_it, N D_it and kt D_it in g TD (E), g OV (E), D ita (E), and D itd (E) can act as fitting parameters, in contrast with the g A (E) parameters. On the other hand, the flat-band voltage V FB and E FB (defined as the energy difference between the Fermi level E F and the conduction band minimum E C at the V GS = V FB condition) are calculated below. Fig. 7 shows the energy band diagram at the flat-band (V GS = V FB ) condition. Assuming that the gate is made of molybdenum, for example, V FB is calculated from the work function difference φ Mo φ IGZO and the charge density per unit area in the gate oxide Q OX, as described by V FB = φ MO φ IGZO Q OX C OX (4) φ MO φ IGZO =(χ MO χ IGZO ) E FB q (5) where C OX = ε OX /T OX and T OX (= T bot + T top ) are the oxide capacitance per unit area and the thickness of the gate insulator, respectively. The extracted physical parameters of the a-igzo active layer were summarized in Table I. In Fig. 8, the measured and simulated I DS V GS curves before cycling and after 1050 P/E cycles are comparatively shown in linear and log scales for the experimental data plotted with simulation results from the DeAOTS. The results agree very well for the initial and P/E-cycled cases.

5 3944 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011 Fig. 7. Energy band diagram for transparent Flash memory devices at the V GS = V FB condition. TABLE I MODEL PARAMETERS EXTRACTED BY USING MFM AND DeAOTS FROM THE a-igzo ACTIVE LAYER BEFORE AND AFTER 1050 P/E CYCLES Fig. 6. Extracted DOS parameters of the a-igzo active thin film in the Au nanocrystal-embedded a-igzo transparent memory device. The measured g A (E) (extracted by the multifrequency technique), model g TD (E), g OV (E), and D it (E) (extracted by using DeAOTS). (a) DOS and (b) D it parameters before P/E cycling, (c) DOS and (d) D it parameters after P/E 1050 cycling. D. Mechanisms on P/E Cycling Effect The endurance characteristics under the illumination of the Au nanocrystal-embedded a-igzo transparent Flash memory device are very important for the robust operation of memory operations. Here, we explained the cycling effect for the Au nanocrystal-embedded transparent memory through the extraction of DOS and D it parameters. The P/E-cycling-dependent DOS and D it of a-igzo active layer are shown in Fig. 9. The acceptor-like DOS g A (E) and the shallow donor state density g OV (E) were increasing with increasing the number of P/E cycles, as shown in Fig. 9(a). The

6 JANG et al.: ENDURANCE CHARACTERISTICS OF a-igzo TRANSPARENT FLASH MEMORY 3945 Fig. 8. Measured I DS V GS curves (red line and symbol) before cycling and (blue line and symbol) after P/E 1050 cycling. (a) I DS V GS curve in the linear scale. (b) I DS V GS curve in the log scale compared with the simulation results from the DeAOTS. They agree very well, depending of the number of P/E cycles. Fig. 9. P/E-cycling-dependent DOS and D it of the a-igzo active layer. (a) g A (E) and g OV (E), and(b)d ita (E) increased with increasing the number of P/E cycling. increased acceptor-like DOS can be expected to shift V T in a positive direction due to electron trapping in the increased DOS. On the other hand, the increased shallow donor traps result in a negative shift of V T. We also note that the Subthreshold Swing (SSW) is degraded by the increased acceptor-like interface-trap density D ita (E) caused by the P/E cycles as shown in Fig. 9(b). Fig. 10 shows the energy band diagram to explain the physical mechanism for the endurance characteristics of the a-igzo transparent memory devices. The negative shift of V C was experimentally observed with increasing the number of P/E cycles. According to the analysis of the extracted DOS and D it, the V C shift was possible in the both negative and positive directions. First, the increased acceptor-like DOS may cause a positive shift of V C by the electron trapping in the a-igzo channel layer. Second, the increased shallow donor traps with the increased ionization of oxygen vacancies (V O V 2+ O + 2e ) may cause a negative shift of V C by the electron detrapping in the a-igzo channel through the conduction band minimum and the carrier generation. Third, a hole injection into the gate insulator during the erase operation under illumination condition with accelerated electric field by energy band bending induced due to generated holes may cause a negative shift of V C by the injected hole charge Q OX in the gate insulator. We observed the final shift of the center voltage V C = 12.7 V. Fig. 10. Energy band diagram illustrating the mechanisms of Au nanocrystalembedded a-igzo transparent memory devices after P/E cycling. With the SSW degradation caused by the increased interface traps, the interface-trap states was increased with the increasing number of program cycles (SSW : V/dec). AshiftinV C with P/E cycles can be explained by three main mechanisms supported by the quantitative extraction by the DeAOTS, as shown in Fig. 11. The increased acceptorlike DOS causes V C = V Acceptor like DOS = 1.4 V and the injected holes in the gate insulator during the erase operation cause V C = V OX = 10.4 V, and the increased shallow donor state causes V C = V OV = 3.7 V. Finally, the net shift of the center voltage V C = 12.7 V was resulted and agrees with the experimental observation. V OX in Fig. 11

7 3946 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011 Fig. 11. Quantitative analysis of the P/E-cycle-induced V T shift. comes from the Q OX in (4). Among V Acceptor like DOS, V OX and V OV, the net V C is dominated by V OX as shown in Fig. 11. Therefore, the main mechanism on the P/E cycling-induced change in V C was found to be the accelerated injection of holes into the gate insulator due to the energy band bending during the erase operation. IV. CONCLUSION In this paper, Au nanocrystal-embedded a-igzo transparent Flash memory devices have been fabricated and characterized with Au nanocrystals as a charge storage layer and a-igzo films as an active layer. The transparent memory device performance and operation mechanisms were investigated. The endurance characteristics and the related physical mechanisms of the Au nanocrystal-embedded a-igzo transparent memory device have been explained through the extracted physical parameters of the a-igzo active layer including DOS and D it by the MFM technique and the DeAOTS simulator. The memory window has been remained the same after 1050 P/E cycles; however V C has been shifted in a negative direction with increasing the P/E cycles. Typically, the effect has been reported and explained to be similar to the negative-bias illumination stress effect. Thus, the P/E cycle-dependent negative V C shift has been explained by the extracted DOS and D it changes with increasing P/E cycles. Through a simulation, it was found that the main mechanism of a shift in V C is due to the accelerated hole injection into the gate insulator during the erase condition caused by the energy band bending. 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Jaeman Jang received the B.S. and M.S. degrees from Kookmin University, Seoul, Korea, in 2009 and 2011, respectively, where he is currently working toward the Ph.D. degree in electrical engineering. During his M.S. studies, he has worked on modeling, characterization, and design of nanoscaled memory device including capacitorless 1-transistor dynamic random-access memory and nanocrystal Flash memory device. His current research interest includes design, fabrication, characterization, and modeling of oxide thin-film transistors and organic Jae Chul Park, photograph and biography not available at the time of publication. Dongsik Kong received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in 2010, where he is currently working toward the M.S. degree in the Department of Electrical Engineering under the supervision of Prof. D. M. Kim and Prof. D. H. Kim. His current research mainly focuses on amorphous oxide semiconductor thin-film transistors and their device physics. Dong Myong Kim (S 86 M 88) received the B.S. (magna cum laude) and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1986 and 1988, respectively, and the Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, MN, in Since 1993, he has been with the School of Electrical Engineering, Kookmin University, Seoul, Korea. His current research interests include fabrication, characterization, and modeling of nanostructure silicon devices, III V compound semiconductor devices, memory devices, and complementary metal oxide semiconductor radiofrequency circuits. Jang-Sik Lee (M 06) received the B.S., M.S., and Ph.D. degrees in materials science and engineering from Seoul National University, Seoul, Korea, in 1997, 1999, and 2002, respectively. In 2002, he was a Director s Postdoctoral Fellow with Los Alamos National Laboratory. In 2004, he was a Senior Research Engineer with the Memory Division, Samsung Electronics, and was in charge of the integration and the device reliability of 32-Gb Flash memory devices. Since 2006, he has been with Kookmin University, Seoul, Korea, where he is currently an Associate Professor with the School of Advanced Materials Engineering. He has authored more than 80 research publications and patents. His research interests include nonvolatile memory devices, low-temperature poly-si thin-film transistors, nanostructured materials and devices, and epitaxial thin-film growth and applications. Dr. Lee is a member of the Materials Research Society, the Electrochemical Society, the Korean Institute of Metals and Materials, and the Korean Institute of Electrical and Electronic Material Engineers. Byeong-Hyeok Sohn received the Ph.D. degree in polymer science and technology from Massachusetts Institute of Technology (MIT), Cambridge, in After postdoctoral work with MIT and the University of Wisconsin Madison, Madison, he was a Faculty Member with the Department of Materials Science and Engineering, Pohang University of Science of Technology, Pohang, Korea, in Since 2004, he has been with the Department of Chemistry, Seoul National University, Seoul, Korea. His main research interest is polymeric and soft nanomaterials for nanotechnology applications. Il Hwan Cho (M 10) received the B.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology, Daejon, Korea, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2002 and 2007, respectively. From March 2007 to February 2008, he was a Postdoctoral Fellow with Seoul National University, where he was engaged in the research on characterization of bulk fin-shaped field-effect transistor silicon-oxide-nitride-oxide-silicon Flash memory. Since 2008, he has been with the Department of Electronic Engineering, Myongji University, Yongin, Korea, where he is currently an Assistant Professor. His current research interests include the improvement of nanoscale nonvolatile memory and the characterization of high-k dielectric layer. Dae Hwan Kim (M 08) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2002, respectively. From 2002 to 2005, he was with Samsung Electronics Company, Ltd., Kyung ki-do, Korea, where he contributed to the design and the development of 92-nm double data rate (DDR) dynamic RAM (DRAM) and 80-nm DDR2 DRAM. Since 2005, he has been with the School of Electrical Engineering, Kookmin University, Seoul, Korea, where he is currently an Associate Professor. He has authored or coauthored more than 170 research publications and patents. His current research interests are nanoscale CMOS devices and integrated circuits, metal oxide and organic thin-film transistors, biosensors devices, exploratory logic and memory devices, energyefficient nano-integrated circuits, and Si quantum devices. He has also worked on the characterization, the modeling, and the circuit design for reliabilities of CMOS devices, thin-film transistors, display, biosensors, and neuromorphic systems. Dr. Kim is a member of the IEEE Electron Devices Society, the Society for Information Display, and the Institute of Electronics Engineers of Korea.