Evaluation approaches for robust deep submicron (DSM) monolithic integrated circuit (IC) components of the shelf (?)

Transcription

1 Evaluation approaches for robust deep submicron (DSM) monolithic integrated circuit (IC) components of the shelf (?) Dr. Horst A. Gieser, Dr. Philippe Perdu Workshop OCT 09, 2009 in Arcachon

2 DSM COTS for Space Applications Memories Flash SRAM DRAM FRAM µ-controllers and Proc. Cores Analog & Mixed Signal: AD- and DA-Converters GHz-RF- and Wideband: Highspeed Comm. Interfaces FPGAs Other? Dellin IRPS 2004

3 Different Levels of Oxide BD 60 nm Prof. PEY KIN LEONG Mr. LI XIANG, NTU IPFA 2009

4 Reliability tests after minor GOX-damage 60 CDM pre-stressed inputs 50 unstressed reference inputs Pins Fail Stress Test Fail Pins Stress Test Fail 20 0 Dyn. LT 100h 3 13 Dyn. LT 100h 0 Handling Static LT 3h 4 18 Static LT 3h V-Ramp to 14V 6 16 V-Ramp to 16V HBM < 50 V 15 3 HBM > 1300V 1 Electrical and Physical Failure Signatures: I leak >> 10 µa, Gateoxide damage input inverter I leak >> 10 µa; Junction burnot protection element Gieser, Reiner et al ESREF1993 & QREI 1994 Volume 10 No. 4

5 Gate Oxide Damage at Input after CDM HBM CDM CDM + RT Storage Field MOS- Input -transistor virgin 1.) < 500 V CDM 2.) < 50 V HBM or other Pulse Transistor with amorphous, high-ohmic damage Polycrystalline, low-ohmic damage TEM after FIB J. Reiner EOS95 H. Gieser et. al. ESREF93

6 Ultra-thin Gate Oxides Technology Approach For High-k/Metal Gates See Garros IRPS Dellin IRPS 2004

7 1st LOTUS WS 2008: Motivation at the Chip Level Reliability uncertainties of complex DSM technologies result from increased variability of process parameters, new materials and narrow windows of operation. Focus on large quantity consumer electronics. Reduced margins in voltage and temperature for acceleration and screening. ASICS allow conservative Design for Reliability + special Process Monitoring How to obtain robust DSM COTS for harsh envionments??? Life time expectation DSM SM Radiation Voltage Temperature

8 ESA View of Reliability vs Technology Node Laurent Hili European Space Agency Microelectronics Section (TEC-EDM) LOTUS WS1 2008

9 Outline Motivation DSM Failure Mechanisms Approach to select robust devices BIST to support selection process and Health Monitoring Conclusions

10 DSM Failure Mechanisms Gate oxide integrity Ileak Short less critical for hk metal Process induced damage (PID) (Antenna 1) Ileak Short Hot carrier injection (HCI) (Design, Architecture) = f(low Temperature) Vth-Shift Negative bias temperature instabilities (NBTI) = f(processing, Bias, Time) Degradation of electrical parameters (mobility, Vth, drain current, ) Electro- /Stressmigration = f (High Temperature, Current Density) Weak vias and contacts IMD Breakdown Mobile ion concentration Vth-Shift Radiation (Total dose, SEE)

11 Assumptions on DSM Reliability and Parameters Influence of particles and extrinsic defects on reliability decreases. Influence of process variability grows due to atomic scale effects. Defects and degradation slow down devices and increase leakage currents at a given voltage. High gate and SD leakage currents of complex DSM circuits may obscure a defect related Iddq contribution.

12 Test Approaches Testing for Defect WL (Advanced) Part Average WL & PL Testing to select individual device for HiRel application Goal: Identify devices with the highest performance at the lowest supply voltage and Iddq.

13 Screening & Burn-In Issues of DSM Technologies VDDext > Vcore Core 1 1,2 0.9 V Core 2 1,2 0.9 V Bias Generator Supply voltage control Core 3 1,2 0.9 V Internal voltages may be generated and differ from external supply. Blocks may be turned on and off for power control Others?

14 Built-In Gate Stress Test & Drain Leakage Test Chip size + 10%!! " V. Malandruccolo ESREF 2009

15 Testing for Defect Clusters Scrap all defective + all devices from a defect cluster with more than 5/8 surrounding defect devices. Chenn-Jung Huang et al 2002

16 Statistical Testing Part Average Testing PAT with static or dynamic limits AEC-Q001 More effective Regression Analysis RA Principal Component Analysis PCA May be sharpened with neigborhood criteria e.g. Iddq Methods require test ressources and a large data base!! Typically limited to Manufacturer

17 Proposed Test Flow for HiRel Devices Functional WL to select potential HiRel devices from defect free areas Full parametric test (similar to characterization) of selected devices Pre-characterization incl. Iddq Shmoo-Plot : voltage over frequency & Tmin & Tmax High voltage/high temperature screen if applicable Post-characterization and margin evaluation Data Mining

18 Possible Mitigation Approaches Device selection + Design for Reliability: Low Iddq Devices best of breed GOX and SubThreshold Currents Fastest min Tmax Low Power Consumption Reduced Temperature Stress Future: Built-in monitors for performance of blocks chips Example: Temperature sensors for processors or smart power devices System Design: Performance derating and performance on demand for blocks and chips Reduncancy (not fo syncronous systems) Load balancing Adjustable operating voltage Communication of health condition and mission parameters

19 Health Monitoring Growing importance of health monitoring of atcual circuits together with mission profiling. Direct parameters for health monitoring Quiescent current Iddq Gate delay for given voltage and temperature Offset voltage Requirement: Controlled focus of information in time and area: Continuous vs. intermittend global across block or chip vs. local for single cell

20 Step 1 of Health Monitoring Flow for COTs: Intervention Evaluate all possible failure mechanisms and modes in view of application. Identify systematically the most critial and probable failure modes in view of application (Pareto). Identify systematically all relevant parameters that indicate ageing in application. memory access time clock frequency IDDQ temperature of structure or chip Others Evalute their robustness and accessibility via external circuit, BIST and Scan Path Add circuits and SW to communicate health condition to system. Define criterion and level to request action, reconfigure circuit or load pattern.

21 Step 2 of Health Monitoring Flow for COTs: Prognosis Implement infrastructure to monitor the load conditions (mission profile). Relate the amount of degradation to the load conditions. Find and verify model for the ageing by means of relevant multi stress experiments with moderate accelleration Estimate the future load conditions on the basis of history Estimate an remaining life time, maybe adaptive if load conditions change. Limitation: Validitity of model and load prognosis (no abrupt changes) Close the loop: Use results for refining models, mission profiles and future designs. Involve manufacturers to integrate sensor infrastructure even in COTS to increase robustness. Win-Win for all.

22 Employ reliable tools: Capacitive Coupled TLP cc-tlp vs CDM 90 nm CMOS TI VFTLP current / A CC-TLP 125 V CDM time / ns CDM 2.9 A cc-tlp 2.9 A Wolf, Gieser IEW2008/EOSESD 2009

23 Conclusions Complexity of technology and design options increases risk to fail goals Close collaboration and pre-competitive funding required for industry and academia. Statistical functional and parametric testing is done for yield improvement primarily Could be used to identify individual HiRel Devices System design must consider safety margins and redundancy to allow for ageing components Reliability models with encrypted parameter sets are needed to communicate key information on process control parameters and statistics from manufacturers to users of COTS? Employ redundancy, load control, temperature control schemes Employ BIST schemes for health diagnosis and interface to system level not only in ASICs Employ more and more reliable tools

24 Need for Close Collaboration & Funding Users e.g. ESA Requirements Mission Profiles Academia Methodology Analytical Experiments Modeling Suppliers Chip Design for Manufacturability, Testability and Reliability Reliability Modelling Test Ressources Data Mining Natl.and European Funding of Reliability Projects

25 Be aware What we don t see is not what we don t have. Let s dig and look together!