Reliability Challenges for 45nm and Beyond. J. W. McPherson, PhD, TI Senior Fellow Texas Instruments, Inc. Dallas, Texas 75243

Transcription

1 Reliability Challenges for 45nm and Beyond J. W. McPherson, PhD, TI Senior Fellow Texas Instruments, Inc. Dallas, Texas DAC

2 2 Outline Transistor Performance with Scaling Gate Dielectric Scaling Interconnect Scaling Reliability Trends with Continued Scaling --- Leakage --- NBTI --- ESD --- SM --- TDDB --- CHC --- EM --- Joule Heating Defect Issues with Continued Scaling Conclusions/Summary

3 SOURCE GATE DRAIN MOSFET Scaling: More Evolutionary than Revolutionary Gate Oxide Gate Polysilicon Oxide Gate Salicide Salicide Cladding Cladding PolysiliconGate Sidewall SidewallSpacer Spacer Silicon Silicon Substrate Substrate FOM = Source/Drain Lightly LighlyDoped Drain (LDD) Channel Region Channel Region I drive ( C Junction + C Gate + C Interconnect ) V dd MOSFET Scaling : More Evolutionary than Revolutionary for 25 years 3

4 Transistor I drive Versus I off Trends 1.00E E-04 Subthreshold slope remains nearly constant from technology node to node: Ids (A) 1.00E E E-10 Vt must be reduced to maintain good Idrive at lower Vdd Ioff increases with lower Vt due to constant subthreshold slope 1.00E E Vgs (V) Increased transistor I drive usually implies increased I off 4

5 5 Strained-Silicon Performance Enhancement Significant Ion/Ioff improvement Raised S/D Implant S/D strain Substrate orientation PMD liner Strained channel Capped poly Recess S/D epi STI liner Active area epi Ioff log (A/μm) na/μm 35 % improvement Reference SiGe Normal Si lattice Strained Si lattice Improved mobility 680 μa/μm Ion (μa/μm) Defect in Silicon 1. Strained Si can produce an increase in I on without a degradation in I off. 2. Stress-induced defects can occur in the silicon if the stress is not applied properly.

6 Impact of Scaling on Gate-Dielectric Leakage Gate Leakage (A/cm 2 ) 10 4 High Performance Low Power SiO 2 Trendline EOT (Å) Nitrided oxide Gate leakage approaching 1000A/cm2. Nitrided oxides a little less. 6

7 Impact of High-k on Gate-Dielectric Leakage J V fb +1) (A/cm 2 ) EOT high k HfSiON nmoscap HfSiON pmoscap HfSiON NMOS SiO 2 Trendline nmoscap HfON Gate Leakage SiO 2 Trendline EOT (Å) SiO2 = ( ) ( thickness) high k k k High-k thickness can be kept relatively thick, to control leakage, while EOT can be made quite low. 7

8 Interconnect Scaling Trends Cu Cu Cu Cu t 2 Low-k 2 Cu A 1 Cu Low-k 1 A 2 Low-k 1 Cu t L t 2 Low-k 2 s w s Cu RC = 2 2ρ Cu k ε 1 ol 1 w s + k k 2 1 w s t t2 1. Cu resistivity ρ going up with scaling (due to boundary scattering). 2. Reduction in interconnect dielectric constant k has been slow. 3. Metal width w and space s continue to reduce with scaling. 4. Length L impacted by design/architecture. 8

9 Interconnect Low-k Dielectric Introduction Dielectric k-value ITRS Roadmap for Low-k Interconnect Dielectric 1999 ITRS 2003 ITRS 1997 ITRS 1999 ITRS 2001 ITRS 2003 ITRS Slipping Actual k~ ITRS 1997 ITRS Year of Production Introduction rate for Low-k interconnect dielectrics has been slow and continues to slip 9

10 Reliability Trends with Continued Scaling 10

11 EOT (Å) TDDB Trends for SiO 2 Gate Dielectrics 10.3Å k(sio 2 ) = 3.9 k(si 3 N 4 ) = Å 8.1Å t PHYSICAL = 12Å 7.3Å 6.3Å N (at%) AF (V -1 ) GATE VOLTAGE (Volts) Agere IBM IMEC TI V-¹ FIT N+ GATE +V G e - direct tunneling electrons H 0 H + SiON PWELL Lose bulk SiO 2 properties below 2 mono layers. 12Å t PHYS for manufacturing. S. Tang Apl. Surf. Sci 137 (1998) M. Green JAP (2001) Power Law Model t BD = av G -N AF = N/V G E. Wu IEDM 541 (2000) TI: P. Nicollian IRPS Tut. (2003) interface traps bulk traps TI: P. Nicollian IEDM (2005) Gate Oxide Integrity Controlled Through: Extensive TDDB testing carefully recording: Hard Breakdown, Soft- Breakdown and Stress-Induced Leakage Current Continual validation of power-law model with a complete physics understanding, e.g., roles of hydrogen species: H 0 and H + Carefully avoiding over-voltage conditions in designs and use conditions Ramped to breakdown testing for each wafer lot using skew and outlier statistical analysis for control 11

12 J V fb +1) (A/cm 2 ) TDDB Trends for High-k Dielectrics High-k Leakage Trends nmoscap HfSiON pmoscap HfSiON NMOS SiO 2 Trendline nmoscap HfON TI: Shanware: IEDM, 939 ( 2003). Reduced Leakage EOT (Å) High-k Gate Dielectric Summary: Leakage generally 2-3 decades lower versus same equivalent oxide thickness Breakdown strength E BD generally decreases with k. Have to be careful with too aggressive scaling of hgh-k thickness. Field/Voltage Acceleration γ increases with k and should be favorable for burnin reduction/elimination. 12

13 Poly NBTI Trends SiO 2 Eox H 0 H H H0 Silicon Interface State Generation Step 1: Si-H(3eV) + hole Si + H + Step 2: H + + e H 0 Step 3: H 0 + H 0 H 2 (4eV) NBTI Effects Controlled Through: Controlling excessive hydrogen Understanding full statistical NBTIdegradation distribution Determination of critical p-channel speed paths Designing with the NBTI-induced shifts comprehended Product Margin-Testing/Guard- Banding ΔFOSC (%) TI: A. T. Krishnan, IRPS Tutorials Stress1: VDD=2.8V/30mins/105 C -12 Stress2: VDD=2.8V/60mins/105 C Characterization V DD (V) TI: V. Reddy et. al., IRPS

14 VDD (V) Channel Hot-Carrier Trends Vdd reduced with scaling Vdd Trends Vdd held ~ constant Lifetime (Arbitrary) L (nm) L (nm) Channel Hot Carrier (CHC) Injection can degrade transistor parameters CHC Effects Controlled Through: Extensive CHC testing --- complete understanding of voltage, temperature and time-dependence of transistor parametric-degradation Determining the full statistical distribution of CHC degradation Circuit checkers, e.g., determination of critical speed paths Designing with the CHC-induced parametric shifts fully comprehended Product Margin-Testing/Guard-Banding NMOS PMOS CHC Lifetime Trend

15 Silicide Trends Sheet resistance (ohm/sq) Silicon consumption (nm) NiSi CoSi Silicide thickness (nm) NiSi CoSi Sheet resistance (ohms/sq) Ref: Lauwers et al, JVST-B, p.2026, 2001 Leakage (A/cm²) 1.E-07 1.E-08 1.E-09 1.E-10 NiSi Junction depth (nm) CoSi2 Ref: Lauwers et al, JVST-B, p.2026, 2001 Silicide : NiSi PtSi Pd 2 Si Resistivity: (μohm-cm) Sheet resistance for NiSi lower than CoSi 2 For same sheet resistance, average Si consumed is much less with NiSi For similar junction depth, lower junction leakage achieved with NiSi 32nm Silicide Challenges : Maintaining low sheet-resistance plus low junction-leakage a challenge Shallow junctions versus adequate annealing of implant-induced damage Raised source/drains required for low-sheet/low-leakage junctions? 15

16 ESD Trends Common Sources for ESD Damage to Semiconductor Devices: Feature Size IC Process Parameter <1 μm Silicide Impact on ESD robustness Poor thermal resistance Human Body <0.25 um Leff Local channel heating Machines Charged Devices nm 32 nm Tox <40 A FinFET SOI Oxide stress Metal current density Ch. Self-heating Every technology advance has significant impact on ESD design for the IC circuits ESD Controlled Through: Special ESD protection circuits are designed and implemented on chip Understanding and mitigating the impact of processing on ESD circuits ESD Checkers are used to aid designers Extensive ESD and Latchup testing of final product JEDIC standards used for shipping, handling and product use 16

17 Electromigration-Induced Damage in Metal Extrusion e - M e - Voids TI: E. Ogawa, 2001 IEEE-IRPS Tutorial Electromigration (EM) Effects Controlled Through: Interconnect Process-Robustness Extensive EM Testing Current Design Rules Based On: Operating Temp, Duty Cycle, AC vs. DC Operation, Metal Length and Width Considerations Current Density Checkers and Power-Density (Hot-Spot) Analysis 17

18 M2 Cu Stress-Induced Via-Voiding VDP Structure Void Formation Kinetics Relative % of Failing Sites (48 total) OPEN >100% >50% >20% >10% >5% % nm 100 C 150 C 200 C 250 C M1 V1 70% 60% 50% 40% 30% 20% 10% 0% VDP Test Structure 168 hrs 336 hrs 500 hrs 168 hrs 336 hrs 500 hrs Constrained-Cu grain-growth & excess vacancies. Interfacial vacancy diffusion & precipitation. TI: E.Ogawa, et al., : IEEE-IRPS, 312 (2002) 168 hrs 336 hrs 500 hrs 168 hrs 336 hrs 500 hrs Relative Creep Rate SM Model : R ( T where: Creep/Voiding Rate Model N 3.2, Q 0.74 ev, T M-D Equation McPherson & Dunn SM Model 0 T) ΔR > 5%, 168 hrs 190 C N Temperature ( C) Exp( Observed stress-induced Cu via-voiding described McPherson & Dunn Model TI: McPherson & Dunn, J. Vac. Sci. Tech. B, 1321(1987) C T 0 Q ) k T Stress Migration (SM) Effects Controlled Through: Post Cu-deposition anneals, strong capping layer adhesion, and SM bakes Redundant vias needed for wide metal leads Structure/layout dependent via rules for critical vias 18 B

19 Low-k Interconnect Dielectric Trends Time to Failure (Arbitary Unit) OSG(k=2.9) P-MSQ (k=2.4) γ TDDB PETEOS(k=4.2) FSG(k=3.5) SiO TI: E. Ogawa, et al., IRPS 2003 Ebd E (MV/cm) Lower-k silica-based materials generally have lower Ebd and TDDB Lower-k materials generally have lower modulus and lower mechanical strength UV and/or e-beam shown to be effective at increasing strength/hardness Low-k Dielectric Issues Controlled Through: Extensive TDDB, adhesion, cohesion, and crack propagation testing Detailed design rules for minimum-pitch line-lengths Dual ramp-rate breakdown testing (TI: G. Haase, et al., IRPS, 466 (2005) 19

20 Temperature Rise [ C] Interconnect Joule Heating Trends Dielectric Thermal Material Constant Conductivity (mw/ o C-cm) PE-TEOS 4.2 ~ 12 FSG 3.6 ~ 8 OSG 2.8 ~ 5 M4, FSG M3, FSG M2, FSG M4, OSG M3, OSG M2, OSG Current Density [MA/cm2] Joule heating in metal leads becomes an issue for current densities > 1MA/cm 2 and is exacerbated by low-k. 20

21 Defect Detection Trends with Scaling Killing interconnect defects: historically ~ 50% of geometry/space killer defect size Inm) technology nodes (nm) cumulative probability % Actually, today, killing interconnect defects can be atomic/molecular in size breakdown field (MV/cm) Killing Defects are becoming increasingly difficult to resolve physically In some cases, the killing defect can be atomic/molecular in size. Must rely more on electrical versus physical signature. Electrical breakdown and TDDB measurements of interconnect dielectrics have become standard interconnect reliability test. Dual ramp-rate breakdown tests now used to determine true minimum to metal-to-metal spacing for interconnects hundreds of meters long 21 7hr 3hr 1hr Impact of timewindow on ILD breakdown strength

22 Photolithography Issues with Continued Scaling ---What you draw is not exactly what you get Contact pad area loss Asymmetric pitch CD control N3 N4 Constrained gate end loss Information is lost Gate CD flaring near pads/turns 22

23 Lithography fewer tricks remain Various Strategies/Tricks: - Attenuated phase shift (130nm) - Model-Based OPC (130nm) - Alternating phase shift (90nm) - Sub-resolution assist feat.( 65nm) - Restricted design rules (45nm) - Immersion lithography (45nm) 32nm Challenges for Lithography Highly restricted design rules and high-index immersion for lithography Double-exposure at multiple layers Full 3D-electromagnetic litho simulation for RET/OPC 23

24 Reliability Impact of Continued Scaling --- Conclusions MOSFET Scaling --- more evolutionary than revolutionary Transistor I drive Increases --- normally come with increases in I off Strained Si --- offers improved I drive without I off increase SiO 2 Gate Dielectrics (~1.2nm thick) --- very leaky ( A/cm2) High-k Gate Dielectrics --- reduced leakage (~ 1000x for same EOT) High-k Films --- lower Ebd but improved field acceleration γ NBTI --- impact on V min greater due to smaller voltage headroom CHC --- no longer benefiting from Vdd reduction Silicides --- low sheet resistance and low junction leakage at odds ESD --- never seems to get easier Interconnect RC --- starting to dominate circuit performance EM and SM --- likely will require some type of Cu-cladding Joule Heating --- more severe with lower-k Defect Detection --- must rely more on electrical signature Litho-Induced Defects --- RET/OPC becoming increasingly important Summary: More Design Attention will be required for Reliability Assurance 24