DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS. ME498 PV Class. Laboratory Manual on Fundamentals of Solar Cell Manufacturing

Transcription

1 DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS ME498 PV Class Laboratory Manual on Fundamentals of Solar Cell Manufacturing Prepared by Bruno Azeredo, and Dr. Elif Ertekin 9/21/2013 The authors would like to thank James R. Nagel and Michael A. Scarpulla for sharing their manufacturing recipes, class manuals and tutorials with us.

2 Cleaning Cleaning a wafer is perhaps one of the most important steps during micromanufacturing, but it also quite time consuming and not as scientifically relevant. Nevertheless, how do we decide when to clean the wafers and at what stages of the manufacturing process? For the purposes of solar cell manufacturing, the step most prone to contamination is either the oxidation or doping step which occur at elevated temperatures ( C). Any metal contaminant present in the surface of the wafer will diffuse into the wafer at such temperatures and all the electrical properties of semiconducting materials are at jeopardy by such metal impurities. When we receive the case of wafers from the factory, we assume them to be dirty. Even though they are cleaned and the quality of cleanliness depends on the vendor. The first step is to make sure that the wafers have no metal or organic contamination. So we do the following steps: 1. Degrease the wafer with acetone, isopropyl alcohol (IPA), DI water and IPA. This step removes most heavy organic contamination such as oils, finger prints, dust. However, acetone leaves an organic residue of its own on the surface and not always removes all other organic contaminants. 2. So, we deploy a standard cleaning solution that removes all organic contamination called RCA Next, we deploy a cleaning solution that removes surface metal contaminants; it is called RCA Finally, we dip the wafer in HF to remove the native oxide and expose it to air to reform the native oxide. Now, we know that even the native oxide is pure and free of contaminants. 5. This step removes any water that is left behind and it is called the dehydration bake (on a hot plate for 135 C for 3 min. Our wafer is ready to be oxidized and we are sure no contamination is sneaking into the chamber whose temperature will be raised to 1125 C. Oxidation Now that our wafers have been cleaned, the next step is to grow a thin layer of oxide around the edges. This layer will serve as a protective barrier during the phosphorus diffusion process as well as act as an insulator between the top and bottom contacts of the cell. The exact thickness of the barrier itself is not very important, just so long as the oxide is deep enough to serve these ends.

3 We shall therefore specify a target thickness of 0.5 um for the oxide as illustrated in Figure 2. Two types of chemical reaction may be utilized to grow oxide on silicon. The first is called dry oxidation and is governed by the reaction Si (solid) + O2 (gas)! SiO2 (solid) Another useful reaction is called wet oxidation because it occurs in the presence of water vapor. The governing reaction is therefore Si (solid) + 2H2O (gas)! SiO2 (solid) + 2H2 (gas) The primary difference between these reactions is that wet oxidation tends to occur at a much faster rate than dry oxidation. It is also worth noting that these reactions can also occur even in ordinary air at room temperature. The result is a native oxide layer on all silicon wafers that slowly grows thicker over time. Fortunately, the rate of reaction at standard temperature and pressure is extremely slow. Even after several days, the thickness of a native oxide layer will generally saturate at no more than 1-2 nm. Although the exact equations for oxide growth are intricate and complex, is possible to simplify matters by approximating the oxide thickness as a linear function of time. The growth rate itself depends heavily on such factors as ambient temperature, gas flow, and even crystal orientation, but can still be reasonably approximated for our current needs. For example, the growth rate for dry oxidation at 1050 C generally ranges between nm per hour. For wet oxidation, the rate increases can almost reach 500 nm per hour. Consequently, one hour of wet oxidation at 1050 C should be enough to produce the desired thickness for our application. It is also common to pad this value with 5 minutes of dry oxidation both before and after the hour of wet oxidation. The instrument of choice for performing thermal oxidation in the MNMS Cleanroom is the Oxidation Tube furnace. This device is simply a pack of quartz tubes designed to bake wafers at very high temperatures. One tube is specifically set aside for thermal oxidation and is connected to a series of gas flow valves. While owing oxygen through the tube, a standard flow rate that works well is 6.0 SLM (standard liters per minute) for both wet and dry oxidation. Once the oxide growth is complete, we can verify by simply visual inspecting the color of the wafer. For a 500 nm thick oxide, the color of the wafer should have changed from a shiny gray into light green-violet color. Can you think about why the wafer color will change with oxide thickness? What light phenomena

4 learned in class can explain why the thickness of the oxide matters on the color (light wavelength) output of the reflected light? Interference equation for normal incidence of two waves: Charts are also freely available online that give a full spectrum of colors over a wide range of oxide thicknesses. After 12 hours of dry oxidation at 1125 C most wafers will tend to grow between nm of oxide. Due to turbulence of air flow within the furnace, it is also common for wafers on the edge of the quartz boat to exhibit perhaps nm of oxide thickness. This can be partially alleviated through the use of sacrificial wafers at each end of the boat, thereby producing greater uniformity for the test wafers packed between. However, this step is strictly aesthetic since the exact thickness of oxide is not a crucial design parameter. 6. O 2 Oxidation at 1125 C for 12 hrs at an oxygen flow rate of 4 sccm (target thickness = 525 nm). Figure 1: Oxide layer (green/violet) is created on all faces of wafer.

5 On the left, it is a picture of six high temperature tube furnaces, each with a particular purpose to avoid cross contamination between different processes. For example, doping and oxidation is always done at different chambers since we can t guarantee that dopants won t deposit on the interior of the tube furnaces. On the right, I am pulling the wafers out of the chamber, note that they are loaded on a quartz boat and that they look violet from an angled view, this is evidence that the oxide thickness is correct! Doping The next step in our procedure is to etch an opening in the top side of the wafer for phosphorus to pass during diffusion. This is accomplished through the use of a process known as photolithography and requires the use of very dangerous chemicals. Students and TAs alike should therefore take great care to carefully follow safety guidelines during this step. Photolithography can be a complex and tedious process, but is also very powerful at producing precise features in a semiconductor device. The procedure itself is graphically summarized in Figure 3 and expressly detailed below: 7. Spin AZ 1518 using the pipette set at 5 ml, recipe #3, please be diligent on aligning the wafer, dropping the PR in the center of the wafer and removing bubbles after dispensing the PR. 8. Hard bake at 145 C for 10 min with cover and Al ring Figure 2: Hard-baked PR (red) is created on back of the wafer.

6 9. Spin AZ 1518 using the pipette set at 5 ml, recipe #3, please be diligent on aligning the wafer, dropping the PR in the center of the wafer and removing bubbles after dispensing the PR 10. Pre-bake at 110 C for 2 min 11. Degrease mask before using and dry it well 12. Using Mask #1, Flood Exposure around 10 seconds in MNMS (Required dose = 150mJ/cm 2 =Intensity*time) (if the flood exposure reads ~7mW/cm 2, that is usually a mistake and suffices to jiggle the connector while measuring the power) 13. Develop in 4:1 volume ratio of AZ 400K Developer : Di Water for about min, make a large volume of solution (~200mL). Only develop front of the wafer. Quench and rinse sample with DI water always and check features in microscope 14. Hard bake at 145 C for 40 min with cover and Al ring What is really important in the parameters that were selected for this lithographical step is the hard-baking temperature. The hard baking temperature thermally activates cross-linking of the photoresist which is essentially a polymer. The more cross-linking, the more chemically resistant the phoresist becomes to most chemicals as it becomes less permeable to other chemicals. This is the case with the next step where we will be using hydrofluoric acid to attach the oxide layer exposed by the photoresist. The other aspect is that the higher the temperature of the hard-baking step, the larger the thermal stresses induced when the wafer is colled down.

7 15. BHF (5:1)dip for 11min (etch rate from reference: 100nm/min [1]), followed by methanol rinse 16. Remove PR with 1165 PR stripper (talk to miki to define PRs stripper option and time), rinse with IPA (no acetone) Figure 3: an expose Si window on front of the wafer w/ contamination. 17. To remove contamination: O 2 Descum Wafer at 200 W for 1 min each side (use AL ring to avoid back side contact with aluminum). Use clean Al ring! This step helps remove contamination from PR stripping. 18. Take wafer for phosphorous diffusion chamber. Dope the wafer at 925C for 30min approximately. Follow the doping source spec/data sheet. Note that thick oxide layer acts as a blocking layer for diffusion of dopants. Figure 4: n-doped layer (yellow) created in the window with a residual oxide layer ~60nm on n-layer.

8 The top left image shows the oxide layer etched where the PR cracked. The cracking is due to polymer swelling in hydrofluoric acid which attacks the oxide where the cracks were generated. The swelling happens because the PR is not cured at sufficiently high temperature and, thus, not very cross-linked. The top right image shows the exact opposite condition where the PR was overly cured and, although protected the oxide layer during the HF etching, it was impossible to remove it on the subsequent step. The right image shows the result under the right conditions where we have the PR removed and the oxide layer intact where it wasn t exposed. Making Al contacts 19. Spin AZ 1518 using the pipette set at 2.5 ml, recipe #3, please be diligent on aligning the wafer, dropping the PR in the center of the wafer and removing bubbles after dispensing the PR 20. Pre-bake at 110 C for 2 min 21. Degrease mask before using and dry it well 22. Using Mask #1, Flood Exposure around 10 seconds in MNMS (Required dose = 150mJ/cm 2 =Intensity*time) (if the flood exposure reads ~7mW/cm 2, that is usually a mistake and suffices to jiggle the connector while measuring the power). Note that this back step does not need alignment. 23. Develop in 4:1 volume ratio of AZ 400K Developer : Di Water for about min, make a large volume of solution (~200mL). Quench and rinse sample with DI water always and check features in microscope 24. Hard bake at 145 C for 10 min with cover and Al ring Figure 5: a window is created on back PR to expose the oxide. 25. Spin AZ 1518 using the pipette set at 4 ml, recipe #3, please be diligent on aligning the wafer, dropping the PR in the center of the wafer and removing bubbles after dispensing the PR 26. Pre-bake at 110 C for 2 min 27. Degrease mask before using and dry it well

9 28. Using Mask #2, Flood Exposure around 10 seconds in MNMS (Required dose = 150mJ/cm 2 =Intensity*time) (if the flood exposure reads ~7mW/cm 2, that is usually a mistake and suffices to jiggle the connector while measuring the power). Note that alignment is crucial for not shorting the solar cell. 29. Develop in 4:1 volume ratio of AZ 400K Developer : Di Water for about min, make a large volume of solution (~200mL). Quench and rinse sample with DI water always and check features in microscope 30. Hard bake at 145 C for 30 min with cover and Al ring 31. Figure 6: a window is created on front PR to expose the residual oxide. 32. BHF (5:1)dip for 11min (etch rate from reference: 100nm/min [1]), followed by IPA/methanol rinse Figure 7: an window is created on PR to expose the oxide. 33. Spin AZ 1518 using the pipette set at 2.5 ml, recipe #3, please be diligent on aligning the wafer, dropping the PR in the center of the wafer and removing bubbles after dispensing the PR 34. Pre-bake at 110 C for 2 min 35. Degrease mask before using and dry it well 36. Using Mask #3, Flood Exposure around 10 seconds in MNMS (Required dose = 150mJ/cm 2 =Intensity*time) (if the flood exposure reads ~7mW/cm 2, that is usually a mistake and suffices to jiggle the connector while measuring the power). 37. Develop in 4:1 volume ratio of AZ 400K Developer : Di Water for about min, make a large volume of solution (~200mL). Quench and rinse sample with DI water always and check features in microscope Figure 8: top PR defines lines patterns. 38. Sputter 300 nm Al on the back and in the front Figure 9: Aluminum lines are formed.

10 This is the top of the solar cell after being coated by Aluminum. These images show the evolution of the sample during the sonication in acetone step. The sample is immersed in acetone which chemically disolves the photoresist underneath the aluminum layer. This step is also called the lift-off.

11 39. Remove PR in acetone and sonication, rinse with IPA Figure 10: PR has been removed; top and bottom contacts are insulated. The shinny ring and lines are the Aluminum contacts, the green outter ring is the oxide which provides the electrical insulation between the top and bottom of the solar cell, and, finally, the gray area is the collection region (n-type surface). 40. Anneal Al contacts at 400 C for 10 min in Nitrogen/Argon gas. This steps is fundamental to create an alloy between silicon and aluminum that is very thin (<10nm). The annealing steps allows for the metal-semiconductor junction to become ohmic (low resistance) instead of schottky. And we are done for the day!!!

12 Bibliography [1] Kirt R. Williams, "Etch Rates for Micromachining Processing Part II," JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, vol. 12, no. 6, December 2003.