Effect of Leadframe Tape Material on Thin Small Non-Leaded Packages (TSNP) Manufacturing Line

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Effect of Leadframe Tape Material on Thin Small Non-Leaded Packages (TSNP) Manufacturing Line Cheng-Guan Ong Infineon Technologies (Advanced Logic) Sdn. Bhd. Daniel.Ong@infineon.

1 Effect of Leadframe Tape Material on Thin Small Non-Leaded Packages (TSNP) Manufacturing Line Cheng-Guan Ong Infineon Technologies (Advanced Logic) Sdn. Bhd. Wei-Keong Ng Infineon Technologies (Malaysia) Sdn. Bhd. Kian-Pin Queck Infineon Technologies (Malaysia) Sdn. Bhd. Abstract - In Thin Small Non-Leaded Packages (TSNP) design, heat resistance tape (i.e. RT321 and RT321+CD1) were used as leadframe carrier throughout TSNP assembly manufacturing line. These carrier acts as package backbone during molding process and were removed during detape process as to expose Cu pad (2 nd interconnection) before plating process. However, under un-optimized parameter condition in TSNP assembly manufacturing line, the heat resistance tape shows inconsistence performances and contribute high assembly yield losses. The current paper investigates the effect of heat resistance tape on torn tape and excess solder defect in detape and plating process respectively. Torn tape defect occurred during mechanical peeling (remove heat resistance tape as to expose Cu pad). Whereas, excess solder defect were detected after Sn plating process, excess solder defined as x and y pad dimension out of specification based on Infineon Technologies Process Control. The DOE s input factor of Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed) were established with the help of CEDA software. RT321+CD1 tape resulted to be best fit in TSNP manufacturing line compared to RT321 tape due to tape physical properties compatibility. However, at high detape temperature, low plating current and high conveyor speed, performances of RT321 tape are comparable with RT321+CD1. Keywords TSNP, Excess Solder and Heat Resistance Tape I. INTRODUCTION Recently, the increased demand for a QFN package type indicates that QFN meets the requirements for semiconductors used in small gadgets. As worldwide mobility increases, the QFN package type can be made much smaller and thinner than the package type having leads protruding therefrom, reducing the required area on a circuit board by about 40% compared to conventional techniques. The QFN package also has excellent heat dissipation, since the lead frame is on the bottom of the package and, thus, the die pad is directly exposed to the outside [1-3]. One of Infineon Technologies Quad flatpack no-lead (QFN) packages are Thin Small Non-Leaded Packages (TSNP) package. Along with this growth in TSNP demand, semiconductor manufacturers are constantly striving to increase the performance of TSNP while decreasing its cost of manufacture. The cost reduction could be achieved through better assembly technology and the utilization of low-cost materials. Currently, Infineon Technologies is exploring the usage of RT321 and RT321+CD1 heat resistance tape. The heat resistance tape on one side of Cu alloy leadframe is served as temporary structure support for subsequent die attach (i.e. Fig. 1), die-to-package interconnection and mold encapsulation processes. Consequently, the whole heat resistance tape was removed during detape process, revealing all the bottom part of the Cu pads embedded in the mold package. The exposed Cu pads become the pads of the TSNP. For surface finish, conventional Sn plating is performed on the pads to improve solderability, corrosion resistance and mechanical strength. Fig 1. EFTECH-64 Cu alloy grade leadframe with heat resistance tape cross section. The current paper reports on the effect of the heat resistance tape on TSNP Cu pad after detape and Sn plating process. Two process that predominantly influences the heat resistance tape were investigated in terms of their correlation behaviours in respectively process parameter factor. These factors are leadframe heat resistance tape materials, Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed). The final part of the paper relates the differences of both heat resistance tape and the corresponding failure modes. II. EXPERIMENTAL PROCEDURES EFTECH-64 Cu alloy grade with different heat resistance tape (their characteristics compositions are shown in Table I) leadframes acted as temporary structural support in TSNP assembly process. After completing the die attach, the first level interconnection (i.e. wire bonding or flip clip process) and the mold encapsulation processes. The tape were removed using mechanical tape remover in detape machine (brand: FICO). The equipment consist with three main station, namely pre-heat station, peeling station and cooling station. Leadframe were placed on pre-heat station for 15 second at different temperature level (i.e. Table II). Then, leadframe were mechanical transfer to peeling station by 1 st horizontal mechanical pusher. In peeling station, leadframe were placed for 5 second at different temperature level (i.e. Table II). Next, the gripper finger gripped and started peeling from leadframe finger in horizontal direction. Leadframe were cooled down at room temperature for 20

second at detape cooling station before 2 nd horizontal mechanical pusher push leadframe to output station.

In between Cu activation and Sn baths, samples were spray rinsed and spray blowed with deionized water and 25 C dryed air. Lastly plated leadframe were blow dried.

Output response for Table II and Table III are torn tape and excess solder defect respectively.

2 second at detape cooling station before 2 nd horizontal mechanical pusher push leadframe to output station. TABLE I: Characteristics comparison of heat resistance tape of RT321 and RT321+CD1 EFTECH-64 grade Cu alloy Characteristics Heat Resistance Tape [4] RT321 RT321+CD1 Detape Temperature, C Tg, C In conventional Sn plating process (machine brand: MECO), leadframe was placed manual on moving conveyor belt. First, leadframe were dipped into Cu activation bath. Then, leadframe undergo Sn plating bath at different parameter level ( i.e. Table III). In between Cu activation and Sn baths, samples were spray rinsed and spray blowed with deionized water and 25 C dryed air. Lastly plated leadframe were blow dried. After that, visual inspection measurements (i.e. output response) were carried out on these leadframe by using 100 X magnification Olympus microscope. Output response for Table II and Table III are torn tape and excess solder defect respectively. Torn tape defect occurred during mechanical peeling (remove heat resistance tape as to expose Cu pad), whereas, excess solder defect were detected after Sn plating, excess solder defined as x and y pad dimension out of specification based on Infineon Technologies Process Control. Manual visual inspection were obtained for each sample to determine the defect count value. Characterization of excess solder was conducted on defect unit by measuring the x and y axis. These value were input into CEDA software as 2 nd level optimization. Microstructural examinations were conducted by scanning electron microscopy (SEM, 15 kv accelerating voltage, JEOL JSM-6360A) on the TSNP pad s. Next, characterization of both heat resistance tape adhesive strength towards temperature were conducted by DMA 8000 dynamic mechanical analyser. III. RESULTS AND DISCUSSION A. Assembly defect characterization Fig. 2: TSNP manufacturing process flow The full factorial design of experiment (DOE) analysis of the heat resistance tape was performed. In current studies, input factor of Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed) were tabulated in Table II and III respectively, and were established with the help of CEDA software. Fig. 3. Optical image of torn tape on RT321+ CD1 tape after detape process. Magnification scale of 2.0 cm. Fig. 3 shows optical image of torn tape defect after detape process. Torn tape was defined as the left over heat resistance tape on EFTECH-64 Cu alloy leadframe after detape process. TABLE II: Series of Detape parameter factor with levels Factors Units Type Levels Pre-heat Temperature C Numeric 3 Main Temperature C Numeric 3 Peeling Method N/A Category 2 TABLE III: Series of Plating parameter factor with levels Factors Units Type Levels Conveyor Speed m/min Numeric 3 Current A Numeric 3 Loading Method N/A Category 2 Fig. 4. Morphology of Cu pad surface after Sn plating process Left: Cross section of Cu pad with RT321+CD1 tape; Right Cross section of Cu pad withrt321. Under current: 70A and conveyor speed: 2.5 m/min. Magnification scale of 10 µm (Left) and 20 µm (Right).

3 Fig. 4 shows cross section SEM picture of 2 nd interconnection Cu pad after conventional Sn plating, EFTECH-64 Cu alloy surface finishing indicates two surface morphology, RT321+CD1 tape without excess solder and RT321 tape with excess solder. Cu pad with RT321+CD1 shows 5 µm (50 %) Sn plating expension from Cu pad, whereas, Cu pad with RT321 shows 17 µm (170 %) Sn plating expension from Cu pad. Based on Infineon Technology Process Control, 10 µm (i.e. set value) x and y axis of Sn plating expension from Cu pad is defined as good unit and beyond from set value is defined as bad unit. B. DOE Analysis and Optimization for Detape Process. The first stage experiment results model goodness fit as R-squared 97.37% and adjusted R-squared 96.93% at 99% confident level for Detape DOE. Table IV: Term Significant of Detape DOE Respond Torn Tape Count 36 R-Squared Adj. R-Squared RMS Error Interaction test result between heat resistance tape and detape parameter are shown in Fig. 5 and Fig. 6. The torn tape (i.e. Count of defect unit) shows slight positive interaction on both auto and manual detape method. The average optimization of torn tape were predicted at high count of defect unit for both auto and manual detape method. Fig. 5 shows RT321+CD1 tape required low temperature (i.e. main temperature: 195 C and pre-heat temperature 180 C) compared to RT321 tape (i.e. main temperature: 220 C and pre-heat temperature 200 C) under auto detape methodology. However, both heat resistance tape at main and pre-heat temperature shifted by ~5.12 % and ~1.67 % respectively when peeling method switching from auto to manual method. Surprisingly, manual detape able to reproduce low defect count unit, at higher temperature compared to auto detape method. But contribution of inconsistance peeling error during manual detape mehod had significantly generated new defect type (i.e. damage frame) during DOE run. Furthermore, warpage (i.e. coil set 2.5 cm) or frame oxidation defect (i.e. Cu surface turn into purplish-brown colour) on EFTECH-64 Cu alloy leadframe was observed on both heat resistance tape type when leadframe were exposed to high temperature, > 210 C. C. DOE Analysis and Optimization for Plating Process. The first stage experiment results model goodness fit as R-squared %, % and %, and adjusted R- squared %, % and % of excess solder, x- axis and y-axis respectively at 99 % confident level for plating DOE. Table V: Term Significant of Plating DOE. Fig. 5. Torn tape prediction with Auto Detape Method for RT321+CD1 (Green Line), RT321 (Red Line) and Current Parameter (Black Line). Fig. 6. Torn tape prediction with Manual Detape Method for RT321+CD1 (Green Line), RT321 (Red Line) and Current Parameter (Black Line). Respond Excess Solder X-Axis Y-Axis Count R-Squared Adj. R-Squared RMS Error Fig. 7 and 8 shows the prediction graph of RT321+CD1 and RT321 heat resistance tape respectively. Plating parameter optimization of heat resistance tape based on current detape parameter shown in Fig. 5. (i.e. auto peeling method, pre-heat temperature: 180 C and main temperature 210 C). Positive interaction test result between heat resistance tape and plating current or conyevor speed were observed at both 0 and 180 loading method respectively. Under 0 loading methodology, RT321+CD1 optimum plating current and conyevor speed at 70A and 2.5 m/min respectively, whereas as RT321 optimum plating current and conveyor speed at 65A and 2.3 m/min respectively with reverse loading methodology (i.e. 180 ).

4 temperature of the maximum loss modulus or the maximum loss factor. Fig. 7. Excess solder, x and y axis prediction with RT321+CD1 heat resistance tape. Fig. 9. Heat resistanc tape behaviour in storage modulus and loss modulus strength towards temperature. Fig. 8. Excess solder, x and y axis prediction with RT321 heat resistance tape. Small bias and high robustness variable setting are desirable properties to reduce excess solder yield loss in small range within optimal plating parameter at 99 % confident level. Under constant 0 loading methodology, behaviour between heat resistance tape at conveyor speed 2.3 m/min (i.e. RT321) and 2.5 m/min (i.e. RT321+CD1) and between plating current 60A (i.e. RT321) and 70A (i.e. RT321+CD1) respectively indicates not significantly different. On the other hand, under constant conveyor speed: 2.5 m/min and plating current: 70A, a significantly differences between RT321 and RT321+CD1 tape were observed at 0 and 180 loading methodology. D. Comparison between RT321 and RT321+CD1 tape. Based on Fig. 9, RT321+CD1 and RT321 glass transition temperature occurred at 190 C and 200 C respectively. The average loss modulus of RT321+CD1 shows % in MPa during 10 C temperature shifting (i.e. from 180 C to 190 C). Whereas, RT321 shows % MPa reduction when temperature shifted from 200 C to 210 C. Both RT321 and RT321+CD1 tape glass transition temperature from the maximum loss modulus is correlated to storage modulus fairly straightforward. Furthermore, the value agrees well with the temperature given by DMA step evaluation [2-3]. As the temperature increases from 25 C to 180 C, the loss modulus shows increases pattern, whereas, storage modules shows decreases pattern. Above 180 C, the loss modulus increases till maximum peak, then decreases as tape physical properties had changed from glass to rubbery stage (i.e. based on heat resistance tape material properties shows in Table 1). In this stage, tape storage modulus shows minor shifting respected to heat resistance tape adhesive properties. The glass transition temperature is often taken to be the Fig. 10. Heat resistance tape peeling force with different temperature at different traveling distance. Furthermore, peeling force on heat resistance tape shows in Fig. 10 agreed on DMA step evaluation (shown in Fig. 9). A subsequent but gradual increment of peeling force was observed when the distance travel increased from 0 µm to 1000 µm, then the peeling force shows constant value from 1000 µm onwards. However, different behaviour were observed on RT321 tape at 190 C (i.e. yellow line). The rise of peeling force correlated directly with glass transition temperature, suggesting the adhesive strength of tape reduces or poor cohesive. (i.e. Tape physical properties turns from glass to rubbery). Above 190 C, RT321+CD1 peeling force distance reduces by 50 % (i.e 1000 µm to 500 µm) indicates heat resistance tape have reached transition temperature and the tape adhesive strength turn weaker but, EFTECH-64 Cu alloy leadframe turn into purplish-brown colour (i.e. leadframe oxidation). RT321 peeling force against distance travel indicates the tape adhesive strength is stronger than RT321+CD1 at 190 C, An increasing in RT321 tape temperature, the peeling force shows not significantly different (p-value > 0.05). This indicates, RT321 tape glass temperature occurred at 200 C and the peeling force reached maximum stage at 1000 µm distance travel.

5 IV. CONCLUSION The present work compares the RT321 and RT321+CD1 tape by characterized it s behaviour in TSNP manufacturing flow. The following conclusions were made based on the investigation: 1. Optimum auto peeling temperature of RT321 and RT321+CD1 tape recorded at 220 C and 195 C respectively. Whereas, optimum auto peeling for preheat temperature of RT321 and RT321+CD1 tape recorded at 200 C and 180 C respectively. Manual peeling shows low reject performances compared to auto peeling, but others defect were observed when leadframe were exposed to higher temperature, > 210 C. 2. Optimization of Sn plating current and conveyor speed are dependent on heat reistance tape and detape parameter. At optimum detape temperature, both heat resistance tape required specific parameter range in order to achieve minimum defect rate (i.e. excess solder). 3. Asides that, the tape adhesive left over after detape process on EFTECH-64 Cu alloy leadframe shows high reject rate of excess solder defect after plating. Remover of heat resistance tape on Cu pad are solely dependent glass transition temperature. ACKNOWLEDGMENT The authors would like to thanks Infineon Technology (M) Sdn. Bhd. for supporting and sponsor this research. REFERENCES [1] Y.S. Lai, P.H. Chang, C.W. Chang, T.Y. Tsai, S.H. Hung, A. Tseng, K. Takai, and T. Hirashima, Development and Performance Characterization of a QFN/HMT Package, Electronic Components and Technology Conference, pp , [2] C.J. Bill, B. Hu, M. Lin, T. Lin, S. Lee, Y.S Lai, and A. Tseng, Advanced QFN packaging for low cost and solution, In Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), th International Conference on, pp IEEE, [3] W. Wu, F. Qin, C. Gao, W. Zhu, and G. Xia, Thermal fatigue life optimization of QFN package based on Taguchi Method, In Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), th International Conference on, pp IEEE, [4] Hitachi Chemical. Accessed date: 14 May 2018.

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION. Universiti Kebangsaan Malaysia UKM Bangi,Selangor, Malaysia

CONSTRUCTIONAL ANALYSIS FOR QFN STACKED DIE FAILURE IDENTIFICATION W. Shualdi 1, W. M. S. W. Suliman 1, A. Isnin 2 and N. A. Mohamad 2 1 Advanced Semiconductor Packaging (ASPAC) Research Laboratory Universiti