Package Defect Test System and Its Application in Assembly Improvement

Transcription

1 Package Defect Test System and Its Application in Assembly Improvement Shaari Ripin 1, M Mamunur Rashid Mohd Firdaus 1, Gopi Nathan Sathia 1, Xue Ming 1 1 Infineon Technologies Melaka, Malaysia Abstract This paper introduces a package defect test system known as Capacitive Testing setup in assembly manufacturing. Using In-Circuit Test (ICT) design concept from mother board testing was made possible to enhance IC testing by doing package defect testing in the semiconductor industry. It provides simplified open/short test features and added with built-in test feature to detect package structural related defect. Primary focus on such a critical package defect known as near-short condition occurring between neighbouring wires and/or inner leads. This kind of defect is known not able to screen out by x-ray inspection and Automatic Test Equipment testing (ATE). At present, this package defect tester application already running full scale and gained significant results in Quality aspect with zero customer complaints ever since implemented in assembly production. The tester performance had been improved its capacity to achieve productivity improvement with higher OEE%, reduce number of low yield lots with high final test yield and contribute high cost avoidance of assembly spill. This package defect tester can be further benefits to entire customer by cascading in testing wide range of packages in semiconductor industry. b) Typical example of Wire Near short Risk of Early life failure Fig Capacitive Testing Concept This Capacitive Testing concept has been improvised its capability in primary focus the way to screen package structural defect. Current complex packaging technologies with high density wires could be a challenge in testing a product and to eliminate any potential early life failure. (Fig.1) This new test application proven success in screening assembly defects especially for cases like nearshort condition either between Wire to wire, inner leads and vertical sagging wires. This defect is not detected either in X-ray nor Automated Test Equipment (ATE). A comparison between X-ray vs ATE vs Cap Test features in table (Fig. 2) Fig. 2 To understand Capacitive Testing concept can be illustrate further under two different test modes to the package, 1) Basic test structure and 2) Sample Population characterization. For basic test structure, using Keysight VTEP technology developed to apply a capacitive sensing based technique primarily for board level test to detect open solder joint. (Fig.3) a) Package complexity with high wire density Fig. 3 SUB /00/$ SHAARI RIPIN IEEE

2 VTEP -Vectorless Test Enhanced Performance This technology is first established for printed circuit board or mother board level testing in performing a capacitive test measurement concept. A basic capacitor is formed by having two metallic surfaces in near close position will result capacitive coupling behaviour as when apply a small AC signal triggering at one of the surface. This capacitance response can be established its signal level for a structure. Looking into packaging material, the lead frame and the Au or Cu wire bonds within an IC are metallic components. With this new design application by positioning another metallic plate on top of the IC, create a basic capacitor formation between the IC s lead frame and a metallic sensor plate placing above the IC. The IC encapsulation material will behave like a dielectric material between these two plates surface. This test structure enable each pin of the IC to be configured as a capacitor and test measurement carried out without the need of pin biasing the IC under room temperature test. a)unit cap tested failed profile test at pin 78 with outlier signal detected. b)the reject unit verified under X-ray found Wire Near short at pin 78 correlate to Cap test result Fig. 5 Pogo-pin Fig. 4 For device testing, a sensor plate is placed on top of package, and the coupling capacitance between one pin or wire and the sensor plate is measured. (Fig. 4) This capacitive measurement is sensitive to the package structural changes, such as, sagging wire, sweep wire and material changes in the package. Capacitive test is sensitive to package defect, which could be highly associated to field reliability performance vs ATE test is sensitive to electrical performance. This test application is a qualitative testing where the capacitance test signal profile is depending on type of structural package defects detected. a) Typical structural package defects detected using capacitive test method. From a collective sample population characteristic will form a normal population or test limits. During testing mode, any package abnormality will be detect as outlier signal or RED spot in (Fig.5) Capacitive test showed outlier signal spotted at a defective pin. Currently 100% x-ray screening and ATE testing have no capability to detect such structural defect resulted high risk of escapee to customer. Looking into key features between ATE vs Capacitive Test showed cap test concept has the advantages and ability to screen gross assembly defect related to wire & lead frame defects. (Fig.6) b) Test feature comparison between ATE vs Capacitive test methodology. Fig.6

3 2.0 CAPACITIVE TEST OPERATION Cap test operation can be further visualise as shown below illustration which is similar concept to ATE test handler operation and test binning. (Fig. 7) Basically all test measurement data from baseline sample population are auto calculated and analyse statistically by test system for each test socket. Fig. 8 a) Capacitive test operation steps b) Test binning table The actual lot testing can start upon baseline procedure completion. In full lot testing, every piece of units will be tested and test measurement data is plotted against the baseline test limits. The unit is tested passed if the actual test value is within the test limits. But consider failed if the test value spotted as outlier which beyond the High/Low test limits. Baseline test run can be performed one time either based on individual lot basis or a batch of lots from same Wirebond machine platform. If Wirebond output response in stability performance then can allow single baseline setup for many lot testing. (Fig. 9) The test limits, Low Limit /High Limit represent by blue lines. The red line represent the test value measured for device under test. Outlier spike represent in red marker. mv c) Output display of 1 test cycle for tested Good units Fig. 7 In production lot testing, 1 st procedure to run Baseline test ( predefine test limits by device/package ) prior to run a complete lot testing. The baseline test run is to define the test limits for every pin of a specific device / package based on learning characteristic from sample population. (Fig. 8) Baseline test run will capture each unit wire profile test measure from minimum sample population size of 240 pcs of singulated units. Each unit may have some test signal profile pattern or capacitance measurement variation depending on type machines used in Wirebond and Mold processes the lot is built. Capacitive testing is a real time testing of running a lot and some batches of lots could produce either lower or higher test measurement. Within each batch of IC, an outlier is spotted as a spike or abnormality pin detected versus good pin test measurement value define from sample population characteristic. Pin No. Fig. 9 In summary, baseline setup is mandotary to establish clean and accurate test profile limits before lot starts full testing. This can be achieved by performing X-ray on the sample group of units in order to exclude any defective unit during baseline test setup. 3.0 PACKAGE DEFECT DETECTION Below are some examples of capacitive test capability in detecting on various type of structural package defects in production lot testing. This allow fast defect detection and improvement drive in assembly process. Plus an enabler for effective test screening for complex Wirebond package and provide Firewall for field reliability failures. Thus, zero defect escapee.

4 Case 1: Defect Wire Sagged Down Case 3: Defect Wire Near Short 1a. The unit failed Bin5 profile test and detected Outlier signal at multiple pins 3a. Cap test detect low yield lots failed Bin5 at pin 81. X-ray found near short wire between failed pin 81 and power pin. 3b. Action : WB team to realign power bar wedge bond position away from wire pin 81. Case 4: Defect Wire Short to Power Bar 1b. X-ray found Wire sag down observed at the multiple pins which correlate to cap test detection. 4a. Cap test detect low yield lots failed Bin5 at pin 114 & 115. X-ray found wire failed pins shorted to power bar. 4b. Action : WB team to redefine normal wire to power bar gap clearance requirement in safe release procedure. Case 5: Defect Lead Frame Residue Case 2: Defect Inner Lead Planarity 2a. The unit failed Bin5 profile and detected Outlier signal at pin 1 5a. Cap test detect low yield lot failed Bin5 at pin 127 to 129. X-ray found foreign residue at the defective pins. 5b. EDX analysis confirm high Ag (Silver) material from lead frame loose particle. Case 6: Defect Wrong Wire Bonding Good unit Bad unit 2b. X-ray found inner lead in offset position at tilted angle view. Good unit Bad unit 6a. Cap test detect low yield lot failed Bin6 short at pin 23 & 24. 6b. X-ray found defective pin with wrong wire bonding to Gnd pin

5 Table 1. Summary of Capacitive Test coverage vs assembly package defect. Capacitive testing added in assembly process enable to achieve product quality stability, improve device delivery and high test yield performance. In final test finishing site also motivated to have higher final test yield, reduces number of low yield lots and optimize final test flow by eliminating room test flow. By implementing this benefits test handler excess capacity. Capacitive test step added in assembly flow showed success trending in product yield stability eg. Copper wire product showed yield loss reduce significantly (a ramp up package, from 32% to 1%. (Fig.11) Significant assembly quality improvement as overall capacitive test lot rejection rate (LRR) in reduction trend. (Fig.12) Capacitive Test : Product Lot Test Yield Trend Fig. 11 Table ASSEMBLY PROCESS IMPROVEMENT This package defect test system been applied widely to QFP package portfolio. This ensure high quality fully tested product and reliability package deliver to customer. With full scale implementation, allow gaining high product test yield stability at 99.7% and yield loss at minimum level ~ 0.2%. (Fig.10) Fig.12 With fully automated test system and high throughput enable faster defect screening on 100% lot testing compare to x-ray screening. Thus enable to gain faster cycle time in assembly product delivery. Allow easy traceability of problematic Wirebond machine for immediate lot containment and thorough machine healthy check for rectification. (Fig.13) a) Product test stability with consistent high test yield b) Product yield loss at minimum level Fig. 10 Fig.13

6 In short, with capacitive testing implemented in assembly manufacturing area allows : Establish strong test capability in detecting assembly package defect by testing 100% test coverage for wide range of QFP packages portfolio. Success in detecting wide coverage of package defect in assembly lots versus doing screening by x-ray or ATE. This leads to zero quality spill and zero customer complaints related to assembly package defect escapee. For final test finishing Reduction number of trip lot or abnormal lot tested resulted higher final test yield improvement in Backend process. 7.0 ACKNOWLEDGEMENTS Authors would like to express high gratitude for great support in running high volume lot testing and achieving line stability by the production team under Irwan, Arif and Gopal and QFP EOL Maintenance team members. 8.0 REFERENCES [1] Xue Ming, Koelz Johann, Lee Chow York, Lee Kwan Wee, Shi Zhi Min, Electrical Package Defect Testing for Volume Production, International Test Conference 2015, Paper12.1 [2] Xue Ming, Shaari Ripin, The first Electrical Package Defect Test System and its application in assembly improvement, SEMICON Southeast Asia 2016 [3] Medalist ivtep Intelligent Vectorless Test EP, Keysight Technology, Oct ATE Final testing achieved consistent higher Test Yield increase by 0.5% with minimum losses related to Assembly O/S rejects. Test Finishing area gain excess tester capacity by removal Room temp test flow from 3 temperature test steps down to 2 test steps. 5.0 LIMITATIONS The limitation of Package Defect Test System for volume production with capacitive measurement approach, and VTEP technology is not full test coverage for the power lines, and have a lower sensitivity for multiple wire interconnections. 6.0 CONCLUSIONS This Capacitive Testing methodology has been proven with > 100 million parts tested for package QFP. The prime focus in detecting package structural defect screening in fully automated testing is proven. This new test methodology is proven its capability to screen out defects (e.g. near-short at Wire-wire and inner leads, vertical sagging wires) which were not detectable either through electrical testing performed by conventional ATE (Automated Test Equipment) or X-ray. This paper reported result with proven effective in providing package defect, such as wire and lead frame defects screening in volume production for high pin count QFP packages. Fast assembly feedback and improvement, 100% automated screening and recommended to apply for package defect testing in manufacturing process of IC component has been demonstrated. Capacitive Test Performance : - Cover wide QFP package portfolio, >100mio tested - Capable for High density multi-tiers wires, > 200 wires - Use in testing complex Package technology - High machine throughput, UPH 4000 in parallel test - Specialize in detecting assembly structural defect - Machine capacity, >400k - Machine OEE%, >80% - Final Test Yield %, > 99.7% - 1st Pass Yield %, > 95% - Baseline Setup Losses, >5%