Resistive Random Access Memory (ReRAM): A Metal Oxide Memory Cell

Transcription

1 Resistive Random Access Memory (ReRAM): A Metal Oxide Memory Cell Hiro Akinaga and Hisashi Shima Abstract We review the recent progress in the ReRAM technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. We first provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2x-nm generation of nonvolatile memories and the so-called beyond-cmos device. Index terms Electrochemical devices, Metal-insulator-metal devices, Nonvolatile memories, Resistance switching I. INTRODUCTION Resistance switching is an essential physical effect in the ReRAM operation. The resistance switching effect has been studied for more than 40 years. As an introduction to this review paper, a historical overview of the academic researches on ReRAM is provided below. Large negative resistance was first observed in the current-voltage (I-V) characteristics of five metal-oxide-metal (MOM) structures: SiOx, Al2O3, Ta2O5, ZrO2, and TiO2 [1]. A peak-to-valley ratio of 30 was achieved, and the switching time was evaluated to be less than 0.5 μs. The author had already reported the general occurrence of the negative resistance effect in an MOM structure, even though the mechanism was not described in the report. The possible mechanism was reported in the study of NiO, where the switching was believed to be due to the formation and rupture of a nickel metallic filament in a NiO thin film sandwiched between two electrodes. This is the first report on the so-called filament model (see section III). The pioneering study discussing the possibility of using this resistance switching for a memory application was reported in 1967 [3, 4]. The results showed the fast switching of the resistance in an Al/SiOx/Au structure. It was concluded from the experimental results that the ionic process, namely the filament formation and

2 rupture, was not responsible for the resistance switching, but that it came from an electronic effect. The resistance switching in oxide materials was reviewed in 1970 [5]. Various properties of resistance switching and models to explain the experimental results are described in this review paper. A comparison with the Ovshinsky device is also presented in this paper. The Ovshinsky device is a bistable memory device consisting of chalcogenide glasses and is currently called phase-change RAM. Two important features were pointed out in their study. The first was the speed of the switching in oxide materials. The study showed that the speed is of the order of microseconds. This is probably due to unipolar switching, which will be discussed in detail in the next section. The second feature is the thickness dependence of the switching voltage. The switching voltage did not show a clear dependence on the oxide thickness, although the resistance switching was considered at that time to be the result of a bulk change in the filament or oxide film. This discussion will be continued in section III of this paper. The possibility of a high-density memory array application was also described, and interestingly, the similarity between the atomic rearrangement in an MOM structure and the electrochemically induced axon coupling in a synaptic junction was speculated. Even though many studies have been conducted on nonvolatile memory from the 1960s to the beginning of the 21 st century [5, 6], there has been practical application until the first report on the ReRAM array in Zhuang et al. fabricated a 64-bit perovskite-oxide-based ReRAM memory array, using a 0.5-μm CMOS process [7]. In 2004, the fabrication of binary transition-metal-oxide based ReRAM was reported by a group from the Samsung Advanced Institute of Technology, as shown in Fig.1. They successfully demonstrated the ReRAM operation below 3 V and 2 ma, 10 6 set/reset operations, and reading cycles [8]. It is well known that the scaling merit of flash memory will enable it to be the main player in the nonvolatile memory technology because of its potential high-density data storage applications, at least until the 2X-nm generation [9]. However, beyond the 2X-nm generation, the scaling merit will not be useful, not for technical reasons, which can be overcome by engineering developments, but because of physical phenomena. Due to degradation such as leakage current the endurance of flash memories will decrease. We cannot expect fast nanosecond-level operations from flash memory because of the intrinsic limit in terms of the write operation. We have to develop high-density nonvolatile memory with high-speed operation for the sustainable development of our society supported by information and communication technologies (ICT). Here, it should be noted that high-speed and low-power operations are two sides of the same coin. ReRAM, which is based on binary

3 metal oxides, will be the best candidate to meet these requirements. In this paper, the recent progress in ReRAM technologies is introduced in section II, together with issues related to the oxide materials. The key mechanism of the ReRAM operation, which consists of a metal oxide, is described in section III. Section IV discusses the difficult challenges facing the practical application of the ReRAM technology for realizing next-generation high-density nonvolatile memory. A novel application will also be mentioned in this section. Finally, the study is concluded in section V. II. TECHNOLOGICAL OVERVIEW Why is ReRAM the best candidate for the beyond-2x-nm generation of nonvolatile memories? The biggest advantage of ReRAM technology is its good compatibility with CMOS technologies. Much of our knowledge about current semiconductor technologies can be applicable to the development of ReRAM. Furthermore, as will be discussed below, the scaling merit will work in terms of the low-power consumption of the ReRAM operation. These issues will bring a strong cost competitiveness to ReRAM. In this section, we will show these technological advantages and the characteristics of ReRAM, together with the epoch-making achievements reported in previous studies. Two operation modes and the technical terminology for ReRAM are shown in Fig. 2. Fig. 2 also shows unipolar and bipolar operations of CoO-based ReRAM with a bottom electrode of Pt and a top electrode consisting of Ti/Pt [10]. By changing the thickness of the Ti, it is possible to change the stable operation mode of the ReRAM device. In the case of Fig. 2(a), after the first voltage application up to about 2.3 V, the high resistance state (HRS) of the as-prepared device changes to a low resistance state (LRS). This process is called forming and is considered to be the soft breakdown of the MOM structure. The LRS changes to the HRS by a voltage sweep in the same direction as forming. A sudden current drop is observed at around 0.5 V. This process is called reset. The HRS that appeared can be changed again to an LRS by applying a voltage of approximately 1.2 V, as shown in the figure. This process is called Set. Now, the ReRAM device starts to show a nonvolatile resistance change when the reset and set processes are alternated. Note that the voltage required for the forming process shows a linear relationship with the oxide layer thickness. The forming voltage will decrease with a decrease in the thickness. In the bipolar operation, the reset and set processes are achieved by applying the voltage in opposite directions, as shown in Fig. 2(b). The detailed operation mechanism will be shown in section III.

4 A. Material issues The resistance switching phenomena have been observed not only in metal oxides but also in various types of materials, such as group VI and III-V semiconductors (in many cases, the switching is volatile, namely the so-called threshold type) and organic compounds [11, 12]. In this article, however, we will focus on the switching observed in binary metal oxide based materials. Table 1 lists the binary metal oxides that have shown nonvolatile resistance switching in the last 6 years [13-57]. This table shows that nonvolatile resistance switching is widely observed in various types of oxides. From the viewpoint of the material choice, the advantage of ReRAM is evident. It is possible to fabricate MOM structures easily by using the oxides widely used in the current semiconductor technologies. Low-current ReRAM operation was reported in the CuOx-based MOM structure. The CuOx layer was grown by the thermal oxidation of the 0.18-μm Cu via [17, 19]. NiO and CoO are being intensively studied as oxide materials for ReRAM, and these transition metal elements are also used in metal silicides employed as gate materials [15, 16, 27-39]. Recently, the good scaling feasibility of ReRAM was demonstrated in an HfOx-based memory with a cell size of 30 nm [24]. The devices in a 1-kbit array exhibited a high device yield (~100%) and robust cycling endurance (>10 6 ) with a pulse width of 40 ns. The memory cell consisted of a TiN/Ti/HfOx/TiN structure. Here, the Ti overlayer played the role of oxygen gettering for better ReRAM operation. The gettering effect has already been investigated in HfOx as a high-k material for the gate dielectric films in CMOS devices [58, 59]. The academic and technological knowledge about high-k materials will be very useful in the design of the stacking structure for a ReRAM device. B. Memory cell designs Shown in Fig. 3 are the schematically illustrated examples of the memory cell design for ReRAM. Basically, the memory cell consists of the bottom electrode (BE), top electrode (TE), and the oxide layer between those electrodes. Figure 3(a) is a widely used MOM structure where the ReRAM cell is fabricated on the metallic via structure [8]. In this case, the material for BE can be different from that for via. In the ReRAM cell structure shown in Fig. 3(b), the metallic via acts as BE [60]. When the via size is smaller than the TE area, the cell size can be decreased by reducing the via diameter and any oxide layers can be deposited on the via structure. In order to simplify the ReRAM fabrication process, the oxidation of the via material is effective, as shown in Fig.3 (c). Although the range of the oxide material choice becomes narrow, an excellent resistance switching has been reported in this structure with CuOx [17, 19] and WOx [49,

5 50] resistance switching layer. In both cases, the oxidation process of Cu and W plugs is, respectively, introduced in order to fabricate the oxide layer for the resistance switching. The ReRAM cell in Fig. 3(d) has a concave structure of the insulating layer. By decreasing the concave area, the memory cell size can be scaled down. The resistance switching in this concave structure has been reported with NiO [61], TiOx [48] and HfOx [24] resistance switching layers. In the case of TiOx ReRAM, the comparison of the resistance switching performance depending on the memory cell structure, cross-bar type and via-hole type devices, has been carried out [62]. The cross-point structure is shown in Fig. 3(e) [63]. In this case, the memory cell size can be determined by the width of BE and TE wires. In any structures, the multi-layered memory cell stacking can be adapted. C. Process issues In the past, due to analogies from ferroelectric RAM, many groups frequently used Pt as the electrode in a ReRAM device [15, 23, 27, 28, 43, 55]. A Pt electrode can be easily fabricated by the sputtering deposition method. However, it has the following disadvantages: high cost of material and the low vapor pressure in the etching process. To enhance the etching ratio, a high substrate temperature is required even in the reactive etching process. A high substrate temperature is also necessary to avoid residual products on the MOM structure. More seriously, these issues decrease the process margin, degrading the scalability. However, the present understanding is that a Pt electrode is not necessary, could be even detrimental, for the stable ReRAM operation. Oxygen ions penetrate through the Pt electrode, which causes the ReRAM operation, and especially the reset operation, to be incomplete after a certain number of write and erase cycles (see section III). Oxide materials are relatively robust in fabrication processes, while the investigation of high-k materials has shown the importance of oxygen control. The properties of oxide materials, such as the resistivity, are drastically changed by the oxygen concentration. This is an advantage of oxide materials and makes it crucial to control the partial oxygen pressure in their deposition process. The precise control of the metal/oxide interface is also an issue for the development. Any unintentional oxygen diffusion from the oxide memory element to the metal electrode and the passivation (insulating) layer should be avoided. Recently, technical improvements to control the oxygen distribution have been reported. For example, an engineered barrier with AlOx at the cathode interface improved the read disturb immunity [24]. In contrast to a diffusion barrier, diffusion control by the oxygen gettering effect of the inserted Ti layer against

6 HfOx was used to control the forming voltage. D. Memory operations This section will show the best characteristics of ReRAM operations up to the present date. The pioneering study of binary-oxide-based ReRAM reported nonvolatile memory operations, which were comparable to those of NOR flash memory. Operation below 3 V and 2 ma with 10 6 set/reset operations and reading cycles was confirmed (see Table 1). The problems were slow reset operation in the unipolar mode and the relatively large reset current. The endurance, or number of set/reset cycles, was increased to a value greater than 10 9 (Ref. 40). The same group demonstrated sufficient retention exceeding 10 years at 85 C. Recently, a retention test at 150 C predicted a 10-year lifetime for a ReRAM cell consisting of HfOx (Ref. 24). So far, in our experiments, the ReRAM cell has shown stable resistance switching in the bipolar mode, rather than the unipolar mode. The switching speed of the reset operation possesses a tendency to be higher in the bipolar mode and lower in the unipolar mode, in a case where both modes were tested using an identical memory cell structure. As seen in Table 1, however, even in the unipolar mode, the current ReRAM cell can be operated by a voltage pulse faster than 100 ns [18, 38]. It should be noted that the resistance switching is considered to be much faster than the cell operation. The pulse width for stable switching is determined not only by the intrinsic switching speed of the ReRAM cell but also by the LC components of the circuit. The process integration for a 128-kbit memory array has been demonstrated in a ReRAM cell with a stacking structure of TiN/CoOx/Ta. Fig. 4 shows a cross-sectional view of a 1T1R memory cell structure and a microphotograph of the 128-kbit ReRAM chip. In this chip, the program state (LRS) and the erase state (HRS) were normally read out by confirming the output signal from the voltage sense amplifier in accordance with the sense enable (SE) signal. An improvement in the resistance distribution at the program state by optimizing the applied voltage to the word line and utilizing the verification operation was also reported in this study. E. Simulations A simulation technique allows us to determine useful and concrete properties in an investigation of the physical phenomena in a nanometer-sized device. Several studies have been devoted to understanding the unipolar operation of ReRAM [31, 42]. The three-dimensional heat distribution in a ReRAM cell was calculated using finite element analysis. With some practical parameters, a heat simulation showed the

7 possibility that the temperature of a nm 3 memory element will reach approximately 900 K, and strongly depends on the thickness of the electrode contacting the cell. This is because the heat dissipation from the memory element is changed by the electrode thickness. We also simulated the time development of the heat distribution using three-dimensional meshed finite difference modeling (DeviceMeister-LP, Mizuho Information & Research Institute, Inc.). Our simulation confirmed that in the MOM structure of a Ta/CoOx /metal electrode, the temperature increased to the same order as that reported by other groups [31]. It was also shown that the maximum temperature in the distribution was strongly dependant on the size of the memory cell, and more surprisingly, the temperature reached the maximum within 10 ps after the voltage pulse was applied to the MOM structure (not shown in this paper). To understand the macroscopic behavior of the unipolar switching, the random circuit breaker network model [42] was proposed, as shown in Fig.5, where each circuit breaker has one of two possible resistance values, where one is the high resistance and the other is the low resistance of the nonvolatile switching. The model recreated the I-V curvature in the ReRAM operation. The on-state network appeared by the percolating cluster growth as an avalanche process, and then the reset process occurred in the network where the breakdown was triggered. The scaling behaviors of the reset voltages and currents in the unipolar switching were also explained by an analogy to percolation theory. III. MECHANISM OF ReRAM Several studies have been conducted to elucidate the origin of the resistance switching of ReRAM. The proposed mechanisms can be classified into two models: the filament model and the interface model. In this section, we first show the representative achievements supporting the filament model. Then, we describe the interface model with the experimental evidence. Finally, we show that the filament model will merge with the interface model in the beyond-2x-nm generation. The experimental achievements of previous studies on both these models will be useful when we proceed with the R&D of the ReRAM technology. A. Filament model As mentioned in section I, the filament model was first proposed in Our previous studies using ReRAM-like MOM stacking structures supported the filament picture of

8 the nonvolatile resistance switching. The electrode area dependence in the order of micrometers (60 60~ μm 2 ) and the oxide thickness dependence in the order of nanometers (40~120 nm) on the I-V characteristics were investigated [17]. The results showed that the current flowed uniformly in the OFF state, while in the ON state the current was localized. In addition, the set and reset voltages did not depend on the thickness of the oxide. These facts evidenced that the set and reset switching was associated with the homogeneous/inhomogeneous transition of the current distribution. Namely, the electric faucet turns ON and OFF at the high-resistance interface to regulate the current flow in the filament conduction path between two electrodes. Performing more physical observations, e.g., by conductive atomic force microscopy (cafm), the evidence of the formation and rupture of conducting channels was provided with a high spatial resolution [35, 42, 44]. By applying the external voltage to the cafm tip as the top electrode, the nonvolatile resistance switching operations of forming, reset, and set were triggered, the conducting spots appeared in the forming and set processes, and the locally distributed conducting regions disappeared after the reset process, as shown in Fig.6. Note that the diameter of the conducting spots was typically approximately 3 10 nm after the forming operation with a bias of 8.0 V. Reductions in the switching power and the switching speed for small cell sizes were observed in the range of 10 2 ~10 10 nm 2 (Ref. 35). This is considered to be due to the reduction in the number of filaments and thinner filaments for a smaller electrode size. In the same report, a high-resolution transmission electron microscopy (HR-TEM) image of the NiO layer showed the fabrication of nanofilament nickel channels across two electrodes through the grain boundaries of the insulating NiO matrix. B. Interface model In the binary-metal oxides discussed in this paper, the large resistance switching is brought about by changing the deficiencies, in other words, the oxidation state of the memory element. The contribution of the electrochemical reaction was implied by the fact that the resistance switching took place on the anodic side of the conductive filaments in NiO [28]. One can easily understand the change in the oxidation state by the analogy of anodic oxidation. The redox reaction was evidenced optically in the Fe-O based ReRAM [22]. Raman microspectroscopy on the lateral device and 4-electrode transport measurements revealed that the resistance switching could be explained as a redox reaction between Fe3O4 and Fe2O3 at the interface near the anode. The evidence for the redox reaction at the electrode interface in a Pt/TaOx/Pt memory cell was confirmed by hard X-ray photoemission spectroscopy (HX-PES) [40]. Fig. 7

9 shows Ta 4d HX-PES spectra of a TaOx large-area test vehicle. The spectra clearly show the correspondence of the reduced TaOx component to the change in the resistance state. Wei et al. claimed that the resistance switching occurred upon changing the barrier height between the anode and TaOx, caused by the redox reaction. The interface layer included Ta2O5 δ and TaO2-β. In the reset operation, by applying a positive voltage pulse to the anode electrode, O 2- ions migrated and the oxidization reaction of the TaO2-β and O 2- led to the formation of Ta2O5 δ. Increasing the Ta2O5 δ component enlarged the band gap and increased the Schottky barrier height at the interface. For the set operation, the reduction reaction of the Ta2O5 δ by applying the negative voltage pulse on the anode electrode decreased the Schottky barrier height. C. Unified model of ReRAM operation The above-mentioned filament and interface models are widely used as irreconcilable mechanisms of the ReRAM operation. However, by considering the resistance switching mechanism with the size of the memory cell, the discrepancy will disappear. Consequently, Fig. 8 can be an explanation of the unified model for ReRAM operation. In our sputtering conditions, the as-prepared oxide layer shows HRS. Before starting the repeated nonvolatile resistance switching, the soft-breakdown of the MOM structure is required. This process is called forming. LRS appears after the forming process. In a submicrometer memory cell, for example, the forming process will bring about a filamentary low-resistance conductive path between the top and bottom electrodes. Here, we assume that the external voltage is driven at Ta TE and the forming process is carried out by applying the positive voltage. In this case, during the forming process, the conductive state expands from the cathodic BE interface and finally reaches the anodic TE interface, followed by an increase in the interfacial TaOx layer thickness. This expansion of the conductive state is possibly explained as the reduction reaction of CoO, i.e., the O 2 - ion deprivation due to their migration to the positively biased anodic Ta TE. The remaining conductive state expanding from the cathodic electrode is thus called the virtual cathode, which act as the electrode opposite to the Ta TE in the subsequent reset and set processes. In the reset operation, when the negative voltage pulse is applied at TE, the repulsive force makes O 2- ions migrate from TaOx to CoOx. In this case, the TaOx layer can be regarded as the oxygen supplier and CoOx is oxidized. Consequently, the CoOx layer is transformed from the conductive state to the insulating state. On the other hand, in the set operation, when the positive voltage pulse is applied at TE, O 2- ions again migrate from the bulk CoOx to TaOx. The TaOx layer during this set operation is assumed to be an oxygen reservoir, yielding the

10 reducing transformation from the insulating CoOx to the conductive state. It should be mentioned that the TaOx layer acts not only as the oxygen supplier but also as the oxygen reservoir, depending on the polarity of the applied voltage. A layer with high oxygen affinity prevents oxygen diffusion into the metal electrode during the repeated resistance switching operations, serving the objectives of a stable ReRAM operation. How large is the size of the faucet of the filamentary conductance path? Actually, the size depends on the currents for the forming and set processes (see below), but will be in the range of 10~30 nm for realistic operation currents. The size is comparable to the memory cell size in the beyond-2x-nm generation. When a ReRAM cell is prepared with a cell size smaller than 30 nm, the ReRAM operation model can be redrawn as shown in Fig. 9. The operation is exactly explained by the interface model. In the generation of a 2X-nm node, the filament and interface models will be unified. The interface model clearly shows that the preservation and supply of O 2- ions by the interfacial layer are caused by a type of electrochemical reaction at the interface; these processes are believed to be promoted by the electric field gradient. Thus, the switching mode changes to bipolar switching because the migrating species are charged. The assistance of the Joule heating accelerates the switching cooperatively to the electric field, where the diffusion constant is exponentially increased under such conditions. In contrast, in some cases the Joule heating contributes the resistance switching competitively to the electric field, yielding unipolar switching. In addition to the electric field gradient, the composition gradient can promote the O 2- ion migration. More specifically, the concentration of O 2- ions in the conductive part is much lower than the matrix area of the oxide layer and/or the interfacial layer. Therefore, because of the temperature rise due to the Joule heating, O 2- ions can migrate in order to suppress the concentration gradient, causing the reset process even though the polarity of the reset voltage is identical to that of the set voltage. However, the oxygen-affinitive electrode materials may disturb this unipolar switching because the chemical bonding between these electrode materials and the O 2- ions is enhanced by the temperature rise. In this case, the extraction of O 2- ions from the interfacial layer to the conductive part in the oxide layer should be accomplished by the negative voltage application to the oxygen-affinitive electrodes, resulting in bipolar switching. Several previous papers have pointed out effective ways to decrease the operation current. For instance, the load resistor and embedded transistor used to regulate excessive current flow during the swing into LRS effectively lower the operation current. In addition, a reduction in the parasitic capacitance component is essential in order to precisely control the resistance in LRS, i.e., the operation current during the reset

11 process. Such current regulation corresponds to controlling the degree of progress with respect to the reduction reaction during the reset operation and the number and/or total area of the conductive regions in the oxide layer. This is the great advantage of the ReRAM technology. We can control the size of the faucet, the size of the conductance path, and can expect a lower power operation with a smaller ReRAM device. A smaller ReRAM cell is definitely better in terms of a smaller switching power. This is not trivial but empirically indicates that a ReRAM cell requiring less switching power will show a higher switching speed. The merit of scaling is evidenced. In addition, in view of the randomness inherent in the filamentary conduction path formation, the miniaturizing of a ReRAM cell is expected to decrease the operation current by excluding candidate sites for the extra paths. In order to lower the operation voltage, it is essential to decrease the forming voltage. Fortunately, in various oxide thin films, the forming voltage can be decreased with the film thickness. Finally, the forming voltage can be comparable to the set voltage and the forming process becomes unnecessary. Here again, we can point out the advantage of downsizing in the thickness direction, which leads to the improvement in the ReRAM operational performance. The redistribution of charged species such as the oxygen ions in the oxide is closely related to the space charges. When nanoscale analyzing techniques for the charges accumulated at the interfacial region are developed, a further understanding of the presumed space charge redistribution corresponding to the resistance switching will be acquired. The detection of the thermally stimulated current (TSC) signal and deep level transient spectra (DLTS) from the nanoscale region in the ReRAM device is also expected to lead to a more precise perception of the interfacial electronic states. The detection of the imperceptible current and capacitance signals with a sufficiently fast time response, such as subnanosecond order resolution, is obviously indispensable for the development of nanofabricated electronic devices, including ReRAM. IV. CHALLENGES As described above, ReRAM is the most promising candidate for the next-generation of nonvolatile memory because of its simple structure, high switching speed, and high scalability. This high scalability is ensured by the fact that the present CMOS technologies are applicable to the technologies for ReRAM. Due to the scaling and the operation-speed limit of conventional flash memory devices, ReRAM will appear in the 2X-nm generation to replace some of the functionalities of flash memory devices,

12 especially for memory applications requiring a fast operation and medium size storage density. However, the potential of ReRAM is not limited to the replacement of flash memories. In this section, we will discuss the challenges facing the ReRAM technologies. A. Integration and reliability The potential of the ReRAM device has already reached the practical application level. The critical requirements for the next few years are related to integration and reliability issues. From the viewpoint of material processing, we have to address the urgent priorities of controlling the oxidization of the metal during the thin film growth. The know-how for the processing of high-k materials will help with the development of growth techniques. Uniform growth will certainly be required, but this issue will not be as serous in the direction perpendicular to the film plane, because only the interface between the oxide layer and the metal electrode plays a crucial role in the ReRAM operation. Compared to a case where the oxide layer plays the role of a tunneling barrier, thickness fluctuations will not directly affect the resistance fluctuation. Developments are urgently required to investigate the reliability. At the device level, we have to develop an acceleration test for operation failure. It is crucial to develop a test procedure to quantitatively evaluate the relationship between the degradation of the device and external parameters such as the temperature of the device and the number of read/write cycles. We must also develop techniques to understand the failure of a ReRAM device. For example, a transmission electron microscope with an electron energy-loss spectroscopy function will be a powerful tool to investigate the interface properties between the metal electrode and the oxide layer. High-spatial-resolution characterization of the heterointerface by scanning probe microscopy technique such as scanning spreading resistance microscopy must be utilized to investigate a nanoscale memory device [64]. It should be noted that the ON/OFF ratio of the resistance state is very large as compared to other emerging nonvolatile memories such as spin-transfer-torque RAM and phase-change RAM. Furthermore, the capacitance of the MOM structure certainly affects the fast operation of the ReRAM device. Designing circuits, for example a TEG design for robust signal sensing, will also be an important assignment in the ReRAM technologies. B. Unipolar switching Since one of the main targets of ReRAM applications is a high-capacity memory, the 1D1R operation must be achieved. Thus, the ReRAM should be operated in the

13 unipolar mode. The need for a unipolar ReRAM cell forces us to prepare a diode with high nonlinearity and a high forward current. A possible solution is to decrease the cell size. The mechanism described in section III shows that a smaller memory cell requires a lower operation current, thus achieving faster switching. On the other hand, the current technologies have not yet realized fast, low-power, and stable operation simultaneously, even in a single ReRAM device. For example, the reset process in the unipolar operation requires higher current than is needed for bipolar operation. This is considered to be caused by the fact that the thermal effect plays a certain role in the unipolar reset process, as described in section III. The thermal management inside and outside of a memory cell will be the biggest challenge to overcome to realize a high-density 1D1R ReRAM array. To investigate the thermal properties in a heterostructure consisting of metal and (semiconducting) insulator layers, a thermoreflectance method that uses a picosecond laser pulse will be useful [65]. At present, only the one-dimensional heat diffusion across a heterostructure with a well-defined layer thickness can be investigated, rather than in two or three dimensional directions. We have to push the limit of the current leading-edge metrology, especially for the nanoscale measurement of the thermal properties of solid-state electronic devices. C. Further improvement of memory performance As described in section II-D, the endurance of the ReRAM device has reached 10 9 (Ref. 40). This number, however, is not sufficiently large to allow the ReRAM device to replace DRAM. Since the switching speed is sufficiently fast for DRAM replacement and the material and process used for ReRAM are very similar to those of the DRAM capacitor, the endurance improvement is certainly one of the biggest challenges as a long-term objective. The key requirement is a method to control the oxygen movement at the interface between the electrode and the oxide layer. Inserting a second metal layer at the interface would solve the problem. The inserted metal should be easily oxidized as an oxygen reservoir compared to the metallic element of the resistance-change oxide layer to prevent oxygen from penetrating into the electrode during the resistance switching. The precise electrochemical design of the interface is certainly required for the development. The forming process will be dropped out in the ReRAM technology, simply because the forming voltage can be linearly decreased with a decrease in the thickness of the oxide layer. More practically, the resistance of the reset state in future ReRAM devices with a smaller cell size will increase. Therefore, by using an oxide layer with lower

14 resistance, such as TiO2 with the oxygen deficits, it will be possible to start the operation from the reset in the ReRAM device with the low resistance as the initial state. Actually, by controlling the TiOx deposition process, the resistance switching without the forming process was confirmed in the Pt/TiOx/Pt ReRAM. More recently, several forming-less ReRAM operations have been reported in WOx [50] and NiO ReRAMs [66]. In the former, by optimizing the oxidizing condition of W plugs, the obtained WOx ReRAM could be in the LRS in the pristine state. In addition, excellent resistance switching properties such as switching cycle endurance and retention characteristics were reported. In the latter NiO ReRAMs, the thermal formation of the filamentary conduction path instead of the electrical forming process was confirmed. Kawai et al. pointed out that the thermal formation of the filament led to the electrical forming-less operation of the ReRAM. As discussed above, the precise control of the resistance in the LRS by using an external current regulator requires a relatively large resistance in the initial state. A control technology for the resistance of the pristine LRS is quite essential in order to realize a forming-less operation with low power consumption and sufficient reliability with respect to the operational voltage and current uniformity. The effective memory cell area of ReRAM is expected to be smaller than 4F 2, where F is the feature size in the semiconductor technology node. There are two possible solutions on how to reduce the memory cell area: multibit storage operation and multi stack memory cell structure. With the benefit of a large ON/OFF ratio for the resistance switching, multibit storage becomes one of the things expected in ReRAM. In a ReRAM device with a Pt/TiO2/TiN stacking structure, data writing for five-level resistance states was demonstrated by varying the amplitude of 5-ns voltage pulses [67]. The retention characteristic evaluated at 85 C showed no degradation at least up to 256 hours. This multibit storage is also confirmed in the other ReRAMs using WOx [50] and HfOx [68]. The multi-stack structure of ReRAM has been demonstrated in the 1D1R configuration [69]. In this case, NiO was used in the memory cell and the p-n diode consisted of p-cuo/n-inzno. This technology is based on the very simple memory cell structure of ReRAM. As pointed out in this literature, in order to establish the multi-stack ReRAM technology, it is necessary to develop the rectifier in order to prevent the leakage current path in the memory cell array. The compatibility with the memory cell miniaturization in terms of the forward current density will become an important measure [69, 70]. In addition to the oxide p-n diode, the MIM structure showing the threshold type resistance switching can be applicable as the access controlling resistor. For instance, the Pt/VOx/Pt resistor in series with

15 Pt/NiO/Pt ReRAM cell showed a successful demonstration of the resistance switching by the 10 ns programming pulse [71]. Compared with the 1T1R configuration, it is clear that the 1D1R configuration give rise to the smaller the memory cell area. Thus, the improvement of the device performance in these diode and resistor for the 1D1R technology is expected to consolidate the advantage of ReRAM with respect to the ultrahigh density integration and the further down scaling of the memory cell area. It should also be noted that the above 1D1R memory array was successfully integrated at room temperature. Because of this low process temperature of ReRAM, this non-volatile memory technology is thought to be applicable in many areas of electronics. For practical operation, resistance states for the cell that are very high or very low resistance states prevent scaling, because a larger transistor or diode may be needed. To make the distribution narrower at each level, the precise control of the electrochemical reaction in the ReRAM cell is certainly required. Decreasing the real-space movement of oxygen ions, for example, the transition from one special position with a local energy minimum to others, or the reconfiguration of the oxygen bonding, will be the ultimate feature of oxide-based ReRAM technology. D. Other potential applications In addition to high-density electronic applications, in the area of large-area electronic applications, the oxide-based ReRAM technology may help to make possible the realization of flexible and transparent nonvolatile memory. Since some of the oxide materials possess a wide bandgap, combining these oxides with thin metal electrodes or transparent electrodes will create candidates for such flexible and transparent ReRAM devices. Actually, nonvolatile resistance switching was reported in the indium tin oxide (ITO)/ZnO/ITO stacking structure [51, 52]. It is surely worth investigating the integration with a transparent thin film transistor. If we can forget about deterministic and digital information processing, the role of ReRAM will be much more important. An analog resistance change has been observed in some metal/insulator heterointerface structures exactly like the stacking structure of ReRAM. For instance, the Pt/TiOx/Pt memristor was proposed [72-75], where charged oxygen vacancies were regarded as a mobile dopant in the semiconducting oxide and the electrical control of the vacancies was utilized to gradually change the resistance of the device. The state variable can be regarded as the distribution of the oxygen vacancies in this beyond-cmos device. Forty years after the first projection regarding the similarity between the resistance switching in a metal/oxide junction and the axon coupling in a synaptic junction [5], we have finally succeeded in developing a solid-state

16 electronic device to replicate the functions of the human brain. Since oblivion is necessary for our brain, the novel ReRAM-like device may gradually forget the stored information. V. SUMMARY We have reviewed the progress of the ReRAM technologies. Although the basic studies on resistance switching failed to produce a realistic application for more than 30 years, an increasing number of R&D-based studies on ReRAM application have been carried out in the last decade. Their impact will bring about a synergy between logic- and memory-based semiconductor technologies. These studies are expected to redefine use of the ReRAM technology, allowing it to be used not only for high-density data storage applications but also for high-performance embedded memory and storage class memory applications. The basic material studies have shown that the electrochemical effect plays a role in the ReRAM operation. It is easy to discern that the reset operation has a close relationship with the elementary process taking place in a solid oxide fuel cell and an oxide-based solar cell. In the area of functional oxide electronics, interdisciplinary research is becoming extremely important and will lead the development of so-called more-than-moore research areas. We invite you to join this exciting emerging field.

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25 Figure captions Table 1 Various binary metal oxide materials utilized in ReRAM devices. TE and BE represent the top and bottom electrodes sandwiching the oxide layer, respectively. U and B letters of the alphabet in the table show the uni- and bi-polar operations of the ReRAM device. Fig. 1 (a) Cross-sectional TEM image of fully integrated ReRAM cell array and the corresponding schematic diagram. (b) Pulse dependent switching behavior with 5μs/l00ns reset pulses and 10 ns set pulses. Courtesy: Dr. U-In Chung, Samsung Advanced Institute of Technology. Fig. 2 (a) Unipolar and (b) bipolar operations of CoO-based ReRAM with the bottom electrode of Pt and the top electrode consisting of Ti / Pt. The voltage sweep is done by the top electrode drive. Fig. 3 (a) Typical MOM simple stacking structure of ReRAM. (b) The memory cell on the metallic via as a bottom electrode with oxide and top electrode layers. (c) The oxidized via material for the resistance switching oxide layer. (d) The concave structure for ReRAM. (e) The cross-bar structure consisting of the bottom and top electrode wires and oxide blanket. Fig. 4 (a) Cross sectional view of 1T1R memory cell structure. (b) Microphotograph of 128 Kbit RRAM chip. (c) The architecture of the 1T1R memory array. (d) Measured waveform of sensing operation for the memory cell. RAS and CAS represent Row Address Strobe and Column Address Strobe, respectively. Fig. 5 Proposed circuit breaker configurations in the random circuit breaker (RCB) networks. (a) Schematic diagram of the RCB network composed of circuit breakers. (b) Detailed operations with switchable bistable states of circuit breakers. (c) Pristine state with a few circuit breakers in the on-state. (d) The low resistance state with a percolating cluster of circuit breakers in the on-state formed between the top and bottom electrodes. (e) The high resistance state with a broken link; an off-state circuit breaker switched from the on-state. (f) The configurations after the 4th, 5th, 6th, and 7th iterations during the forming operation show that the percolating cluster growth occurs as an avalanche

26 process. These snapshots also indicate that the growth has a preferred direction, parallel to the applied electric field [42]. Fig. 6 Conductive AFM measurements (C-AFM) on TiO2 films. (a) Schematic diagram of the C-AFM measurements. (b) The I V curves using the conducting AFM tip as a top electrode, clearly show the forming, Reset, and Set operations. (c) Mapping of the current flow through the surface just after the forming operation with 8 V shows locally distributed conducting regions. d) After the Reset operation with 1 V, the TiO2 surface in the HRS state shows that the locally distributed conducting regions disappear [42]. Fig. 7 Ta 4d HX-PES spectra of TaOx large area test vehicle. The height of the reduced TaOx component corresponds to the change of the resistance state, the low resistance state (LRS), the high resistance state (HRS) and the initial state showing the highest resistance state. Courtesy: Dr. Hiroshi Kumigashira, The University of Tokyo Fig. 8 Filamentary model for the ReRAM operation. Note that the size of the memory cell shown in this schematic image is the order of 100 nm. Fig. 9 Unified model for the ReRAM operation. Note that the size of the memory cell shown in this schematic image is the order of 10 nm, smaller than the size of the faucet of the filamentary conductance path shown in Fig. 7.

27 Oxide Thickne ss BE Material TE Material Operatio n Mode Table 1 Device Size Operation Current Operation Voltage Operation Speed Endurance Retention Remarks Ref Al2O3 20 nm Pt Ti B 250 μm φ 20 ~ 50 ma ~ -2.0 V (reset), 2 ~ 7 V (set) DC NS NS 13 Al2O3 2 nm Pt (Word line) CoO, NiO 50 nm Pt Pt U CoO 50 nm Pt, Ta Pt, Ta B CoO, Fe2O3, NiO 4 ~ 120 nm Pt Pt Pt, W(probe) U U 500 nm 500 nm μm 2 ~ μm μm 2 ~ μm 2 10 (W needle), 60, 100, and 200 μm φ ~ 1mA DC, pulse (4.5 V) 70ns NS NS 1D1R, CuO/InZnOx diode ~ 10 ma ~ 6 V (forming) DC NS NS ~ 10 ma -13 V (DC forming), pulse (-3.0 and +3.5 V/20ns for Pt/CoO/Ta) Cu2O 12 nm Cu Ni, Co U 0.18 μm φ ~ 0.1 ma ~ 3 V (DC set) CuxO NS Cu Al, Pt, Ti B μm 2 ~ 10 ma 4.5 V (DC forming) Cu2O 6 ~ 8 nm Cu Ni, Co, Ti, and Ta U/B 180 nm φ (Cu plug size) DC, pulse (20ns) Data up to 100 NS 16 5 ~ 10 ma DC DC NS NS 17 < 40 μa for Ti TE, < 100 μa for Ni TE (DC) DC, pulse (100 ns ~ 1000 μs) DC, pulse (+3V/1μs, -1V/1ms) NS NS (PtTE) NS Endurance more than 10 4 for AlTE DC, pulse < 3 V DC, pulse (100ns) NS NS 1T1R 20 FeOx 100 nm Pt Pt CVS μm 2 < 20 ma Constant voltage stress (CVS) CVS NS NS 21 FeOx, Zn:FeOx HfO2, SiO2, TiO2 HfOx 100 nm Pt Pt B NS < 5 ma NS Pt Pt U cm 2 ~ 10 ma 5, 10 nm TiN, TiN/AlOx MgO 1.2 nm CoFeB CoFeB U TiN B 30nmφ ~10-5 cm 2 < 0.3 ma nm 2, nm 2, nm 2 Pulse (-3.0V/1ms for forming, +2.0V/10~100ns for set, -2.2V/10~100ns for reset) HfOx(Vr = 1~1.8V, Vs = 3 ~ 4 V), TiO2(Vr = 0.6 ~ 0.7 V, Vs = 2 ~ 3 V), SiO2(Vr = 8 ~ 9 V, Vs = 9 ~ 15 V) 1T1R (DC: ±1.5V, pulse: 1.5 ~ 2.3 V) MnO2 80 nm Pt Ti B 120 μm φ ~ 30 ma -1V (reset), +0.9V (set) Pulse (10 ~ 100ns) More than Data up to 1000 h at 85 C for Zn:FeOx DC NS NS 23 DC, pulse (40-100ns) ~ 10 ma < 2 V DC Data up to 400 DC, pulse (±1.5V, 10ms) More than 10 5 Data up to 10 5 sec at 150 C At least 88 h at 85 C At least 10 4 s at 80 C T1R 24 NiO 100 nm Pt Pt U 300 μm φ 2 ~ 23 ma ~ 2 V (set) DC NS NS NiO 60 nm Pt Pt U 200 μm φ ~ 20 ma ~ 1.5 V (set) DC NS data at 250 C 28 NiO 30 nm Pt, SrRuO3 Pt, CaRuO3 U/B μm 2 ~ 20 ma < 5 V DC Over 200 NiO NS Pt Pt U 0.25 μm 2 ~ 1mA 3.5 ~ 5 V DC NS NS NiO 60 nm Pt Pt U μm 2 ~ 20 ma ~ 2 V (set) DC NS NS NiO 40 nm Pt Pt, Ta, Al, Mo, Ag, Cu, PtTi NiO NS Pt, SrRuO3 Pt U/B 100 μm φ More than 3000 s at RT Epitaxial NiO 29 Filament observation Heat dissipation U μm 2 1 ~ 10 ma ~ 5 V (set) DC NS NS 32 ~ 40 ma (PtBE), ~ 5mA (SRO-BE) ~ 1.8 V (SRO-BE, reset) DC NS NS 33 NiO NS Pt Pt U μm 2 2 ~ 70 ma 5 V (forming) DC NS NS NiO 10 nm Pt Pt U (0.1 μm) 2 ~ (50 μm) 2 NiO 10 nm Pt Pt U (0.7 μm) ma ~ 10mA (Pt/NiO/Pt), 10-3 ma (CAFM) < 20 μa (0.36 μm G-width T) ~ 1.5 V (Pt/NiO/Pt, set), 2 ~ 3.5 V (CAFM) < 2 V (DC), < 2.5 V (pulse) DC, pulse (1.0V/10ns for reset) DC, pulse (1.2V/100 ns for reset, 2.5V/100 ns for set) NiO 40 nm Ni Ni, TiN U 10 μm 2 < 50 μa 1 ~ 2 V for forming DC NS NiO and Ti:NiO 8 nm Pt Pt U 0.49 μm 2 < 100 μa DC, pulse < 3 V 1.8V/5ns for reset, 2.8V/10ns for set NS Data up to 100 Data up to 100 NS At least 1000 h at 150 C Data up to 10 4 s at 150 C Data up to 1000 h at 150 C Switching energy scaling T1R 38 Ti:NiO NS NS NS U μm 2 1 ~ 10 ma DC < 4 V DC 1000 NS TaOx 30 nm Pt TiO2/Ta2O5 3/10 nm Ru(Ti), TiN, Ti, Ru, Pt Ti, Al, Ta, Ni, W, Cu, Ag, Ir, Au, Pt B μm 2, 2 2 μm 2, 4 20 μm 2 < 200 μa (pulse voltage sweep) < 2.0 V (pulse) 10 ~ 100 ns 10 9 Data up to 3000 h at 150 C 1D1R, CuO/InZnOx diode 39 1T1R 40 Ru B NS ~ 100 μa 5 ~ 6 V for forming DC 10 6 (DC) NS 1T1R 41 TiO2 NS Pt Pt U NS ~ 10 ma 3 ~ 4 V (forming), 1 ~ 2 V (set), ~ 0.5 V (reset) DC NS NS Random circuit breaker network model TiO2 43 nm Pt Pt U 300 μm φ 32 ~ 82 ma 1.5 ~ 2.9 V (set) DC NS NS 43 TiO2 TiO2 20 ~ 57 nm 27 nm Ru Pt, Al U(PtTE), (AlTE) 300 μm φ ~ 100 A/cm 2 ~ 70 ma 2.0 ~ 2.5 V (set, 57 nm TiO2) DC NS Data up to 10 days at RT ~ 1mA (B), -1.6 ~ + 1.1V (BRS), 2 ~ 3V(URS, Pt Pt U/B 200 μm φ 30 ~ 50 ma(u) set) DC NS NS 45 TiOx NS Pt Pt U/B TiOx 10 nm Al Al B 1 1 μm 2 < 20 ma (U), DC 3 ~ 4V for set (URS), DC -2.5 V (cross point) < 5 ma (B) for reset and +1.5 V for set in BRS μm 2 (cross point) DC NS NS 46 < 3 ma DC ±3 V DC NS NS 47 < 2 V (triangular voltage sweep), TiOx NS TiN Pt U NS < 5 ma -1.8V/50ns for set and +2.2V/50ns for reset DC, pulse (50ns) Data up to 14 NS 48 (BRS), +4.5V/50ns for set (URS) WOx NS W TiN U/B WOx NS W TiN B 170 nm φ DC < 2.0 V, pulse < 3.1V DC, < 10 ma Data up to 100 NS Multi level 49 (Via size) (50 ~ 100 ns) pulse (50 ~ 100ns) ~ 0.07 μm 2 (Via size) ZnO 100 nm ITO ITO U 500 μm φ ZnO 50 nm ITO/Ag/IT O 3.5V/80ns for forming, 2.4V/80ns NS for reset, 1.2V/80ns for set Pulse (80ns) Data up to 900 NS 50 ~ 20 ma 3.2 V (forming) DC At least 100 At least 10 5 s at RT Transparent V (forming), 0.6 V (reset), Data up to 10 5 at Transparent ITO U NS ~ 3 ma 1.5 V (set) DC Data up to 200 RT, 10 4 at 85 C and flexible 52 About 3.3 V for forming, ZnO 100 nm Pt Pt U 220 μm φ < 6 ma DC Data up to 100 NS 53 ~ ±2V for set, ~ ±1 V for reset ZnO 30 nm TiN Pt B 100 ~ DC (±1.2 V), pulse (4V/ <10ns for μm 2 < 6 ma set, -4V/ >40ns for reset) DC, pulse NS NS 54 ZrO2 130 nm Pt Pt U 300 μm φ ~ 10 ma 1.4 V (reset), 8.9 V (set) DC 10 5 NS ~ 70 Ti, ~ 30 ma ZrO2 nm Pt W(probe) U/B 250 μm φ (B, TiTE) -3.0V (reset), +2.0V (set) in BRS DC NS NS 56 DC, pulse (1.5V/1μs for More than Data more than ZrO2 20 nm Pt TiN B μm 2 < 1 ma -2 V (reset), +1.5 V (set) set, -2.0V/1μs for reset) sec at RT 57

28 Fig. 1 Akinaga

29 Fig. 2 Akinaga

30 (a) (b) (c) (d) (e) Fig. 3 Akinaga

31 Fig. 4 Akinaga

32 Fig. 5 Akinaga

33 Fig. 6 Akinaga

34 Fig. 7 Akinaga

35 Fig. 8 Akinaga

36 Fig. 9 Akinaga