inemi BFR-Free Free PCB Material Evaluation Project Chair : Stephen Tisdale Intel Corporation SMTAi Presentation August 21, 2008

Transcription

1 inemi BFR-Free Free PCB Material Evaluation Project Chair : Stephen Tisdale Intel Corporation SMTAi Presentation August 21,

2 Co-Authors Gary B. Long Intel Corporation Hillsboro, OR Dr. Kostas Papathomas, Ph.D. Endicott Interconnect Endicott, NY Roger Krabbenhoft IBM Corporation Rochester, MN Terry Fischer Hitachi Chemical Beacon Falls, CT 1

3 Thrust Area: Energy & Environment TIG: Environmentally Conscious Electronics & Substrates inemi BFR-Free PCB Material Evaluation Project Project Members Phase 2 Start: Web-site: 2

4 inemi BFR-Free Free PCB Material Evaluation Project Overall Project Objectives: Build on industry knowledge and capability Consider unique market segment requirements Identify technology readiness and gaps Stimulate supply capability Recommend standards development opportunities Anticipated Outcome: Define electrical requirements based on market segment application Validate electrical and mechanical properties Loss tangent and Dk modeling over required range of signal speed Mechanical performance validation for lead free assembly Validate material supplier and PCB manufacturer infrastructure capability Estimate costs volume market leader for new material may not achieve cost parity with best-in-class FR4 3

5 inemi BFR-Free Free PCB Material Evaluation Project IS / IS NOT This Project IS: Technical evaluation of key electrical and mechanical properties Focused on those attributes of most value to supply chain Build on learning from prior investigations Recommendations for standards development or further investigation Focused on circuit board materials This Project IS NOT: An EHS assessment Biased towards specific laminate suppliers, geographies, or market segments Repeat of prior work Standard Development Focused on assembly or board / component reliability characterizations 4

6 3 Phased Approach 5

7 Phase 1: Design Goal: Review prior work and make recommendations for testing needed. Investigation should take into account the needs of electronic product sectors represented by inemi membership. Identify market segment requirements Identify candidate materials (sync with EPA) Identify key performance characteristics and test criteria Design test vehicle(s) and test methodologies, leverage standards where possible 6

8 Identify Key Performance Characteristics and Test Criteria Proposed Test Strategy Screening of Materials Evaluation of electrical, physical, and thermal properties of commercially available Bromine-free laminate materials. Materials passing the initial screen will go to Phase II, which is building of test vehicles to evaluate other material properties. (see next slide) Determination of propensity for failure (i.e., delamination, via fatigue degradation) in a Pb-free process environment on a perapplication basis Thinner / less thermally massive boards up to 245 C (4-10 layer) More thermally massive boards up to 260 C. (12 24 layer) Third party lab evaluates boards per IPC 6012B Class 2 (if deemed necessary) Current HVM and Pb-free Assembly Capability Were Required 7

9 inemi BRF- Free PCB Material Project Product Style Resin Content (%) Resin Flow (%) Gel Time (Sec) Volatile Content (%) Material A Material B Material C Material D Material E Material F < 0.8 Material G Material H Material I Material J Material K NA Halogen free Prepreg properties as reported by suppliers

10 inemi BRF- Free PCB Material Project Optical microscopy and electron EDS used for analysis. Representative photographs for some of the materials. Fillers that are used as the source of flame retardance are composed of Al, Si, & Mg inorganic compounds. The inorganic filler content ranges were found to be 1-32% by weight. Material A Material C P based flame retardants the source could be either reactive phosphorous organic components or particulates. Material F Material B Typical filler types for Bromine free materials

11 inemi BRF- Free PCB Material Project Prepreg & Laminate properties evaluation Prepregs: All prepregs tested consisted of 1080 style, were tack free and of good quality Resin content ranges 64-70% Flow 32-50% Gel time sec Glass transition temperature of prepregs C Minimum viscosity Pa.s / relatively low minimums Temperature of viscosity minimum C Inorganic Filler content 1-32 %» Type Si, Al, Mg, P based compounds» Filler Shape and EDS spectra for elemental Laminates: Electricals ( cursory look) Majority have Dk Df is in the range of 0.01XX Glass Transition temperature (DSC mid pt) C, majority in the 150C range Thermal decomposition Temperature (5% wt loss) All laminates above 330C T260 / w Cu Time ranges 18 - > 120 min (test was terminated after 120 min) BE-67G, S1165 in the low range T300 / w Cu Range nearly 0 - > 120 min (majority 0-26 min) Significant Filler Content Does Not Impact Rheology 10

12 inemi BRF- Free PCB Material Project Prepreg & Laminate properties evaluation Laminates: Moisture absorption Room Temperature / 24 hr relatively low absorption» With Materials B, D and J <0.20% PCT / 1hr Materials B, D and J < 0.7% ; others >= 1.4% PCT rating / 8 hrs exposure followed by 15 sec /500F dip Fail : Materials C, D, E, I & K Pass: Materials A, B, F, G, H & J Copper Adhesion / Gould 1 Oz. JTCS Good adhesion observed Materials B, F & K >= 8 lbs/in Interlaminate Adhesion ~ 3lbs/in Materials F & K being the highest (4-5 lbs/in) Material B samples not tested/cut the wrong direct not enough samples to redo Oxide Interlaminate and 90 deg adhesion (Bond Film) Typical 2-3 lbs/in Material F > 4 lbs/in Thermal Expansion x-y < Tg ppm/c ( a bit high due to high resin content) x-y > Tg ppm/c z < Tg ppm/c ( 32 is rather low needs to be verified) Z > Tg ppm/c (normal ranges) Flammability Appear to be UL94-V0 Good Thermal Stability, Comparable Moisture Absorption, Slightly Lower CTE-Z and No Impact of Filler on Adhesion 11

13 Moisture PCT Vs. Laminate 12 Moisture - 1 hr PCT (%) Material A Material H Material G Material B Material K Material F Material C Material D Material E Material I Material J Moisture RT Vs. Laminate Materials PCT results Material A 9/9 pass Material H 6/6 pass Material G 7/8 pass Material B 8/8 pass Material K 5/9 pass Material F 10/10 pass Material C 0/6 pass Material D 2/10 pass 8 hrs 4 hrs Material E 3/5 pass 4/4 pass Moisture - 24 hr RT (%) Material I 0/10 pass 4/8 pass Material J 10/10 pass 8/8 pass Material A Material H Material G Material B Material K Material F Material C Material D Material E Material I Material J RT Moisture Characteristics relatively low at < 0.35% with some < 0.2%

14 Phase 2: Test Goal: Develop, manage, and execute performance testing. Develop evaluation schedule Procure parts and test vehicles Assign teams to carry out completion of the testing in a standardized fashion. Perform mechanical and reliability testing on test vehicles. 13

15 Identify Key Performance Characteristics and Test Criteria Proposed Test Strategy Electrical Evaluation (< 20GHz) Dielectric Constant (1MHz / 1GHz / 10GHz / Higher?) Dissipation Factor (1MHz / 1GHz / 10GHz / Higher?) Surface Insulation Resistance (before solder mask) Dielectric Voltage Breakdown (Dielectric Withstanding) Mechanical Evaluation Tg T-260 / T-288 Cross Sections Line width & spacing Hole to Pad Registration Peel Strength Bend Test Reliability CAF / IST / HATS Shock / Drop (based on market segment requirements?) 14

16 inemi BRF- Free PCB Material Project SMASPP Test Status/Results The laminate material electrical properties were evaluated using the Short Pulse Propagation (SPP) technique. This technique is currently in the review/release process, IPC D24b task group This technique outputs frequency dependant dielectric constant (D k ) and dielectric loss (loss tangent, D f ) over the frequency range supported by the test equipment. In this case, the data is valid between 10KHz 20GHz. The effective laminate losses ( effective D f ) output is a combination of laminate material losses and those Cu skin effects which are due to the roughness of the Cu foil. Both must be accounted for in performance analysis. Skin effects associated with smooth Cu foil are separated out. Uses the SMASPP2z Test Vehicle Design Eight (8) Layer Test Vehicle, ~ 40 mils Thick Cores & Prepreg Were Matched For D k and Resin Content Within Each of Two Stripline Structures Resin Poor Structure and Resin Rich Structure. Allows One To Assess Full Range Of Expected D k & D f For Each Laminate Dk / Df Measurements Determined by the SPP Technique 15

17 inemi BRF- Free PCB Material Project MSA / Pb-free Solder Process Compatibility Testing IBM SMASPP2z Electrical Test Vehicle 8 Layer Design Resin Rich Stripline Layer Resin Poor Stripline Layer 5 x 11 (6up per panel) Extract Dk and Df from 10KHz to 20GHz Using Short Pulse Propagation Technique Provides Time Domain Broadband Assessment of Laminate Material Dielectric Constant and Loss Tangent 16

18 inemi BRF- Free PCB Material Project MSA / Pb-free Solder Process Compatibility Testing Uses the HOP31B Test Vehicle Shown at Right 40 mil / 80 mil Thick Design Point Same as MEBII test board Mixed Solder Assembly (MSA) Process Peak Temp, 245 o C Full Pb-free Assembly Process Peak Temp, 260 o C Test Vehicle Assesses Basic Compatibility With Higher Reflow Temperatures 17

19 inemi Halogen-Free PCB Project Intel Materials Evaluation Board MEB II Flexible design Multiple layer count and thicknesses capable Designed for 18 x24 panel (16.5x22.5 useable area) 4 Quadrants 4 Sub-panels Some coupons have breakaway tabs Focus on material property evaluation Board level reliability coupons Electrical, mechanical, thermal property coupons Minimal fabrication capability (trace/space coupons) Minimal assembly testing MEB II allows testing of electrical, thermal, mechanical, and reliability performance Basic Design Parameters Current Project 10 layers, structure Minimum Through hole drill = 10 mils Minimum Microvia = 5 mils Minimum buried via drill = 10 mils Minimum Trace and space plated layer = 3/3 Minimum Trace and space 0.5 oz inner layer = 3/3 Minimum Trace and space 1 oz inner layer = 4/4 Plate to IPC Class 2 Build at 2 thicknesses: 1mm and 2mm

20 Phase 3: Results Goal: Compile results, assess significance, make recommendations, and publish report. Assess performance relative to market segment requirements. Assess technology readiness / identify gaps Assess manufacturing capability and supply capacity Publish results 19

21 inemi BRF- Free PCB Material Project SMASPP Test Status / Results Effective Dielectric Constant Results, Before and After Reflow Simulations Effective Dk* HF Laminate Resin Content Rich/Poor 1GHz Dk 5GHz Dk 10GHz Dk 20GHz Dk Material A Rich, 66% (control) Poor, 55% Material B Rich, 70% Poor, 53% Material C Rich, 73% Poor, 53% Material D Rich, 73% Poor, 53% Material E Rich, 73% Poor, 53% Material F Rich, 73% Poor, 53% Material G Rich, 73% Poor, 53% Material H Rich, 73% Poor, 53% Material I Rich, 70% Poor, 51% Material J Rich, 70% Poor, 51% Material K Rich, 67% Poor, 53% Before Reflow Effective Dk HF Laminate Resin Content Rich/Poor 1GHz Dk 5GHz Dk 10GHz Dk 20GHz Dk Material A Rich, 66% N/A N/A N/A N/A (control) Poor, 55% N/A N/A N/A N/A Material B Rich, 70% Poor, 53% Material C Rich, 73% Poor, 53% Material D Rich, 73% Poor, 53% Material E Rich, 73% Poor, 53% Material F Rich, 73% Poor, 53% Material G Rich, 73% Poor, 53% Material H Rich, 73% Poor, 53% Material I Rich, 70% Poor, 51% Material J Rich, 70% Poor, 51% Material K Rich, 67% Poor, 53% After Pre-Bake and 3x, 245 o C Reflow Simulations Bake/Reflow neither significantly nor consistently changes the laminate dielectric constant. 20

22 inemi BRF- Free PCB Material Project SMASPP Test Status / Results Effective Dielectric Loss Results, Before and After Reflow Simulations Effective Df** HF Laminate Resin Content Rich/Poor 1GHz Df 5GHz Df 10GHz Df 20GHz Df Material A Rich, 66% (control) Poor, 55% Material B Rich, 70% Poor, 53% Material C Rich, 73% Poor, 53% Material D Rich, 73% Poor, 53% Material E Rich, 73% Poor, 53% Material F Rich, 73% Poor, 53% Material G Rich, 73% Poor, 53% Material H Rich, 73% Poor, 53% Material I Rich, 70% Poor, 51% Material J Rich, 70% Poor, 51% Material K Rich, 67% Poor, 53% Before Reflow Effective Df** HF Laminate Resin Content Rich/Poor 1GHz Df 5GHz Df 10GHz Df 20GHz Df Material A Rich, 66% N/A N/A N/A N/A (control) Poor, 55% N/A N/A N/A N/A Material B Rich, 70% Poor, 53% Material C Rich, 73% Poor, 53% Material D Rich, 73% Poor, 53% Material E Rich, 73% Poor, 53% Material F Rich, 73% Poor, 53% Material G Rich, 73% Poor, 53% Material H Rich, 73% Poor, 53% Material I Rich, 70% Poor, 51% Material J Rich, 70% Poor, 51% Material K Rich, 67% Poor, 53% After Pre-Bake and 3x, 245 o C Reflow Simulations Bake/Reflow does not consistently change the laminate loss tangent, but is likely dependant on moisture content at time zero.. 21

23 inemi BRF- Free PCB Material Project MSA / Pb-free Solder Process Compatibility Testing Four Cell Matrix 3x Reflow, 245 o C 5x Reflow, 245 o C 3x Reflow, 260 o C 5x Reflow, 260 o C Expose 6 Parts / Material / Thickness to Each Cell Condition Cross Section Parts To Look For Laminate Integrity Issues Results For 9 of the 10 Halogen Free Laminate Materials, as Well As the Control Material, No Laminate Integrity Issues Were Noted One Laminate Material (Material D ) Showed Resin Cracking Issues In Both 40 and 80 mil Thick Test Vehicles 3x and 5x 245 o C cells Most BFR-free Laminates Did Not Show Functional Degradation Using This Format and Process Flow 22

24 inemi BRF- Free PCB Material Project MSA / Pb-free Solder Process Compatibility Testing Example Photos Of Laminate Cracks Induced By Thermal Exposure Laminate cracking driven by higher temperature reflow process. 23

25 inemi Halogen-Free PCB Project Test Status MEB II Delays in the delivery of the MEB II test vehicles prevented completion of all the test activities for publication in this presentation The following is a summary of the testing to be reported from the MEB II test vehicle Test Dk and Total Loss Via Registration IST Moisture Adsorption CAF Flexure Modulus Tg and Z-axis CTE Status Complete Complete Partial Partial Partial Not complete Not complete All Results will be made available at a later date

26 inemi Halogen-Free PCB Project Test Status MEB II Electricals The Dk and total loss were extracted from S-parameter measurements taken using an Agilent E8364B Performance Network Analyzer (PNA). The test data below was taken from layer 2 innerlayer stripline structures with 5 mil traces, 3 inches long referenced to planes on both layers 1 and 3 across 1080 dielectric. The S-parameter measurements were taken across the full frequency range of the PNA (10MHz to 50 GHz). Dk at Indicated Frequency Material 1GHz 5GHz 10GHz 20GHz 30GHz 40GHz A - Control B C D E F G H I J K Total Loss in db/inch at Indicated Frequency Material 1GHz 5GHz 10GHz 20GHz 30GHz 40GHz A - Control B C D E F G H I J K The Dk for the HF materials is generally equivalent to or higher than the control Material The total loss for the HF materials is generally equivalent to or lower than the control material

27 inemi Halogen-Free PCB Project Test Status MEB II Moisture Adsorption Moisture testing was conducted by placing the coupons in an Espec ECL 2CA Temperature Humidity chamber and measuring the S-parameters using a HP 8510C VNA as the coupons are cycled through a controlled temperature humidity program. The coupons were connected to the 2-port VNA using coax cabled SMA connectors on each end of the test trace. The S-parameter measurements were taken across the full frequency range of the VNA (10MHz to 20 GHz) and recorded by time at 1 hour intervals. The program consists of: 1) initial readings, 2) dry bake at 105C/0%RH until readings reach asymptotic state and, 3) soak at 85C/85%RH until readings reach asymptotic state. Material Code Change in Dk from Dry to 5GHz and 85C A Not Complete B 7.70% C Not Complete D Not Complete E Not Complete F 8.56% G 8.96% H 9.69% I Not Complete J Not Complete K 10.50% Complete results are not available as of this writing for comparison to the control material. Moisture adsorption does significantly affect the Dk of the materials

28 inemi Halogen-Free PCB Project Test Status MEB II Via Registration Registration testing was done electrically with an open circuit reading indicating a passing result and short indicating a failing result. The test probe is an Intel designed unit which translates the opens and shorts output to a registration magnitude and direction for the board. Max Radial A B C D E F G H I J K Board thickness within Material Code Builds F and K had the worst via registration Build C,D, and E have suspect registration data due to known panel adjustments and the large number of perfect registration readings

29 inemi Halogen-Free PCB Project Test Status MEB II IST Testing The IST testing utilized 2 coupon designs on the MEB II board. A through-hole design with 10 mil drill in a 20 mil pad on a 32 mil grid. A microvia coupon with a 5 mil drill in a 12 mil pad on a 20 mil grid. The microvia coupon had 2 circuits, one with microvias from layer 1 to 2 (S1), and the second with microvias from layer 2 to 3 (S2). The coupons were subjected to 5 different assembly conditions prior to IST testing: 1) As is, 2) 3 reflows at 245C peak temp, 3) 5 reflows at 245C peak temp, 4) 3 reflows at 260C peak temp and, 5) 5 reflows at 260C peak temp. The IST testing was conducted in accordance with IPC TM test method. The coupons were tested until a resistance change of 10% was observed or a maximum of 1000 cycles completed. The through-hole coupons were cycled from room temp (72F or 22C) to 150C. The microvia coupons were cycled from room temp to 190C. Material/Supplier Code Microvia Results Through Via Results A Not Complete Not Complete B All 30 passed 1000 cycles 1 - passed 1000 cycles C All 30 passed 1000 cycles 9 - passed 1000 cycles D All 30 passed 1000 cycles 0 - passed 1000 cycles E All 30 passed 1000 cycles All 30 passed 1000 cycles F 15 - passed 1000 cycles 17 - passed 1000 cycles G 18 - passed 1000 cycles 27 - passed 1000 cycles H All 30 passed 1000 cycles 29 - passed 1000 cycles I Not Complete Not Complete J Not Complete Not Complete K 9 - passed 1000 cycles 18 - passed 1000 cycles In general, the cycles to failure dropped as the assembly conditions became more severe. Cross section FA analysis of selected failures are being examined to confirm the root cause of the early failures.

30 inemi Halogen-Free PCB Project Test Status MEB II CAF Testing The CAF testing utilized 2 through hole IST coupon structures. 22 and 16 mil via-to-via spacing with a 10 mil drill. The power and sense circuits were biased at 40V in the through-hole and the microvia coupons. The boards were soaked prior to testing at 85C/85%RH, 96 hours for the 40 mil coupons, and 192 hours for the 80 mil coupons. The coupons were tested at 85C/85%RH for 1000 hrs until a minimum decade drop in the initial resistance was observed. Material/Supplier Code A B C D E F G H I J K CAF Results Not Complete 25 - passed 1000 hours 31 - passed 1000 hours 35 - passed 1000 hours 38 - passed 1000 hours 8 - passed 1000 hours 16 - passed 1000 hours 10 - passed 1000 hours Not Complete Not Complete 11 - passed 1000 hours CAF results for the HF materials tested showed variable responses The same sample conditions produced test results which failed early (<50 hours) and lasted the full 1000 hours without failing

31 inemi BFR-Free Free Projects The Next Step 30

32 inemi BFR-Free Free High Reliability Project Proposal Anticipated Outcomes Validate electrical and mechanical properties Loss tangent and Dk modeling over required range of signal speed Mechanical performance validation for lead free assembly and rework (delamination) Critical Test Parameter Evaluation (CAF, IST, flex, etc.) Validate Board Level Reliability Capability PCB Modulus / Thickness Impact on Mechanical Capability HF Board Level Assy / Rework Process Characterization Mechanical Characteristics (Pad Crater / Ball Pull etc) CTE Characteristics SJR (Shock / TC etc) HF Component / HF PCB Companies Interested in participating in the Follow-On Project should contact Jim McElroy or Bob Pfahl at inemi 31

33 inemi BFR-Free Free High Reliability Project Proposal Status : Key PCB & PCBA parameters identified Initial Suite of testing proposed First Pass SOW (Statement of Work) initiated Next Steps : Finalize SOW Technical Committee Review & Approval Project Members Identified / Project Statements Signed Continue to refine key project attributes Note : Companies Interested in participating in the BFR-Free High Reliability Project should contact Jim McElroy or Bob Pfahl at inemi 32

34 contacts: Jim McElroy Bob Pfahl

35 Back-up What is Halogen Free? 1. JPCA (Japan Printed Circuit Association) JPCA-ES defines criteria and method for halogen-free Br < 0.09wt% (900ppm) Cl < 0.09wt% (900ppm) 2. IEC ( International Electrotechnical Commission) Finalized requirements of IEC : 900 ppm maximum Cl 900 ppm maximum Br 1500 ppm maximum total halogens 3. IPC B has adopted the IEC definition of halogen-free 900 ppm maximum Cl 900 ppm maximum Br 1500 ppm maximum total halogens Note: Fluorine, Iodine, and Astatine (other Group VIIA halogens) are not restricted in the industry definition of halogen-free. 34

36 inemi BRF- Free PCB Material Project Property test methods used in the Halogen free material evaluation Property Tested Test Method Electrical Dielectric constant GHz Loss 1 MHz (IPC-TM-650) B (IPC-TM-650) Thermal Glass transition temperature, DSC (C) Glass transition temperature, TMA (C) Decomposition temperature, TGA (C) Time to delamination (min) (IPC-TM-650) (IPC-TM-650) (IPC-TM-650) A (IPC-TM-650) Flammability EI C-H Physical Pressure cooker test (min) Moisture, 24hr/RT (wt% gain) (IPC-TM-650) (IPC-TM-650) Moisture, 1hr/PCT (wt% gain) ASTM D570 (E 1/105 and D 24/23) Cu bond (lb/in) (IPC-TM-650) Sticker ILB (lb/in) EI CMH Oxide ILB (lb/in) EI CMH CTE (ppm/c) Resin content (IPC-TM-650) (IPC-TM-650)

37 inemi BRF- Free PCB Material Project Targeted Reliability TV Stack-Ups Description Thickness Description Thickness Layer 1 Plated 1/2 oz Cu 1.6 mils Layer 1 Plated 1/2 oz Cu 1.6 mils Prepreg 2.4 mils - 1 ply 1080 Prepreg 2.4 mils - 1 ply 1080 Layer 2 Plated 1/2 oz Cu 1.2 mils Layer 2 Plated 1/2 oz Cu 1.2 mils Prepreg 2.4 mils - 1 ply 1080 Prepreg 2.4 mils - 1 ply 1080 Layer 3 Unplated 1/2 oz Cu 0.6 mils Layer 3 Unplated 1/2 oz Cu 0.6 mils Core 4 mils - 1 ply 2116 Core 4 mils - 1 ply 2116 Layer 4 Unplated 1/2 oz Cu 0.6 mils Layer 4 Unplated 1/2 oz Cu 0.6 mils Prepreg 3.6 mils - 2 ply 106 Prepreg 3.6 mils - 2 ply 106 Layer 5 Unplated 1 oz Cu 1.2 mils Layer 5 Unplated 1 oz Cu 1.2 mils Core 6 mils - 2 ply 2112 Adjust to achieve overall thickness of 0.040" Core Layer 6 Unplated 1 oz Cu 1.2 mils Layer 6 Unplated 1 oz Cu 1.2 mils Prepreg 3.6 mils - 2 ply 106 Prepreg 3.6 mils - 2 ply 106 Layer 7 Unplated 1/2 oz Cu 0.6 mils Layer 7 Unplated 1/2 oz Cu 0.6 mils Core 4 mils - 1 ply 2116 Core 4 mils - 1 ply 2116 Layer 8 Unplated 1/2 oz Cu 0.6 mils Layer 8 Unplated 1/2 oz Cu 0.6 mils Prepreg 2.4 mils - 1 ply 1080 Prepreg 2.4 mils - 1 ply 1080 Layer 9 Plated 1/2 oz Cu 1.2 mils Layer 9 Plated 1/2 oz Cu 1.2 mils Prepreg 2.4 mils - 1 ply 1080 Prepreg 2.4 mils - 1 ply 1080 Layer 10 Plated 1/2 oz Cu 1.6 mils Layer 10 Plated 1/2 oz Cu 1.6 mils 40 mils 80 mils 47 mils - 6 plies 7628 Adjust to achieve overall thickness of 0.080" HOP31 and MEB II Test Vehicles will be built with both 40 mil and 80 mil thickness stack-ups 36

38 MEB II Test Methods Board Level Reliability and Mechanical Testing: IST (Interconnect Stress Test) Precondition samples 3X reflow prior to soldering connectors. Test per IPC TM at a test temperature of 150C. Test to failure. CAF Test per IPC TM Test via to via, via to trace, trace to trace, and plane to plane with the following structures: modified IST coupon, trace and space coupon, Hi-pot coupon. Test conditions: 65 or 87% RH with bias voltage of volts depending on design. Test to failure. Flexural Modulus Test per ASTM D x ¾ sample. Test X and Y board directions. Copper Peel Strength - Test per IPC TM C Peel Strength of Metallic Clad Laminates. 5 x ¾ sample. Tg and z-axis CTE Test per IPC TM C test method. 6mm x 6mm sample. Thermal Stress X-section Test per IPC TM E. 1X and 3X floats at 288C. Resin Micro-hardness Micro-hardness indenter on x-sectioned resin rich area of the laminate. Solder mask adhesion Test per IPC TM B

39 MEB II Test Methods Electrical Testing: Permittivity (Dielectric Constant) and Loss Tangent (Dissipation Factor) VNA S-parameter measurements up to 30 GHz. Moisture Diffusivity In situ VNA S-parameter measurements at 105C bake, 85C/85% RH, and 35C/85% RH. Check moisture absorption rate and desorption rate. Insulation Resistance Test per IPC TM Capacitance Test per IPC TM A Assembly Testing: Temp Cycle In situ air to air method (HATS machine). Conditions are product dependent, need to finalize test temps and dwells. Test to failure. Transient Bend Package size dependent spans for bending. Measure strain curves and examine damage levels (Die and Peel, x-section) Rework Test thermal limits of rework conditions. Board side ball pull Dage ball pull equipment.