Scaling, Power and the Future of CMOS. Mark Horowitz, Elad Alon, Dinesh Patil, Stanford Samuel Naffziger, Rajesh Kumar, Intel Kerry Bernstein, IBM

Transcription

1 Scaling, Power and the Future of CMOS Mark Horowitz, Elad Alon, Dinesh Patil, Stanford Samuel Naffziger, Rajesh Kumar, Intel Kerry Bernstein, IBM

2 A Long Time Ago In a building far away A man made a prediction On surprisingly little data That has defined an industry Slide 2

3 Moore s Law Slide 3

4 CMOS Computer Performance Slide 4 intel 386 intel 486 intel pentium intel pentium 2 intel pentium 3 intel pentium 4 intel itanium Alpha Alpha Alpha Sparc SuperSparc Sparc64 Mips HP PA Power PC AMD K6 AMD K7 AMD x

5 Moore s Original Issues Design cost Power dissipation What to do with all the functionality possible Slide 5 ftp://download.intel.com/research/silicon/moorespaper.pdf

6 Outline How designers will deal with poor power scaling Origins of the power problem An optimization perspective Low power circuits and architectures Cost of variability Future scenarios What device characteristics matter (to me) Slide 6

7 The 80 s Power Problem Until mid 80s technology was mixed nmos, bipolar, some CMOS Supply voltage was not scaling / power was rising nmos, bipolar gates dissipate static power From Roger Schmidt, IBM Corp Slide 7

8 Solution: Move to CMOS And then scale Vdd 10 1 Feat Size (um) Vdd 0.1 Jan-85 Jan-88 Jan-91 Jan-94 Jan-97 Jan-00 Jan-03 Slide 8

9 Scaling MOS Devices JSSC Oct 74, pg 256 In this ideal scaling V scales to αv, L scales to αl So C scales to αc, i scales to αi (i/µ is stable) Delay = CV/I scales as α Energy = CV 2 scales as α 3 Slide 9

10 Processor Power Continued to grow, even when Vdd was scaled Slide 10

11 Why Power Increased Growing die size, fast frequency scaling Clock Frequency (MHz) Slide 11

12 Good News Die growth & super frequency scaling have stopped 100 Cycle in FO Slide 12

13 Processor Power They were high power too Slide 13

14 Bad News Voltage scaling has stopped as well kt/q does not scale Vth scaling has power consequences If Vdd does not scale Energy scales slowly Slide 14 Ed Nowak, IBM

15 Energy Performance Space Every design is a point on a 2-D plane Energy Performance Slide 15

16 Energy Performance Space Every design is a point on a 2-D plane Energy Performance Slide 16

17 Energy Performance Space Every design is a point on a 2-D plane Energy Performance Slide 17

18 Trade-offs for an Adder 10 5 Dom. BK Stat. KS 10 4 Stat.Carr.Chain Stat. BK Stat.Carr.Sel Dom. LF Dom. KS 10 3 Stat. LF Stat Slide

19 Key Observation: Define the Energy/Delay sensitivity of parameter For example Vdd: Sens V ( ) dd E V = dd D V = dd V V dd dd * At optimal point, all sensitivities should be the same Must equal the slope of the Pareto optimal curve Slide 19

20 What This Means Vdd and Vth are not directly set by scaling Instead set by slope of Pareto optimal curve Leakage rose to lower total system power! 10 5 [V dd =1.3 Vt N =0.22] 10 4 [V dd =1.2 Vt N =0.26] 10 3 [V dd =0.68, Vt N =0.31] [V dd =1 Vt N =0.30] Slide 20

21 Low Power Design Techniques Three main classes of methods to reduce energy: Cheating Reducing the performance of the design Reducing waste Stop using energy for stuff that does not produce results Stop waiting for stuff that you don t need (parallelism) Problem reformulation Reduce work (less energy and less delay) Slide 21

22 Cheating Many low-power papers talk only about energy Don t consider performance Reducing performance can always reduce energy But there are many ways to reduce performance Good technique must lower the optimal curve Sensitivity of technique Must be better than current curve This depends on location on the curve Slide 22

23 Reducing Energy Waste Clock gating If a section is idle, remove clock Removes clock power Prevents any internal node from transitioning Create system power states Turn on subsystems only when they are needed Can have different off states Power vs. wakeup time Disk (do you stop it from spinning?) Slide 23

24 Embedded Power Gating Since transistors still leak when power is off Power Switch Control Signals Embedded Power Switches Rows of Standard Cells Can reduce leakage 250x reported But costs Performance Drop in Vdd, Gnd Royannez, et al, 90nm Low Leakage SoC Design Techniques for Wireless Applications, ISSCC 2005 Slide 24

25 Range of Applicability Power supply gating Done to remove leakage power But slows down the circuit Adds series resistance to the supply Energy/op Makes circuit worse when energy sensitivity is high Performance Slide 25

26 Parallelism If the application has data parallelism Parallelism is a way to improve performance With low additional energy cost Slide 26

27 Existing Processors 1 Watts/(Spec*L*Vdd 2 ) processors working in parallel Spec2000*L Slide 27

28 Parallel Server Chip Power 5 from IBM Slide 28

29 Problem Reformulation Best way to save energy is to do less work Energy directly reduced by the reduction in work But required time for the function decreases as well Convert this into extra power gains Shifts the optimal curve down and to the right Energy/op Slide 29 User Performance

30 Cost of Variation Variability changes position of the optimal curves Need to margin Vth, Vdd to ensure circuit always works 10 1 Vth = 120 mv Energy Vth = 0 mv 10-1 Performance 10 0 Slide 30

31 Partial Compensation Adjust Vdd after you get part back Compensates very well for small deviations in Vth 10 1 Vth = 120 mv Energy Vth = 0 mv 10-1 Performance 10 0 Slide 31

32 Reducing Voltage Margins At test time determine Vdd for that part Have private DC-DC converter already 20% Slide 32

33 Variable Application Demands Try to provide a couple of operating points Application can control speed and energy Hard question is what are valid Vdd, F pairs Usually determined during test Dynamic voltage scaling Intel Speed Step in laptop processors 2 performance/power points Transmeta Long Run Technology Many operating points. Test data + formula Slide 33

34 Constant Power Scaling Foxton controller on next-gen. Itanium II Raises Vdd/boosts F when most units idle Lowers Vdd for parallel code to stay in budget Slide 34

35 Self Checking Hardware Razor (Austin/Blaauw, U of Mich) Use the actual hardware to check for errors Latch the input data twice Once on the clock edge, and then a little later If the data is not the same, you are going too fast clk clk_del Din 2 Din 1 Din RAZOR FF Main Flip-Flop Shadow Latch Error_L comparator Q[0] error Slide 35

36 With Error Recovery Can run the chip so it makes some errors Chip gets right answer 99.9% of the time 0.1% of the time, the chip must rerun operation Voltage at 0.1%Error Rate 1.8 Chips 1.7 Linear Fit y= x Voltage at First Failure Slide 36

37 Adjusting Vth In theory want to adjust Vth too Leakage (A) Very hard to do with modern transistors Vdd (V) Slide 37 Leakage vs Vdd with Different Body Bias Vbb=0.8 Vbb=0.7 Vbb=0.6 Vbb=0.5 Vbb=0.4 Vbb=0.3 Vbb=0.2 Vbb=0.1 Vbb=0

38 Future Systems Some simple math Assume scaling continues Dies don t shrink in size Average power/gate must decrease by 2x / generation Since gates are shrinking in size Get 1.4x from capacitive reduction Where is the other factor of 1.4x? Slide 38

39 Exploit Parallelism / Scale Vdd If you have parallelism Add more function units Fill up new die (2x) Lower energy/op E/ P will decrease Vdd, sizes, etc will reduce Build simpler architectures Energy/op Performance Works well when E/ P is large Per unit performance decrease is small Slide 39

40 Exploit Specialization Optimize execution units for different applications Reformulate the hardware to reduce needed work Can improve energy efficiency for a class of applications Stream / Vector processing is a current example Exploit locality, reuse High compute density HISC NI µ-controller Bill Dally et al, Stanford Imagine Memory System SRF Clusters Slide 40

41 Exploit Integration If both those techniques don t work Still can increase integration by at least 1.4x Moving units onto one chip Reduces the number of I/Os on system I/O can take significant power today Allows even larger integration Slide 41

42 TI - OMAP2420 Royannez, et al, 90nm Low Leakage SoC Design Techniques for Wireless Applications, ISSCC 2005 Specialization And power domains Most units are off OMAP Power Domains #1: MCU Core #2: DSP Core #3: Graphic Accelerator #4: Core + Periph. #5: Always On logic Slide 42

43 Low-Power PowerPC Nowka et al., Lowpower PowerPC, ISSCC Slide 43

44 What All This Means As long as $/function and cap continue to scale Moving to the new technology will be profitable And will allow designs to be better systems In the worst case, active die area will decrease Scale gates by the decrease in gate capacitance In most cases, we will do much better But how to optimize devices in this new domain? Slide 44

45 Radical Idea: Scaling channel length may no longer be critical I still want small (i.e. dense) devices But I also want lower variations & external control of Vth Longer Leff may actually improve energy efficiency Less variability lower energy penalty Especially as move to lower performance (parallelism) Energy L nom L nom + 10% 120 mv 110 mv 60 mv 55 mv Performance Slide 45

46 Conclusions Unfortunately power is an old problem Magic bullets have mostly been spent Power will be addressed by application-level optimization, parallelism/specialized functional units, and more adaptive control Need to rethink scaling Still makes things cheaper But what do we want from scaled transistors? Slide 46

47 Technology Scaling Seems simple, Every years Number of transistors double Transistors get faster Gates become lower power (CMOS) Life just gets better and better Slide 47

48 Reality is a Little Different While scaling has been smooth Almost nothing else has been Device and circuit technology has changed DTL, ECL, TTL, pmos, nmos, CMOS Power periodically becomes a critical issue It is critical again Slide 48

49 nmos, TTL, ECL Were King 1978 Started in VLSI First design was bipolar/ecl 3µm nmos was hot Intel 8086 Intel 286 BIT Sparc Slide 49 DEC µvax HP Focus

50 MOS Scaling Was Understood MOS devices operate on electric fields If E fields are the same Relation between E and J is the same So if all voltages and lengths scale iv curve retains the same shape, scaled in V Bob Dennard worked all the math in 74 JSSC Oct 74, pg 256 Slide 50

51 Dilemma Processors today are power limited As are many other chips Technology scaling will not save us With Vdd fixed, energy scaling will be modest How does one build more powerful processors? Or other types of chips When constrained, optimize! Slide 51

52 Optimizing the Right Thing Given systems are power limited Highest performance system is not interesting Will dissipate too much power Lowest energy solution is also not interesting Will not have enough performance Want constrained optimization Highest performance for 20 Watts Lowest power for 100 SPEC Slide 52

53 Leakage Trends Active Power Density Subthreshold Power Density Gate Length (um) Slide 53

54 Design Parameters To Adjust Circuit (sizing, supply, threshold) Circuit topology (adder: CLA, CSA, ) Logic style (domino, pass-gate, ) Energy/op Performance Micro-architecture (pipelining, cache design, branch architecture, etc) Slide 54

55 Energy Efficient Designs Are on the Pareto optimal curve wasting energy Energy/op infeasible Performance On this curve design parameters are constrained Slide 55

56 Leakage Energy Matching marginal costs for Vdd and Vth V dd 0.4 Voltage Leakage Ratio V th Leakage Ratio Activity Factor Slide 56

57 Measured Leakage Data 0.5 Leakage Ratio Slide 57

58 IBM Cell Processor Slide 58

59 Vth Variation Since leakage is exponential on Vth Average Vth for leakage is not the expected Vth Cumulative Probability Relative Leakage Contribution Leakage Vth Relative Leakage Vth Slide 59

60 How Else to Save Energy? Running faster than needed wastes energy Forces you to run higher on performance curve Why do you run faster than needed? Need margins to account for variability From application, environment, or technology Variations cause waste Slide 60

61 Dynamic Voltage Scaling Burd et al ISSCC 2000 Slide 61

62 Dynamic Voltage Scaling Dynamic voltage scaling Adjusts Vdd to the right value for desired performance Big problem is how to find the right Vdd Need to know the relationship between Vdd and F Need to have a circuit that matches the critical path How do you do this with variations? Slide 62