Topics. Performance Characterization. Performance Characterization. Performance Characterization. Resistance Estimation. Performance Characterization

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1 Topics Performance haracterization Performance haracterization apacitance Estimation Inductance Estimation Voltage versus Time curve (ideal) 3 March March 009 Performance haracterization Performance haracterization Gate delay Voltage versus Time curve Interconnect delay 3 March March Performance haracterization Delay Primary determinant of the speed of a circuit Due to resistances and capacitances Dependent on resistivity ρ of material Directly proportional to length Inversely proportional to cross-sectional area l R = ρ A 3 March March 009 6

2 l ρ l R = ρ = = Rs A H W L W R s is the sheet resistance expressed in terms of Ω/ (ohms per square) square is a dimensionless quantity 3 March March Intrinsic resistance In linear region (for a given V GS ) (Al) (Based on a typical 0.5 µm MOS process) I DS = k ( VGS VT ) V DS V DS L Req = = = k( V V W GS T ) µ V V ox( VGS VT ) W ox ( GS T ) µ L Rs = µ ( V V ) ox GS T 3 March March apacitance Estimation Intrinsic resistance Dependent on ox and carrier mobility Typically Ω/ Temperature variant Intrinsic capacitance Interconnect capacitance Interconnect capacitance and resistance is the primary determinant of interconnect delays Rs = µ ( V V ) ox GS T 3 March March 009

3 Overlap related capacitance hannel related capacitances Dependent on region of operation Diffusion to substrate capacitances 3 March March Overlap related capacitance ε ox GSO = GDO = Aoverlap = ox xdw tox Usually can be ignored since x D is very small Source n+ Gate x D p substrate Gate oxide Drain n+ 3 March March hannel related capacitances utoff No channel Therefore, no gate to source or drain capacitances hannel related capacitances Depletion -- No channel 3 March March

4 hannel related capacitances As gate voltage increases, depletion region deepens (d increases), causing dep to decrease, and thus decrease the gate to body capacitance As gate voltage nears V T, inversion channel forms causing a barrier for the gate to body capacitance hannel related capacitances Saturation hannel is pinched off Gate to source capacitance exists Gate to drain capacitance is zero GS = 0 GD = oxwl 3 3 March March hannel related capacitances Linear hannel is formed Therefore, no gate to body capacitance GS = GD = oxwl Depletion Saturation Linear 3 March March 009 Transistor Grate apacitance hannel related capacitances Worst case g = WL ox ox ranges from.7-6 ff/µm For a.5µ by.5µ channel = (6)(.5)(.5) g =3.5 ff 3 March March

5 Diffusion to substrate capacitance Junction capacitance Side wall or periphery capacitance (drain and source sidewalls) diff = L W j s j is the bottom-plate capacitance per area = ( L W ) diff jsw s + jsw is the side wall capacitance per linear distance 3 March March Interconnect capacitances j is typically ff/µm jsw is typically ff/µm For a.5µ by.5µ diffusion region = L W + ( L W ) diff j s jsw s + = (.5)(.5) +.8( ) = 5.8 ff plate ε di = WL t di 3 March March Interconnect capacitances ross-interconnect capacitances When h is comparable in magnitude to t, fringing electric fields can increase the total effective parasitic capacitance The effect is magnified as the ratio of w to h decreases If w=h, the effective capacitance can be up to 0 times plate an be very difficult to compute Requires three dimensional field simulations Usually provided by process measurements 3 March March

6 ross-interconnect capacitances Inductance For the most part is not an issue Small enough to ignore except for very high performance chips Inductance is usually higher for I/O interfaces 3 March March Delay Definitions Interconnect delay Lumped R model harge V in to V DD t The transient output voltage is V = R out( t) VDD e V DD t dlh R V DD e = ln = R t t dlh. 69R 3 March March Interconnect delay More accurate than lumped R model More difficult to solve for large N Need full-scale SPIE simulation 3 March