# EEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

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1 EEC 118 Lecture #5: MOS Fabrication Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

2 Announcements Lab 3 this week, report due next week HW 3 due this Friday at 4 PM in box, Kemper 2131 Quiz 1 today! Amirtharajah/Parkhurst, EEC 118 Spring

3 Outline Review: CMOS Inverter Transfer Characteristics CMOS Inverters: Rabaey (Kang & Leblebici, and ) MOS Fabrication: Rabaey Chapter 2 (Kang & Leblebici, Chapter 2) Amirtharajah/Parkhurst, EEC 118 Spring

4 Review: CMOS Inverter Operation NMOS transistor: V DD Cutoff if V in < V TN Linear if V out < V in V TN Saturated if V out > V in V TN PMOS transistor V in V out Cutoff if (V in -V DD ) < V TP V in < V DD +V TP Linear if (V out -V DD )>V in -V DD -V TP V out >V in -V TP Sat. if (V out -V DD )<V in -V DD -V TP V out < V in -V TP Amirtharajah/Parkhurst, EEC 118 Spring

5 Review: CMOS Inverter VTC Operation P linear N cutoff P cutoff N linear P linear N sat P sat N sat P sat N linear Amirtharajah/Parkhurst, EEC 118 Spring

6 Review: CMOS Inverter VTC Sizing V DD V out k p =k n k p =5k n Increase W of PMOS k p increases VTC moves to right Increase W of NMOS k n increases VTC moves to left k p =0.2k n V DD For V TH = V DD /2 k n = k p 2W n or 3W n W p V in Amirtharajah/Parkhurst, EEC 118 Spring

7 Preview: Dynamic Positive Edge-Triggered FF Clk Clk D I0 I1 Q Clk C0 C1 Clk No feedback devices Data stored on input capacitances of inverters I0 and I1 Dynamic logic issues apply: leakage, capacitive coupling, charge sharing Amirtharajah/Parkhurst, EEC 118 Spring

8 Preview: Static Latch Bistability V i1 V = V 2 o1 i2 V o A V = V i1 o2 V = V C (metastable) i2 o1 V = V i1 o2 Amirtharajah/Parkhurst, EEC 118 Spring B

9 Preview: Transmission Gate Positive Latch Clk Q D Clk Clk Amirtharajah/Parkhurst, EEC 118 Spring

10 Preview: NMOS Pass Gate Positive Latch Clk Q D Clk VDD V Tn Fewer devices, less area, lower clock load Threshold drop on internal nodes implies more static power, less noise margin Amirtharajah/Parkhurst, EEC 118 Spring Q

11 Fabrication Process Substrate is grown and then cut Round silicon wafers are used Purity emphasized to prevent impurities from affecting operation ( % pure) Each layer deposited separately Some layers used as masks for later layers Planar process is important Requires minimum percent usage of metal to ensure flatness Amirtharajah/Parkhurst, EEC 118 Spring

12 Silicon Substrate Manufacturing Amirtharajah/Parkhurst, EEC 118 Spring

13 Building a Golf Course with Similar Process Plane drops materials from the air Sand, then dirt, then grass seeds, then trees Certain masks applied during process to prevent material from hitting particular areas For instance: After Sand, mask placed over areas where sand trap will exist. Mask later taken off at end of process to reveal sand trap. Amirtharajah/Parkhurst, EEC 118 Spring

14 Fabrication: Patterning of SiO 2 Step I Grow SiO 2 on Si by exposing to O 2 High temperature accelerates this process Cover surface with photoresist (PR) Sensitive to UV light (wavelength determines feature size) Positive PR becomes soluble after exposure Negative PR becomes insoluble after exposure Amirtharajah/Parkhurst, EEC 118 Spring

15 Fabrication: Patterning of SiO 2 Step II Exposed PR removed with a solvent SiO 2 removed by etching (HF hydrofluoric acid) Remaining PR removed with another solvent Amirtharajah/Parkhurst, EEC 118 Spring

16 NMOS Transistor Fabrication Thick field oxide grown Field oxide etched to create area for transistor Gate oxide (high quality) grown Amirtharajah/Parkhurst, EEC 118 Spring

17 NMOS Transistor Fabrication Polysilicon deposited (doped to reduce resistance R) Polysilicon etched to form gate Gate oxide etched from source and drain Self-aligned process because source/drain aligned by gate Si doped with donors to create n+ regions Amirtharajah/Parkhurst, EEC 118 Spring

18 NMOS Transistor Fabrication Insulating SiO 2 grown to cover surface/gate Source/Drain regions opened Aluminum evaporated to cover surface Aluminum etched to form metal1 interconnects Amirtharajah/Parkhurst, EEC 118 Spring

19 Inverter Fabrication: Layout Inverter Logic symbol CMOS inverter circuit CMOS inverter layout (top view of lithographic masks) Amirtharajah/Parkhurst, EEC 118 Spring

20 Inverter Fabrication: NWELL and Oxides N-wells created Thick field oxide grown surrounding active regions Thin gate oxide grown over active regions Amirtharajah/Parkhurst, EEC 118 Spring

21 Inverter Fabrication: Polysilicon Polysilicon deposited Chemical vapor deposition (Places the Poly) Dry plasma etch (Removes unwanted Poly) Amirtharajah/Parkhurst, EEC 118 Spring

22 Inverter Fabrication: Diffusions N+ and P+ regions created using two masks Source/Drain regions Self-aligned process since gate is already fabricated Substrate contacts Amirtharajah/Parkhurst, EEC 118 Spring

23 Inverter Fabrication Insulating SiO 2 deposited using chemical vapor deposition (CVD) Source/Drain/Substrate contacts exposed Amirtharajah/Parkhurst, EEC 118 Spring

24 Inverter Fabrication Metal (Al, Cu) deposited using evaporation Metal patterned by etching Copper is current metal of choice due to low resistivity Amirtharajah/Parkhurst, EEC 118 Spring

25 NWELL MOS Process MOS transistors use PN junctions to isolate different regions and prevent current flow. NWELL is used in P- substrate so that PMOS transistors are isolated and don t share currents. Amirtharajah/Parkhurst, EEC 118 Spring

26 More Complex Processes Twin Well CMOS Process Can help to avoid body effect Allows for Vt and channel transconductance tuning Requires extra processing steps (more costly) Amirtharajah/Parkhurst, EEC 118 Spring

27 Silicon-On-Insulator (SOI) Process Both transistors built on insulating substrate Allows for tight compaction of design area Some of the parasitic capacitances seen in bulk CMOS disappear Wafer cost is high (IBM produces SOI, Intel doesn t) Amirtharajah/Parkhurst, EEC 118 Spring

28 Accounting for VDSM Effects VDSM = Very Deep Sub Micron Effects significant below 0.25 μm (0.18 μm, 130 nm, 90 nm, 65 nm, 45 nm) Compensation made at the mask level OPC Optical Proximity Correction Occurs when different mask layers don t align properly Test structures are used to characterize the process Ability to adapt depends on the consistency of the error from process run to process run Amirtharajah/Parkhurst, EEC 118 Spring

29 Accounting for VDSM Effects: OPC Amirtharajah/Parkhurst, EEC 118 Spring

30 Accounting for VDSM Effects: Example Example of 2D OPC effects: rounded edges, narrowed lines Uncorrected Corrected Amirtharajah/Parkhurst, EEC 118 Spring

31 Compensating for VDSM Effects: Masks Layout Mask Silicon Amirtharajah/Parkhurst, EEC 118 Spring

32 Compensating for VDSM Effects: CAD Flow to compensate is transparent to layout designer Layout design proceeds as normal Mentor Graphics Flow Amirtharajah/Parkhurst, EEC 118 Spring

33 References Design of VLSI Systems. A web based course located at: Simplified Rule Generation for Automated Rules- Based Optical Enhancement, Otto et. al. On web at: dex.html Mark Anders and Jim Schantz of Intel Corporation Jan Rabaey, Lecture notes from his book Digital Integrated Circuits, A Design Perspective Amirtharajah/Parkhurst, EEC 118 Spring

34 Next Time: AC Characteristics CMOS Inverters AC Characteristics: Designing for speed Combinational MOS Logic Amirtharajah/Parkhurst, EEC 118 Spring

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