Lessons Learned in Deploying Part Average Testing in a Production Environment

Transcription

1 The World Leader in High Performance Signal Processing Solutions Lessons Learned in Deploying Part Average Testing in a Production Environment Kieran Horgan, Analog Devices Philippe Lejeune, Galaxy Semiconductor Solutions 1

2 Agenda Lessons learned at ADI (Kieran Horgan) PAT Process Overview Yield Learning Lessons learned at other companies (Philippe Lejeune) Combining different types of outlier removal 2

3 PAT Background at ADI Automated Part Average Test solutions were released into Analog Devices wafer sort areas (Probe) in 2005 Initially implemented to satisfy Automotive Market sector requirements Have extended use of PAT into specific Consumer products Discovered hidden value of PAT to aid continuous improvement activities in Probe 3

4 PAT Process : Release to Production Product Development Product Pre-release Release to Manufacturing Test Engineer Product Engineering DataLog DataLog DataLogs Wafermaps Qty PAT Recipe Result Test Engineers run product and create datalogs and wafermap for Product Product Engineering analyse datalogs and wafermaps and generate Part Average Test recipes QA Analysis and Approval of Results and Prior Analysis 4

5 PAT Process : Production Operation Wafer Sort (Probe) Automated PAT PAT Yield Analysis PAT Recipe Result Feedback PATENGINE DataLog DataLog DataLogs Wafermaps Production is Run Datalogs and Wafermaps are Generated 5 Post-Sort, the Datalogs are Processed in PAT engine, and Wafermaps and Reports are Generated Yield Engineering Review PAT yield losses and Categorise loss. Data is feed back to the relevant groups for analysis

6 Defect Types Yield Engineering Groups broadly classify failures seen at PAT: Material Defect Loss Loss due to genuine material defect Systematic Defect Loss Loss due to variation or instability in the Process Yield data fed back to Engineering as part of continuous improvement process 6

7 Material Defect Loss Results from Current and Leakage Test PAT analysis Typically Random in Nature Outliers to the Test Distribution Highlights die with Potential Defect and Reliability issues Die are graded as Fail and removed from population Defect Issues are fed back to wafer Fab and Sort Engineers 7

8 Systematic Defect Loss Results from Current and Leakage Test PAT analysis, and Good Die bad neighbourhood analysis Can be seen as Patterns on a wafer Outliers to the Test Distribution Highlights die with Potential Defect and Reliability issues Die are graded as Fail and removed from population Defect Issues are fed back to wafer Fab and Sort Engineers 8

9 Systematic Defect Loss Loss at PAT is typically higher for Systematic Defect Loss than Material Defect Loss Systematic Defect Loss highlights Processing issues Continuous Monitoring of Systematic PAT loss is part of the Continuous Improvement process at Analog Devices Results from PAT guide Engineering to review the process steps and make improvements 9

10 Systematic Defect Loss Continuous Improvement Material Handling Pre-Lot Verifications Golden Device Testing Post-Lot Verifications Yield Monitoring Audits Equipment Specifications Equipment Standardisation Upgrades to Equipments for Process Improvements Equipment Monitoring Equipment Calibration Equipment verifications DUT board verifications Probe Ring verifications Data Integrity Systems Automated Product setups MES integration 10

11 Lessons Learned PAT can lead to both lower DPM and improved yield PAT loss review is integral to the Continuous Improvement and Quality process Separation/Classification of PAT loss types (systematic or defect) is Key Systematic Defects occur as a result of variation or Instability in the Wafer/Probe Process Minimising variation decreases PAT loss and improves processes for all material 11

12 LESSONS LEARNED AT OTHER PAT DEPLOYMENTS Philippe Lejeune, CTO, Galaxy Semiconductor Solutions 12

13 Example of Parametric Outlier 13

14 Example of Geographic Outliers Good die in a bad neighborhood Edge die exclusion Die location history Target Die 14

15 PAT Issues at Die-size Extremes Geographic rules break down for large die Parametric rules miss outliers for small die 15

16 The Value of Hybrid Recipes Combining Multiple PAT Rules Clustering analysis Filters analysis over specific bins and/or masks NNR Mix of local geographic with parametric for finer outlier resolution Minimize unnecessary yield loss 16

17 Issues for PAT: Too Much Spread in the Distribution for Parametric Tests This distribution has zero DPAT fallout no outliers 17

18 But There are Outliers Present! These die are OUTLIERS! 18

19 Solution: NNR (Clustering Analysis) Reduce the sample count to contain local die only Filters analysis over specific bins or masks (eg: outer ring) 19

20 With Reduced Sample Count Outliers Become Visible 20

21 Near Neighbor Residual (NNR) Analysis NNR Analysis to find devices that do not match their neighbors, but are part of the normal wafer distribution. Iddq 21

22 Summary of PAT Lesson Learned Efficient PAT requires flexible rules Richness of PAT rules is instrumental for low yield hit Combining PAT rules offers better coverage Bottom line: PAT as part of a continuous improvement process can result in lower DPM and yield gain. Not just for automotive 22

23 23 Q&A