TSMC Property. ConFab. Bridging the Fabless-Foundry Gap. BJ Woo. Sr. Director Business Development TSMC TSMC, Ltd

Transcription

1 ConFab Bridging the Fabless-Foundry Gap BJ Woo Sr. Director Business Development TSMC

2 2 Outline Fabless Requirements Technology Scaling Challenges IP Quality Foundry Integrated Manufacturing Value Summary

3 3 Fabless Requirements Prior to Risk Production Phase: 1st Si success for design win Competitive Technology Selection Accurate SPICE Model High Quality IP Volume Production Phase: Gain MSS Fast Ramp and Reliable Supply Performance and Yield Improvement Ample Capacity

4 4 Design Enablement for 1 st Si Success Fabless Process for Product NTO Product Spec. Definition Close Collaboration between Fabless and Foundry Foundry Support to Facilitate Product Success Technology Selection Comprehensive Process Offerings Library buildup DRM (RDR) Insertion Post-sim., & Timing Analysis DFM & Accurate SPICE IP Validation IP Quality Management System & Cybershuttle Product Tape-out One Stop Shopping w/ Mask, Si, and Backend

5 5 TSMC CMOS Technology Platforms <20nm FinFET 20nm 28nm 2P2E; M0 HK/MG Low-R 40nm 65/55nm 90/80nm ESF3 Automotive Immersion Cu/ELK Strained Silicon 12 BSI 0.13/0.11µm Cu/LK 8 BSI 0.18/0.15µm 0.25µm ESF1 Automotive 0.35µm >0.5µm Expanding Functionality Expanding Functionality MEMS Embedded Flash (MCU) Embedded DRAM Analog Logic Available RF Planned Power IC- BCD High Voltage CMOS Image Sensor For reference only; Subject to change without notice by TSMC

6 6 Challenges for 1 st Si Success Particularly in Advanced Technology Nodes SPICE model accuracy Variation increases with technology scaling Device structure innovation to reduce random variations RDR (restrictive design rule ) and DFM (design for manufacturing) to reduce layout style related variations IP quality assurance IP quality is one of the key concerns for customers IP quality management system to allow easy access of high quality IPs CyberShuttle support to validate key IPs with Si

7 7 Technology Scaling Larger Variation; Smaller Manufacturing Window Less design margin to start with NMOS Ion/Ioff Plot NMOS Ion/Ioff Plot Isoff Isoff Isat_SS (model) Idsat Isat_FF (model) Idsat 90nm, 65nm, 40nm, 28nm, 20nm,

8 8 Random Variation Reduction Device Structure 35 Vt(au.) Planar SiON/Poly Planar HK/MG σv t T 4 ox W N a L σ 10 FinFET Scaling

9 9 Restrictive Design Rules (RDR) Reduce Layout Style Related Variability 28nm RDR Style OD PO OD PO OD PO PO OD PO PO OD PO Process Variation 65nm SiON 40nm SiON 28SiON No RDR 28HKMG No RDR 28HKMG RDR

10 10 DFM Solutions for Product Performance DFM-rule should be used to improve product performance Disallow J Table 1: Idsat variation as a function of J OD Ploy The effective OD width could vary because of the OD rounding effect when the poly to OD spacing is small

11 11 SPICE Modeling Limitation Layout pattern complexity increases SPICE model simulation variability RDR and DFM significantly reduce simulation vs silicon gap x% 0% Simulation vs Silicon Gap Restricted Layout -x% Layout Patterns Style

12 12 Major Challenges in IP Usage Source : IC Manage global design management survey April, 2011 Quality Is Key Concern

13 13 IP Quality Management System Robust IP Quality Check/Management to Lower IP Usage Risk Ecosystem IP DRC/LVS ESD Silicon Report TSMC-Online TM DDR USB SATA DSP SRAM DAC TSMC IP QA System Customer Final Design Data Tape Out Consistency Checks Tape Out ADC Others LVDS MCU IP Dev. Production History Design Margin Data Consistency IP Quality Check IP Quality Score & Usage IP Tag Check for Tape Out Quality

14 DUT6_STD_2C-PR DUT12_STD_DM 14 LC Tank Model=> Accuracy and Schedule Request from high Speed SerDes and PLL PDK with P-cell for Varactor and FMOM Customized Inductor For design Q-Factor frequency (GHz) Customers Successful Design Generate Layout and Tape out System simulation In Customer site

15 15 HKMG Analog Layout Guidance HKMG layout considerations for sensitive analog blocks Device mismatch induced by gate density Gaps between simulation and silicon Foundry & EDA collaborated solutions based on HKMG layout guidance in sensitive regions Surrounding patterning and gradient insertion feature Gradient density analysis tool Verification tool to check against golden data

16 16 CyberShuttle for IP Validation TSMC CyberShuttle has successfully verified more than 12,000 devices

17 17 First Silicon Success TSMC optimizes technology and manufacturing to deliver high first silicon success rate 100.0% TSMC NTO Success Rate 99.8% 99.6% 99.4% 99.2% 99.0% 98.8%

18 18 Manufacturing Excellence to Serve Customer Demand Giga fab and integrated mask-wafer-backend service drive fast ramping and reliable supply Persistent technology optimization to improve performance and yield Continue in Capex investment to support required capacity

19 19 Benefits of GIGAFAB GIGAFAB manufacturing scale improves ramping speed and delivery precision control Effective Capacity Ramp-up Agility Fast Cycle time GIGAFAB P1 P2 P3 P4 Delivery Precision Cost Effectiveness

20 20 Synchronization Drives Manufacturing Efficiencies & Fast Time to Market Increase production efficiencies Centralized production control and Integrated CIM Assure fast time-to-market Customer GDS Design Service Mask Making/ OPC Wafer Fabrication Backend Service Packaged Components Manufacturing Synchronization

21 21 Cycle Time Improvement Cycle time is one of the keys to enable fast time to market Days/Layer 1

22 22 Productization for Advanced Nodes Cost and complexity increase significantly with technology scaling Shortening product T/O to volume production enables better ROI for Foundry and Customers (Starting point: wafer output > 1K)

23 23 Optimizing Technology Processes for Better Yield and Performance Product Engineering Feed backward for faster yield learning Feed forward for higher yield Customer GDS Design Service Mask Making/ OPC Wafer Fabrication Backend Service Packaged Components Technology Optimization

24 24 D 0 Improvement Drive D 0 reduction relentlessly even facing increased technology complexity

25 25 Product Grade Improvement 28nm Customer collaboration achieves continuous speed and power improvements through process/device optimization Product grade improvement methodology keeps customer s products competitive 28HP Speed improvement 28LP IDDQ IDDQ reduction IDDQ IDDQ reduction Speed Speed

26 26 Synergy of Mask & Wafer Technology Mask and wafer process technologies are developed together for optimized result Synergistically developing OPC, mask and silicon processes ensures tape out success and high yields Feedback & Iteration for Optimized Result GDS OPC* Mask Wafer Making Printing Yield Test Production * OPC : Optical Proximity Correction

27 27 Integrated Si and Backend Service Si foundry with integrated bump and CP service, extendable to turnkey, offer customers: Simplified supply chain without bump capacity matching issue Consistent bump and test quality Shortened cycle time OSAT A Bump Si Wafer Foundry OSAT B Bump OSAT C Bump Integrated Wafer, Bump, & CP Service Wafer Bump OSAT CP OSAT CP CP OSAT A Ass y+ft OSAT B Ass y+ft OSAT C Ass y+ft OSAT A Ass y+ft OSAT B Ass y+ft OSAT C Ass y+ft

28 28 Integrated Manufacturing Value Faster Responsiveness Higher Product Grade Better Quality One-stop Ownership Customer GDS Design Service Mask Making/ OPC Wafer Fabrication Backend Service Packaged Components Integrated Manufacturing One- Stop Ownership

29 29 Summary Bridging the Fabless-Foundry gap to achieve timeto-market with the best performance/watt/cost Manufacturers and designers to work closer than before almost like IDM Early engagement on technology selection, structured layout/ RDR, and early Si validation of critical circuits Close collaboration in the development of circuits with performance/power optimization that adapt to manufacturing variation Collaboration should extend to production phase for high MSS Foundry Integrated Manufacturing Value fast responsiveness, higher product grades, better quality, and one-stop ownership