Lessons Learned from SEMATECH s Nanoimprint Program

Transcription

1 Accelerating the next technology revolution Lessons Learned from SEMATECH s Nanoimprint Program Matt Malloy Lloyd C. Litt Mac Mellish 10/19/11 Copyright 2010 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline Timeline of nanoimprint at SEMATECH Key lessons learned Overall performance Process/Templates Overlay Defectivity Unit process development and alternative applications Summary

3 Timeline of Nanoimprint at SEMATECH Imprio300 Jet and Flash Imprint Lithography (J-FIL) tool installed at SEMATECH. Transition from SEMATECH to member company/customer driven NIL projects Early investigation and planning for NIL program J-FIL learning and development Process/Tool stability testing Overlay Defectivity Member company/customer projects, semiconductor and other applications

4 Overall Technology Status J-FIL is continuously improving towards the ITRS requirements for 22nm Flash. Process Template Metric Resolution CDU LWR Overlay Defectivity Resolution CDU LWR Image Placement Defectivity Status SEMATECH has actively worked in all of the critical areas. Excellent resolution, CDU, and LWR performance. Overlay is an engineering challenge, not an insurmountable roadblock. Defectivity remains the primary technical challenge, but is improving rapidly.

5 Resolution, CDU, LWR Achieving excellent pattern quality is easy with J-FIL. 22nm HP Posts 22nm Gate Structures 22nm HP L/S Across 300mm Wafer 11nm Pattern (as measured) CD: 19.4nm average, 0.97nm 3σ LWR: 2.45nm average, 0.6nm 3σ (Courtesy of Samsung)

6 Process Integration Integration with existing processes provides a unique set of challenges specific to nanoimprint. Imprint on High-K Metal Gate Stack (7 layer film stack, including hard mask layers) Top layers in stack delaminated from wafer due to adhesion failure in film stack during template/wafer separation. Films stacks for nanoimprint must be designed to handle high separation forces. Additional challenges Process setup, particularly drop pattern setup and offset, can be subjective. Development of robust RLT breakthrough etch processes.

7 Unexpected Problems Problems can quickly escalate for a variety of reasons. Good Imprint Sequence Showing Rapidly Growing Defect (Optical Images) Common problems: Template design Adhesion layer condition Template contamination Particles Field 2 Field 170 Field 50 Field 90 Field 130 Field 210 Field 230 Field 249 Separation Problem NOT A COMMON PROBLEM! Separation problem occurred during testing of experimental, non-standard, template material and process. Wafer broke during failed attempt to recover it from the tool.

8 Residual 3σ (nm) Templates Amazing 1X template capability. 1 st Gen. Template Template Pattern Placement (Residual 3σ) Early 2008 Early 2008 Early 2009 Late 2009 Late 2009 Template # Res X Res Y 22nm Flash Requirement 22nm HP L/S Programmed Defects Alternative Patterns 2 nd Gen. Template Recent transition to 6025 form factor: Eliminates some of the primary sources of template fabrication defects (65mm dice/polish). Conforms to industry standard substrate size (compatible with existing infrastructure).

9 Overlay While moated alignment marks are not suitable for high volume manufacturing, they have worked well for development. Alignment Mark Contamination High Contrast, Moatless, Alignment Marks Note reduced mark size Resist contaminated alignment marks No moat Moat Successfully demonstrated the following on the Imprio300 at SEMATECH using moated alignment mark templates: ~15nm overlay across 300mm etched Si wafers. 0 layer alignment wafers created on an ASML 1900i. (Courtesy of Molecular Imprints) Proof of concept overlay ~30nm on high-k metal gate stack wafers. Film stack: Adhesion/SiO 2 /a-si/tin/hfo 2 /Si

10 Overlay Originally considered a roadblock to implementation, now mainly just an engineering challenge. Date X mean+3σ Y mean+3σ Comments Presented By Early nm 21nm 18x30mm field Samsung Late nm 11.3nm 15x15mm field Toshiba Late nm 14.6nm 26x32mm field SEMATECH Early nm 13.0nm Early nm 10.31nm Expect further improvements with: Imprio500, High Contrast Marks 26x33mm field, Imprio500, 6025 template (22nm Flash overlay requirement is 7.4nm.) Reduced template pattern placement. Finer control of imprint tool alignment systems. Reduced distortions on incoming wafers. The absence of a global alignment strategy is a concern. Molecular Imprints Molecular Imprints

11 Defectivity Defect sources are being systematically identified and mitigated by suppliers and end-users. Particles Large Area Glass Damage Mouse Bite Non-Fill Bridge Template Fabrication Wafer Processing Design for imprint (DFI) Blank substrates Processing/Cleaning Inspection/Repair Replication Incoming wafers Wafer prep/handling Pre-imprint inspection Template cleaning Imprint Gross Defectivity Metrology/ Testing Inspection Device testing

12 Incoming Wafers (Particles) Incoming wafer cleanliness is a critical concern as imprint is much more sensitive to particles than projection lithography. Why is a particle free wafer necessary for J-FIL? Large particle preventing resist spread Self cleaning Typical front-side particle spec: <50 >90nm (or 65nm) Not okay for J-FIL! Accumulating defects Stuck to template Stuck to template ITRS Starting Material spec for 22nm: Critical particle diameter: ~11nm Critical particle count: 260 particles Okay for J-FIL? Unpatterned wafer inspection: Sensitivity ~30nm with KLA SP2/SP3. Shared concern with all NGLs. Best Case No particles Self cleaning Small, stuck on template, non-damaging Large, prevents proper imprint, non-damaging Template damage Worst Case

13 Template Defectivity Template defectivity has improved significantly in recent years. Early generations: Small to huge defects, high defect counts. Current generation: Mainly small, single point defects. Examples of Current Template Defects (at DNP) Made in late 2010 by DNP for SEMATECH 80nm pitch comb & serpentine structures 6025 template defectivity now ~10def/cm 2 (Toshiba, SPIE Advanced Lithography 2011).

14 Recent Defect Results A low defect nanoimprint process is possible.

15 Recent Defect Results A low defect nanoimprint process is possible.

16 System Integration Predictions An imprint specific, customized integration strategy will need to be considered for particle/defect mitigation. Theoretical Modularized System Integration Strategy Example Pre-imprint inspection. Send non-conforming wafers for reclean or rework. Spin-coat/bake/chill adhesion layer or other underlayer. Inspection/Sorting Adhesion coating (Coat/bake/chill) Clean & Surface Preparation Imprint Head #1 Imprint Head #3 Imprint Head #2 Imprint Head #4 Multiple imprint heads to increase throughput. Template SMIF load/unload Remove all particles from incoming wafers at imprint cluster. Template Cleaning Wafer FOUP load/unload Frequent template cleaning may require integrated cleaning capability.

17 Template Replication Flexibility of tools/processes allows for quick replication of device and test patterns off of previously patterned wafers (EUV, 193i, e-beam, etc.). (Samsung, SPIE Advanced Lithography, 2011) Blank Template with Hardmask Replicated Pattern Replication of some form: (Courtesy of Samsung) Will be required for device manufacturing with nanoimprint. Should be considered for the manufacture of EUV/193i reticles to reduce CoO.

18 Alternative Applications & Unit Process Development Nanoimprint is an ideal solution for alternative applications and unit process development due to its flexibility and resolution capability. Cancer Research 450mm Patterning (Courtesy of CNSE) Color Filter Master Template Fabrication (Courtesy of Samsung) Nanoimprint chosen as the patterning solution for early 450mm development.

19 Summary Key lessons learned over the course of SEMATECH s nanoimprint program have been presented. Significant improvements have been demonstrated for most critical aspects of J-FIL. Its viability as a candidate for future memory manufacturing has been demonstrated, but additional development is required. It is an ideal solution for unit process development and alternative applications. Would like to see: Integration of imprinted layers into the manufacturing flow of a 22nm (or similar) node device, and demonstration of performance. An assessment of overlooked topics such as template repair and lifetime, global alignment, edge die and zero street width imprinting. Industry support and collaboration for this very capable technology.

20 Acknowledgements Molecular Imprints, for continuing to push the limits of nanoimprint to make the technology what it is today. DNP, for developing high end template fabrication processes in support of the nanoimprint community. Toshiba, Samsung, Suss-HamaTech, Canon, IMS, EVG, ISMI, and other companies who have helped support the development of nanoimprint and whose materials are referenced in this presentation. CNSE, for providing wafer processing and metrology support, and a place in Albany to work on nanoimprint for the past three years. SEMATECH, for providing the opportunity to investigate nanoimprint lithography for semiconductor (and other) applications. Thank you