Best Known Methods for Latent Reliability Defect Control in 90nm 14nm Semiconductor Fabs. David W. Price, Ph.D. Robert J. Rathert April, 2017

Transcription

1 Best Known Methods for Latent Reliability Defect Control in 90nm 14nm Semiconductor Fabs David W. Price, Ph.D. Robert J. Rathert April, 2017

2 Outline 1. Introduction 2. BKM s to Minimize Latent Reliability Defects 3. Application of Part Average Testing Principles to Inline Defect and Metrology Data 2 KLA-Tencor Confidential - Internal Use Only

3 KLA-Tencor Overview >40 years Global Leader in Process Control since 1976 ~21,900 ~ tools installed worldwid e global employees countries $3.0B FY16 revenue $2.0B R&D investment over last 4 fiscal years 3 KLA-Tencor Confidential - Internal Use Only

4 Semiconductor Inline Process Control 1) You can t fix what you can t find 2) You can t control what you can t measure 4 KLA-Tencor Confidential - Internal Use Only

5 Semiconductor Reliability For a well designed process and product, early-life reliability issues are dominated by random defectivity. 5 KLA-Tencor Confidential - Internal Use Only

6 Random Defectivity The defect types that impact reliability are the same as those that impact yield. 6 KLA-Tencor Confidential - Internal Use Only

7 Outline 1. Introduction 2. BKM s to Minimize Latent Reliability Defects 3. Application of Part Average Testing Principles to Inline Defect and Metrology Data 7 KLA-Tencor Confidential - Internal Use Only

8 Increasing Yield Decreasing D0 Continuous Baseline Defect Reduction Automotive Fabs must reduce defectivity beyond what is normally considered cost-effective. process tool defectivity Automotive Current world class yield and defect density Defect-limited yield requirements for automotive devices Non-Automotive 0% Time 8 KLA-Tencor Confidential - Internal Use Only

9 Process Tool Defect Reduction Common Practice Surfscan Pre-scan Process DSA Adders to SPC Surfscan Post-scan 1. Establish baseline Best tool for automotive Areas for improvement 2. Empower tool owners 3. Set quarterly reduction targets 10 0 Tool/chamber matching Intra-tool partitioning SEM Review with EDX Signature analysis Defect & root cause library 9 KLA-Tencor Confidential - Internal Use Only

10 Sensitivity to Killer and Latent Defects The inline defect sensitivity requirement for Automotive is one full design rule more aggressive than non-automotive devices. Common Practice 10 KLA-Tencor Confidential - Internal Use Only

11 Partition and Quarantine Program Common Practice Elements of a Product Wafer Inspection Strategy Broadband Plasma Defect Inspection Laser Scanning Defect Inspection Macro/Edge Defect Inspection e-beam Inspection Overlay Metrology Films Metrology CD Metrology 11 KLA-Tencor Confidential - Internal Use Only

12 Macro-Defect Screening Common Practice 12 KLA-Tencor Confidential - Internal Use Only % of wafers are scanned. 1-2 levels, low sensitivity / high tput 2. Results automatically ink and scrap.

13 Outline 1. Introduction 2. BKM s to Minimize Latent Reliability Defects 3. Application of Part Average Testing Principles to Inline Defect and Metrology Data 13 KLA-Tencor Confidential - Internal Use Only

14 Part Average Testing Statistical screening technique Introduced by AEC in 1997 Assumes die outside of the normal distribution (but inside the spec limit) have a higher chance of reliability failures. 14 KLA-Tencor Confidential - Internal Use Only

15 Example 1: Parametric Part Average Testing (P-PAT) Common Practice Is there a statistical difference in chip reliability between Chip A and B? Chip A Chip B 15 KLA-Tencor Confidential - Internal Use Only

16 Example 2: Geographic Part Average Testing (G-PAT) Common Practice Wafer 1 Wafer 2 Is there a statistical difference in chip reliability between Chip A and B? Chip A Chip B 16 KLA-Tencor Confidential - Internal Use Only

17 Application of PAT Concepts to Inline Defect and Metrology Data Strengths: FA points to a direct correlation between reliability failures and on-wafer random defectivity. Fabs already make extensive use of inline Inspection and Metrology for yield improvement and waferlevel excursion monitoring. Traceability: Opportunity for step-level defect data for each chip to improve failure analysis. D rel D yield Challenge: Only a very small fraction of defects produce latent reliability failures. Scrapping every die with a defect would usually mean zero yield. 17 KLA-Tencor Confidential - Internal Use Only

18 Inline Defect Part Average Testing (I-PAT) Inspection Layer 1 (LS) Inspection Layer 2 (LS) Stacked-defect die map created by adding together the defects from inline inspection steps Inspection Layer 3 (BBP) Inspection Layer 4 (LS) Inspection Layer 5 (BBP) Inspection Layer 6 (LS) Inspection Layer 7 (LS) Inspection Layer 8 (BBP) Inspection Layer 9 (EBI) Chip A Chip B... Inspection Layer N (macro) Is there a statistical difference in chip reliability between Chip A and B? 18 KLA-Tencor Confidential - Internal Use Only

19 Emerging Practice I-PAT Implementation Stacked Defect Wafer Map from 10 critical steps Calculate the Latent Defect Probability Index (LDPI) for each die based on # of stacked defects, modified by: Size filtering Rough bin classification Within die location / care area / NanoPoint. Layer-step weighting LDPI Histogram m + 3s 0 Large number SINF* file to probe Outlier Die *Standard Integrator Navigator File 19 KLA-Tencor Confidential - Internal Use Only

20 Summary 1. Latent reliability defects from the semiconductor manufacturing process are a critical issue for automotive electronics reliability. 2. Fabs employ several methodologies to provide additional process control for automotive devices: Use of lowest defectivity process tools Factory wide defect reduction activities Partition and Quarantine of excursion wafers Inline screening using macro defect inspection tools 3. Part Average Testing methodologies are being applied to inline defect and metrology data (e.g., I-PAT ). 20 KLA-Tencor Confidential - Internal Use Only

21 Acknowledgements References: 1. D.W. Price and D.G. Sutherland, Process Watch 7: The Most Expensive Defect, Part 2 Solid State Technology (on-line and print editions). July Shirley, Glenn and Johnson, Scott. Defect Models of Yield and Reliability. Published lecture #13 for Quality and Reliability Engineering ECE 510 course at Portland State University, Roesch, Bill. Reliability Experience. Published lecture #12 for Quality and Reliability Engineering ECE 510 at Portland State University, Riordan et al. Microprocessor Reliability Performance as a Function of Die Location for a.25um, Five Layer Metal CMOS Logic Process. 37 th Annual International Reliability Physics Symposium Proceedings (1999): DOI ( 5. Barnett et al. Extending Integrated-Circuit Yield Models to Estimate Early-Life Reliability. IEEE Transactions on Reliability, Vol. 52, No. 3. (2003). 6. Kuper et al. Relation between Yield and Reliability of Integrated Circuits: Experimental results and Application to Continuous Early Failure Rate Reduction Programs. Proceedings of the International Reliability Physics Symposium (1996): Automotive Electronics Council, Component Technical Committee, Guidelines for Part Average Testing AEC-Q001 Rev-D, December 9, Contributors Doug Sutherland (KT) Kara Sherman (KT) Robert Cappel (KT John McCormack (KT) Barry Saville (KT) Scott Hoover (KT) Jim Young 21 KLA-Tencor Confidential - Internal Use Only

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