ARRAY PACKAGE USERS GUIDELINES

Transcription

1 ARRAY PACKAGE USERS GUIDELINES TABLE OF CONTENTS Section 1 Description of Array Packages Section Editor: Mark McLeod, IBM. 4 Section 2 Array Package Applications Section Editor: Carl Bloch, Digital Equipment Corporation.. 18 Section 3 Electrical and Thermal Guidelines Section Editor: Tom Tartar, AMD.. 22 Section 4 Assembly Process Guidelines Section Editors: Larry Marcanti and Thakor Patel, Northern Telecom.. 33 IMPORTANT NOTICE This document is published by as a convenience to those who may be seeking information on Array Packaging technologies. has not evaluated particular products and cannot be responsible for errors or omissions. does not assume any liability arising out of the application or user of any product or circuit described herein, neither does it convey any license or rights. accepts no liability for incidental or consequential damages arising from use of any products. This disclaimer of warranty is in lieu of all warranties whether expressed, implied or statutory, including implied warranties of merchantability or fitness for a particular purpose by. All rights reserved. 1

2 Overview This document was prepared by the Array Packaging Working group of the HDP User Group. The information included within this document is intended to be an aid in a fast start use array packaging in second level assemblies (Component to PCB). It is not intended to be used solely in the establishment of an assembly process nor is the HDP users group responsible or liable for process results when this guideline is used. Each user will have to use his own good manufacturing judgment and practices to achieve acceptable results. Information contained in these guidelines is based on information obtained from early users of array packages. There are several types of array packages that are in use, as of this writing, and all have different use characteristics and cost/performances windows. They include Plastic Ball Grid array (OMPAC ), Ceramic Ball Grid Array (CBGA), Tape Ball Grid Array (TBGA), and Solder Column Carriers which use solder columns in place of balls (SCC). There are variations on all of these package types which impart added benefits of thermal dissipation, electrical performance enhancement, or reliability enhancement. Each section will attempt to reflect the nuances of all these package types. As with any package, array packages will continue to evolve as new use requirements are defined. The information in this guideline will require updates with time and the reader of this document should be cognizant that information contained is the best present information. L. Marcanti Chairman, Array Packaging Working Group, HDP User Group 2

3 Section 1 Description of Array Packages Ball Grid Array Introduction Ball Grid Array (BGA) packages encompass a broad spectrum of product from factors that can be found under several different names like solder grid array, land grid array, or solder bump array. These BGA Packages are just starting to emerge in volume applications within the industry. Yet, even at this early stage in the product introduction. There are numerous types of BGA packages to choose from. The 2 leading types of PBGA (Plastic Ball Grid Array), which are laminate based packages, and CBGA (Ceramic Ball Grid Array) packages. These packages are currently in use at companies such as Motorola, IBM (R/S 6000 & A/S 400) and Compaq. They are closely followed by TBGA (Tape Ball Grid Array) and CCGA (Ceramic Column Grid Array) packages. The common characteristics across all of these Array packages is the surface mount area array interconnect on the bottom side of the package. This technique offers users smaller form factors than existing packages for equivalent I/O. The area array interconnect is typically on a 2X tighter grid than pinned packages (1.5mm to 1.27mm vs. 2.5mm). This results in up to a 4x area savings over the equivalent pinned packages. The savings over a.5mm peripheral leaded package is about 2.5x. Figure 1 shows the relative savings of BGA vs. PGA and peripheral leaded packages. These savings are maximized with the chip-up designs as illustrated in Figure 1. Within the chip-up designs the ceramic versions currently offer the highest densities since no depopulation is required. The tape version is currently depopulated under the chip and some of the laminate versions will depopulate because of wiring restrictions, thermal vias or to avoid high stress locations under the chip. There are only minor density differences between different chip down BGA designs. Because of the center depopulation they lose some of the chip up or flipchip BGA density leverage. Photo comparing PGA to CBGA 3

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5 Even with these dense I/O footprints. Most of the BGA packages can still be wired without complex card crosssections. A 361 I/O 25mm BGA can wire out 316 signal on a card with 2 signal layers. The remaining 45 connections would likely be required as power for most applications and therefore support the 2Scard. A 625 I/O 32mm BGA can wire out 540 signal I/O on a 4Scard. These 2 examples are for the tighter 1.27mm grid with no center depopulation. Packages with the 1.5mm grid, with center depopulation for thermal vias or a cavity down will be even easier to wire out. The size leverages of BGA's contribute to their thin and light advantages over many existing alternatives. TBGA in its basic configuration is the thinnest and lightest. However, Tape Array Packages lose some of this leverage as coverplates and heatsinks are added. The BGA thermal leverage varies depending on the package type and chip interconnect. The flip chip packages and cavity down laminate packages offer the highest thermal performance. In these packages the heatsink can be attached either directly to the back of the chip (Flip Chip) or through a Cu plane to the back of the chip (Cavity down laminate). All versions of the TBGA package also support attaching the heatsink directly to the back of the chip. The cavity down versions are next in capability. The chip down laminate version can support attaching the chip directly to a copper plane in the laminate which in turn can be attached to a heatsink. More detailed capabilities are covered in the thermal section. The shorter electrical paths provided in these packages offer clear advantages over plastic PGAs. The signal and power connections can drop almost straight down. This reduces connection lengths which shortens the delay, reduces coupled noise and lowers the power distribution inductances. The flipchip versions offer the best overall performance advantages because it repeats the BGA advantages just listed above at the chip interconnection level. These leverages at the chip level can be significant for both the power distribution and signal delays due to the lossey nature of on-chip wiring. Refer to the electrical section for more details. Even with a 2.5X smaller package the BGA leads have center to center lead spacings over 2X larger than the.5mm PQFP. This simplifies the card assembly manufacturing as outlined in assembly section of this document. When should a BGA package be selected? The attributes covered throughout this document show that BGA's should be considered whenever small size, thin & light, enhanced electrical performance, enhanced thermal performance and/or high I/O's are required. Today this high I/O crossover point is in the 200 to 300 I/O range. The price of simple BGAs such as the 2S/0P laminates are approaching PQFP prices in this I/O range. This has started to make their selection economical for even the unenhanced applications. When the BGA card assembly savings are factored in this crossover points moves even lower. The more sophisticated BGA s are priced lower than equivalent pinned modules which will make their selection attractive those applications that don't require plugability. A cost effective socket is required to replace the applications requiring plugablity. While all of the package descriptions and characteristics covered here refer to single chip modules. Their multi-layer capability supports increased wiring capacity and the large processing format make laminate and ceramic based BGAs ideally suited for multichip modules. Mainframe computers have for years used the same base multilayer ceramic technology for their large MCMs and TCMs (Thermal Conduction Modules). The tape 5

6 package is processed on a large web and can support large packages. However, its current 2 layer structure will restrict it to few-chip packages. The attractive prices and capabilities of these technologies will help stimulate the move to MCMs as the known good die supply increases and our experience base with BGAs grows. JEDEC (Solid State Products Engineering Council) The JEDEC Ball Grid Array registrations are listed on page 7, Figure 2. For each JEDEC body size the number of connections along a side is listed as the matrix and the square of the matrix (or total connections) is listed under each package type. These numbers represent the maximum number of interconnections possible for each JEDEC outline. Actual matrix size and I/O may be less from some vendors or for some specific packages or applications. 6

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8 Plastic Ball Grid Arrays PBGAs (Plastic Ball Grid Arrays) are now available from several sources and that number is continuing to grow. PBGAs are laminate based packages that typically use a BT or Driclad (TM) resin for higher temperature stability and lower moisture absorption. Currently these packages all support wire bond chips. Flip chip laminate attachment is qualified at least one supplier and under development at several others. The simplest of these packages is a 2S/0P (2 Signal / 0 Power layers) laminate with a chip up wire bond and overmold as shown in Figure 3. The 2S/0P has the least wiring flexibility and is the lowest priced BGA product available. In this configuration it comes close to PQFP prices in some I/O and volume ranges. Especially when the total card assembly cost is included. Enhancement to the base 2S/0P structure give this package the capability to support applications well beyond anything possible in plastic flatpacks. Most companies break their laminate product lines into two categories. The standard packages are all variations of the chip up design. The most common enhancement to the standard package is the addition of thermal vias directly under the chip. This improves the thermal performance but reduced the number of interconnections available for signal. For 2S/0P laminates this impact may be minimal. In most cases the wiring limitations of the 2S structure that are restricted to perimeter signal vias are such that it can t reach all the inner I/O anyway except for use as redundant power or thermal enhancement. This is demonstrated in Figure 4, page 10, that shows the bottom surface wiring for a 2S package with a 1.5mm ball pitch. In this example the signal lines can go about 4 rows deep and supports signal wiring on 270 I/O out of the 400 available. With contant wiring groundrules, the ratio of unusable I/O increases with the number of interconnect and the size of the package. 8

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10 The next enhancement is a logical extension of the laminate technology. This is the addition of more signal and/or power layers to the laminate. The additional wiring capacity reduces or eliminates the unusable I/O limitations outlined before. The addition of power and ground layers reduce the power distribution drops and inductance for improved electrical performance. The power and ground layers also improve the impedance control of the transmission lines. Typical applications with power planes can support anywhere from 35 to 80 ohm impedance designs. The "high performance" packages are characterized by the cavity down design as shown in Figure 5. Use of these packages are driven primarily by thermal requirements. As covered in the thermal section of this document. A cavity down design with the die attached directly to a copper heatspreader can dissipate about 4 times more heat than a chip up design in the same environment. The disadvantages of the cavity down designs are size and cost. For an equivalent number of I/O the cavity down package must be bigger to make up for the unusable area under the cavity. Figure 6 shows a 32mm cavity down package with 225 I/O. Depending on the space constraints of each particular application this increased area could adversely impact the next level design. However, there will also be cases where the larger package might support a simpler card due to the larger fanout area. In the Figure 6 example the same die without a cavity down could be packaged in a 21mm BGA package. This 2.3X larger package drives an increased carrier cost. Plus the cavity itself drives additional processing cost and complexity. 10

11 Flip chip packages offer the size and cost advantage of the chip up designs and the thermal advantages of the cavity down designs. The flip chip approach also eliminates the long inductive wire bond leads for improved electrical performance. The chip joining process is a batch operation and has a relatively low cost curve with increasing I/O. These advantages are really independent of the base carrier material and are applicable across all packages described in this section. 11

12 Ceramic Ball Grid Array Multilayer Ceramic (MLC) is the base technology for the CBGA (Ceramic Ball Grid Array) and CCGA (Ceramic Column Grid Array) packages currently offered. This is the same MLC technology base that has been used and proven for over a decade in Thermal Conduction Modules (TCMs) and Multichip Modules (MCMs). Some of those TCM and MCM applications drove substrates with over 50 layers of signal and power, over 2000 pins and supported over 100 chips. Today's CBGA are a few chip or single chip modules that are typically 4 to 12 layers instead of over 50 layers. This makes them cost competitive with PBGA packages of equal function. That plus the years of experience and proven reliability of this technology is a major advantage of the ceramic BGA and CGA products. The number of layers in a given package is driven by the I/O, chip size and electrical requirements. As with most package types the ratio of chip size to I/O will determine the escape requirements on the substrate. This will help determine the layer count. Large chips with low I/O counts and without any electrical enhancement can be supported with only 4 layers. This is effectively the minimum layer count available in aceramic package and is required for mechanical stability and handling. As the I/O count goes up additional layers can easily be added to support them. In addition to signal layers, power and ground layers can be added to the design to improve the electrical performance. These power planes function as reference layers to provide impedance control for the signal lines. They also serve to reduce the DC power distribution drops and the power distribution inductance. Further electrical enhancements can be accomplished with the addition of decoupling capacitors to the module. 12

13 There are 2 prime card attach technologies for ceramic grid array modules as shown in Figure 7. While both techniques support industry standard FR4 cards and utilize standard surface mount assembly processes. They differ from the standard PBGA card attach in a small but important way. The CBGA consists of a high melting point solder (90/10 Pb-Sn) ball attached to the ceramic carrier and the FR4 card with aneutectic solder. This 90/10 solder ball doesn't reflow during module or card assembly and thus provides a standoff between the module and the card for improved reliability. It also provides clearance under the module for easier cleaning after card assembly. This standoff accommodates the mechanical strains generated during normal power cycling due to the Coefficient of Thermal Expansion (CTE) mismatch between ceramic and FR4 and any mechanical flexing. Unlike PBGA packages, whose maximum strain is under the die, the worst case locations for this stress is always at the outside corners of the package and is chip size independent. For most applications up to around 500 to 600I/O the ball standoff provides sufficient reliability. 13

14 The CCGA technique is a 90/10 solder column attached to the module and card with eutectic similar to the BGA solderballs. The columns are.5mm in diameter and up to 2.2mm in height. They are assembled to the card using the same standard attach processes and card specifications. The column provides a larger standoff and is about 10X more reliable in thermal fatigue than the CBGA structure. Users should choose the CCGA for applications with high delta Tj and thermal cycle requirements or for applications with greater than 500 to 600 I/O. Figure 8 shows the thermal fatigue comparison of CBGA vs. CCGA for a 625 I/O 32.5mm package. 14

15 Figure 9 shows the delta temperature field conditions supported by a 25mm 313 I/O module with a 100 PPM EOL cumulative fails. Although CGAs are available for any body size. BGAs are usually more desirable wherever they meet the reliability requirements. The BGAs are more robust and less prone to handling damage. Their lower height of less than 2mm also makes them more attractive for low profile applications. Users should review their exact use condition and failure rate objectives with their supplier to determine the right interconnect technique. Ceramic packages offer the additional flexibility of several encapsulation options including hermetic packages. The ceramic substrates are not as susceptible to moisture induced defects or die cracking currently associated with PBGAs. Tape Ball Grid Array The Tape Ball Grid Array (TBGA) or Tape Array Package (Trade Mark) package combines the advantages of multi-layer TAB packages with a BGA footprint. This avoids the card assembly concerns that has constrained the growth of higher I/O perimeter TAB packages. The result is an enhanced electrical package that is both thin and lightweight with the simpler BGA card assembly. A typical 300 I/O TBGA package would have a module height of 1.45mm above the board and a weight of 2 to 3 gms. This is for a module without a coverplate or heatsink. A TBGA cross-section is shown in Figure

16 The current TBGA products offered by IBM Microelectronics Division range in size from 21mm to 40mm with I/O ranging from 192 to 736. The BGA balls are offered on both 1.5mm and 1.27mm spacing to match similar BGA products described elsewhere in this section. In addition the technology is flexible enough to allow extensions to other package sizes or grids down to 1.0 mm or 0.8 mm. The Inner Lead Bond (ILB) can utilize either conventional peripheral thermocompression bonding or area array solder reflow attach like IBM's C4 technology. Also, the packages coefficient of thermal expansion (CTE) is matched to the card for high reliability. The tape's 2 levels of metalization provides a functional ground plane that is standard. The base polyimide material has a dielectric constant of 3.0. These attributes lower the effective power supply inductance and supports an impedance range from 45 to 60 ohms matching most card technologies. TBGA thermal extensions are achieved with a coverplate or heatsink that is bonded directly to the back of the chip with a thermal adhesive as shown in Figure 10. This provides a very low internal thermal resistance for maximum heat dissipation. The next level of assembly is similar to other BGA and SMT components. TBGA packages can be assembled to a card along with other SMT components and does not require any specialized placement equipment. It also uses standard SMT attachment materials and reflow equipment. 16

17 Section 2 Array Package Applications The following is a summary of application windows/advantages seen by the use of array packaging. It is taken from a presentation and discussion held at a HDP User Group Array Workshop. It provides a good synopsis of opportunities and challenges. BGA Benefits Summary: BGAs provide significant module assembly yield benefits Results so far support <10ppm assembly capability BGAs provide advantageous interconnect density. 1.5 mm BGA equal or superior to 0.4 mm QFPs above -140 IO 1.27 mm BGA equal or superior to 0.4 mm QFP above ~75 IO 1.00 mm BGA equal or superior to 0.3 mm everywhere (If designed per JEDEC specifications) Solder joints and packages are reliable in proper design space. Modeling Results show BGA's can provide superior heat dissipation to PQFPs Up to 4 watts without 1-2 m/sec. (Thermal vias) Up to 2 watts without 1 m/sec. Up to ~4 watts with enhanced 0 m/sec. BGA mechanical integrity superior to peripheral leaded devices; No bent leads Greater intrinsic capability for meeting coplanarity requirements. Device test does not damage leads BGAs preferred over 0.4 and 0.3 mm devices. Short Term BGA Issues Current package integrity improvements expected: Popcorning, Moisture controlled to < 0.1% Floor life, ~72 hours floor life, moisture absorption Missing balls; Reported by others but never seen at Digital; yet BGAs are not inspectable Good! They don't need to be. Devices offered in BGA format are rare. BGA packaging costs higher than PQFPs today. Need to reach cost parity. The BGA "Catch 22" Device suppliers waiting for market demand. Device customers waiting for product availability and costs. RISK: If BGAs do not dominate vendor package offerings for low power moderate IO devices, we may need to introduce 0.4 mm and 0.3 mm TQFP assembly & test processes. 17

18 References 1. "Surface Mount Array Interconnections for High I/O MCM-C to Card Assemblies, by T. Caulfield, J. Benenati and J. Acocella, ICEMM Proceedings, "Solving I/O Density Problems Using MLC Packages", by F. Cappo and J. Milliken Surface Mount Technology, June "Ball Grid Array: The New Standard for High I/O Surface Mount Packages", by Bruce Freyman and Robert Marrs, Japan International Electronics Manufacturing Technology Symposium, "The Current State of Laminate Based, Molded MCM Technology", by Philip Rogren, Hestia Technologies, IEEE/CHMT International Manufacturing Technology Symposium, IBM Microelectronics Division BGA product literature. 6. Amkor Electronics Inc. BGA product literature. 18

19 Why Choose BGA? Provides immediate yield improvement in manufacturing. No bent leads Relatively benign coplanarity requirements Coarse pitch; self registering components Preserves current assembly equipment capital base for 2 to 3 package generation (~5 years) Enables more aggressive savings in test strategy. Provides attractive alternative to deploying traditional COB and TAB assembly processes. Natural evolution to area flip chip assembly DCA. Buys time for "Know Good Die" implementation. Eliminates potential need to form leads at module assembly. Design benefits in lower inductance and lower thermal resistance. Future Challenges for BGA Package Integrity: Determine appropriate application limits for various Configurations (i.e. over molded, tape, ceramic) Solve popcorn risk Provide adequate floor life (re. moisture absorption) Broaden standard package offerings Readily available qualification data per package family Very low die functional DOA rates (< 100 ppm) Error free packages; no missing balls 19

20 Extended Package Capability: Reduce pitch while increasing IO count Keep max. ball field < ~33 mm square Reduce package margin size to JEDEC specifications Provide thermal via option for any IO count offered Add multi-tiered cavity down design with heat slug Develop reliable low profile BGA < 1.5 mm height (Competitive with low profile COB and TQFP) Later; Column grid arrays to extend size and power dissipation. 20

21 Conclusions BGAs offer a viable alternative to other S.M. packages. Some technical issues need to be resolved but there are no show stoppers. Volume issues will/can be resolved with real demand. 21

22 Section 3 Electrical and Thermal Guidelines Introduction This section of the design guideline addresses electrical and thermal performance criteria which will aid in the selection of ball grid array packages. A set of relationships is presented along with generalized rules to follow when selecting package options during the design process. Published papers, books and other documents are referenced for more in-depth study and a glossary of terms and definitions is provided. Performance capabilities and limitations associated with geometry, material properties and configuration alternatives are discussed to assist the design team in identifying the best package to satisfy the application requirements. Scope This document includes information culled from industry sources on ball grid array packages in use or destined for use in the semiconductor industry. The packages listed will be presented with thermal and electrical data information, referenced to the source. Comparisons with other surface mount packages will be included where applicable. This document is not meant to be a comprehensive collection of all possible configurations of the ball grid array package, but instead, a guideline for the most commonly used styles. Typical package styles and configurations are listed below. PBGA (PLastic Ball Grid Array) Encapsulation Styles Overmolded Globtop Lid Seal (B-Stage) Ball Material Low Temperature Solder (63/37) CPBGA (Cavity PLastic Ball Grid Array) Encapsulation Styles Globtop Lid Seal (B-Stage) Ball Material Low Temperature Solder (63/37) CBGA (Ceramic Ball Grid Array) Multilayer Ceramic Encapsulation Frit Seal Solder Seal Ball Composition High Temperature Solder (90/10) Low Temperature (63/37) TBGA (Tape Ball Grid Array) Single Layer / Two-Layer Tape Encapsulation Lid Attachment Heat Sink Attachment Ball Composition High Temperature Solder (90/10) 22

23 The scope of this document offers the following measures: Identify the variables affecting thermal and electrical performance Provide first order relationships between these variables derived by synthetic and empirical means (models and measurements) Provide rules, limits, and capabilities by which the performance criteria can be with reasonable accuracy Supply references to documents which provide specific technical information Provide a glossary of terms and definitions Thermal Characteristics of BGA Packages Thermal performance is a key issue in the implementation of BGA packages. This section provides typical operation limits for the various configurations which can be compared to other surface mount packages. Thermal enhancements are also observed for behavior using thermal resistance (ja) as a metric. Nomenclature The term "substrate" will be used to denote the package. The term "PCB" will be used to denote the printed circuit board which the package is mounted on. A. Θja requirements and power dissipation The following two graphs - Figure 13 & 14 - show the relationship between power dissipation and thermal resistance, with a defined junction temperature of 125ºC. This information can be used to judge the package thermal capability needed to satisfy design requirements. Figure 13 shows thermal resistance requirements for a given power dissipation at an ambient temperature of 70 C for up to 10 watts. Figure 14 is the same data for power dissipations to 100 watts for ambient temperatures of 25 C, 55 C, and 75ºC. 23

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25 B. Typical Thermal Performance of BGAs The following information is helpful in choosing a BGA technology and to determine if thermal enhancement is needed to satisfy the design rules. Several BGA packages are compared with ja as the metric. Table 1 is a list of the BGA package types with a description of each configuration. Figure 15 shows thermal resistance ranges for a variety of BGA packages sorted by package type. The data shows that there is a wide range of thermal resistance capability in the BGA package family. Figure 16 presents the same data, sorted by thermal resistance. Here we see that the pin count (thus the overall geometry) of a BGA package does not limit the performance that can be gained with the addition of various thermal enhancements. C. PCB Considerations When selecting a package, be sure to keep in mind the end user mounting surface. The printed circuit board has a large effect on the thermal resistance of BGA packages. In fact, thermal enhancements such as vias are not effective unless the PCB is designed to take advantage of them. Thermal conductivity of the printed circuit board is increased as layers are added. Ground or power planes add more copper to the board, thereby increasing thermal conductivity, decreasing the thermal resistance of the component. Table 2 shows the calculated thermal conductivity of typical FR-4/Cu laminate circuit boards (5). 25

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27 The board in this study is assumed to have a thickness of 1.27mm (0.050 ) and the copper is assumed to be 36um (1.4mil) thick. Figure 17 shows the effect of increasing the thermal conductivity of the PCB on 169 and 225 pin BGA packages. This effect is significant and should always be considered. Copper coverage and thickness is a primary factor in these calculations. See reference (5) and (6) Jim Andrews for details on PCB thermal conductivity and other environmental effects. 27

28 D. Package Power Dissipation Capability The following graph (Figure 18) illustrates the power handling capability of BGA packages based on 125ºC junction temperature and ambient temperatures of 23, 55, and 70ºC for the configurations listed in Table 1. Figure 19 is the same data sorted by power dissipation capability. 28

29 E. Materials and Environment Package Material Properties Physical properties of package materials are necessary to develop models and to aid in estimating the thermal performance of a chosen package configuration. Table 3 lists thermal conductivities for common materials used in BGA package manufacture and the reference for the listing. The values listed in Table 3 represent typical materials at or around 25ºC. For the utmost accuracy it is necessary that the references and other documents are studied. Geometry Although geometry of the package will have an effect on the thermal performance, it does not necessarily limit the capability of a given package style. Thermal enhancements such as external heat sinks or the addition of thermal vias to the package substrate can increase the power handling capability of the package significantly (Figure 15 and Figure 16). It is also noted (Figure 17) that the addition of highly conductive layers (planes) to the PCB is necessary to take advantage of the substrate thermal vias. Substrate size alone cannot be directly related to thermal capability, as many other attributes of the package contribute to the heat transfer from the package. For instance, as the number of vias in the substrate increases, the effective thermal resistance decreases. Spacing and size of the vias also affect thermal performance. As the size of the vias in the substrate increase, or the distance between the vias decreases, thermal resistance will decrease, not neglecting the printed circuit board effect. In general, BGA thermal performance is not limited by geometry, but is heavily dependent on environment and mounting conditions. Strict thermal design rules can be achieved with most pin counts through the use of thermal vias and careful board layout, or with heat sinks or other thermal enhancements such as forced air. Cavity down designs typically offer the best heat transfer mechanisms due to the direct heat flow path between the die and the external heat sink. 29

30 Electrical Performance Limits Electrical characteristics of BGA packages are dependent on many factors, but can be suited for higher performance devices when compared to other package styles with similar pin counts. Inductance is the primary factor in most designs related to switching noise effects. Self inductance of BGA package interconnects range from less than 2nH to over 11nH. Although there is a wide range of values, most BGA package designs can hold up to 50% of the signal line inductances to less than about 6nH. Using well defined return paths can drastically reduce inductance in PBGA designs. Mutual inductance of signal lines is reported to be very low, typically l00ph to 400pH in CBGA. Plane inductance can be very low due to the ability several planes in the substrate, and to assign specific pins to the planes. Published data shows power plane inductances ranging from 300pH to 400pH, and power supply loop inductances as low as 60pH, making the package attractive from a ground bounce perspective. Figure 20 shows signal line self inductances for package types shown in Table 4. Capacitance of signal lines is also an important design parameter. Data indicates typical capacitances to be in range of 0.4pF to 6.0pF depending on the geometry and materials used in the package design. Figure 21 plots signal line bulk capacitance for package types listed in Table 4. Resistance for BGA package configurations is reported to be from tens of millions to hundreds of millions, again depending on the geometry and materials. Characteristic impedance ranges from 35 to 60 ohms, with propagation delay reported from 50 ps to 250 ps. 30

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32 Section 3 References 1. T. Tarter and J. Pursel, 'Thermal Resistance Characterization of 169 BGA Packages, AMD internal publication, Jan R. Marrs, B. Freyman, J. Martin, "High Density BGA Technology", 1993 ICEMM Proceedings, pp J. Pursel, T. Tarter, Thermal Resistance Characterization of the 225 BGA", AMD internal publication, Jan IBM Microelectronics Division, Ceramic Chip Carrier Business Unit Presentation Material, Jan C. Wyland, "The Effect of PCB Thermal Conductivity on Package Thermal Resistance", 1993 IEPS Proceedings, pp K. Azar, S.S. Pan, J. Parry, H. Rosten, "Effect of Circuit Board Parameters on Thermal Performance of Electronic Components", 1994 Semi-Therm proceedings, p H. Shaukatullah, M. Gaynes "Experimental Determination of the Effect of Printed Circuit Card Conductivity on the Thermal Performance of Surface Mount Electronic Packages", 1994 Semi-Therm proceedings, pp B. Guenin, "Analysis of Board-to-Air Thermal Resistance", Presentation to JEDEC JC15 Committee, March J. Andrews, "Package Thermal Resistance Model: Dependency on Equipment Design", IEEE Trans. On comp., Hybrids, and Manufacturing Technology, "SRC / CINDAS, Microelectronics Packaging Materials Database", Diskette and Reference Manual, Purdue Center for Information and Numerical Data Analysis and Synthesis, West Lafayette, Indiana 11. Microelectronics Packaging Handbook, R. Tummala and E. Rymazewski, Van Nostrand Reinhold, B. Freyman, R. Pennisi, "Overmolded Plastic Pad Array Carriers (OMPAC): A Low Cost, High In Density IC Packaging Solution for Consumer and Industrial Electronics", /91 / , IEEE T. Costlow, "Ball Grid Arrays; The Hot New Package, But Questions Need Answering Before Designers Use It, Electronic Engineering Times, March 15,1993, p P. Venkatachalam, D. Perlman, "25-mm Solder-Ball-Connection Module for Improved Memory Performance, 1993 IEPS Proceedings, p W.Y. Yip, C.T. Tsai, "Electrical Performance of an Overmolded Pad Array Charrier (OMPAC), Proceedings, p R.L. Groover, C.C. Huang, A. Hamzehdoost, "BGA - Is it Really the Answer?", 1994 ITAP & Flip Chip Proceedings, p Electronic Materials & Processes Handbook, Charles A. Harper, Ronald M. Sampson, Second Edition, McGraw-Hill, Inc. New York, A. Mawer, R. Darveaux, A. M. Petrucci, "Calculation of Thermal Cycling and Application Fatigue: Life of the Plastic Ball Grid Array (BGA) Package", 1993 IEPS Proceedings, p

33 Section 4 Assembly Process Guidelines The major advantage of array packages is the improvement seen in process yields at assembly. Peripheral leaded devices at the mm pitch have process yields of ppm with well controlled process. Array packages will yield ppm with a tuned process. Array packages can be inserted into a standard surface mount process sequence if care if taken. Device and PCB coplanarity are key the factors that must be kept in the control window. The array package size will determine how tight that window must be kept. In addition to this some special care must be taken to assure that balls in the center of the package reach melt point. The following is a typical process sequence for array packages as well as standard surface mount components: 33

34 Stenciling For Ompac type packages that have Eutectic solder volume of 1900 cubic mils has been found to be acceptable. This can be achieved with a inch stencil and inch dia round openings. For devices which use a 90/10 high melting temperature solder balls a larger solder volume is necessary and inch stencil is preferred. Typical design rule: for a 30 mil solder sphere, the size range of solder pad should be 27 to Board warpage must be controlled to per inch max. A good characterization of the stencil process is required to assure adequate solder volume. Some users have employed the user of laser surface profilometry in establishing process settings. Some stenciling equipment has vision registration which may aid in assuring solder coverage. Both no clean and more highly activated paste have been used successfully in array package assembly. 34

35 Placement For array packages over pitch non-vision assisted placement has been used. This is dependent on the size of the card and the size of the BGA being placed. Experimental results have shown self alignment of the BGA does occur during the reflow process. The amount of off pad that can be tolerated is dependent on the device size but some data has shown that up to 2/3 off pad placement was realigned on 313 I/O devices. Vision placement also can provide an opportunity for solder ball inspection prior to placement. Although this is normally not problem. All conventional device handling and in process schemes are possible. Handling of Solder Column Carriers require more care and tray presentation is recommended. A key issue with Plastic array packages has been popcorning. (STORAGE OF THE DEVICES IN A CONTROLLED ATMOSPHERE IS RECOMMENDED!) Baking of the devices prior to assembly can be used as a way to drive moisture out prior to fusing. Floor storage critical times are dependent on ambient conditions. Each manufacturer will have to access his particular situation to establish rules. Device orientation is key. Some identifying feature should give positive checking. Two techniques that have been used are: the clipping of substrate corner and removal of corner solder ball. Some reference or target on the top edge of the device which registers the ball arrays on the bottom may also be useful when manual placement of the device is required. Solder Fusing The best results will be seen using a convection oven in which a uniform heat flux is applied to assembly. Thermocouple runs of test devices are recommended when setting up an initial process. A typical temperature profile for plastic BGA is shown in Figure 3. The thermocouple should be placed in the center of package and the temperature should reach at least 205ºC for 30 seconds. It is strongly recommended that cross section of joints also be made to assure proper metallurgical bonding has occurred. The use of nitrogen atmosphere in the soldering process is not essential but may be advantageous depending upon your process characteristics. Cleaning If you are using a flux system that requires cleaning, the key concern is access to area under center of the package. During solder fusing the ball will collapse from the original height of to (see Figure 4). It is important to remove both cleaning solvent and contamination. The effectiveness of your cleaning must be evaluated in a case by case basis as the size of the device and the location of the assembly will effect the outcome. 35

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37 Rework Package removal has been successfully done using a hot air system with a heated platen. The nozzle size is custom to the device. 200 mils of clearance is required around the array package site. Typical process sequence would be: 37