Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

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1 Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

2 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer Level package) Introduction to ewlb Innovations in ewlb platform ewlb Status at STATS ChipPAC fccube Summary 2

3 Next Generation Package Requirements (Mobile) Shrink on silicon: 32nm, 28nm 20nm Wafer size increase will impact FE assy PCB Area Mobile product form factor SIP/MCP solutions for early modem integration to reduce number of packages Handle increasing IO count per silicon area Package thickness mobile product form factor POP thickness reduction to < 1.0 mm including 2 die memory BGA thickness 0.8mm System Integration Enable easy platform design at customer level SI/PI at package level e.g. embedded decoupling Package ball-out in line with customer PCB build-up targets Thermal Performance Peak performance limited by package design Non-POP side-by-side memory solutions for tablets Exposed die heat spreader for AP New materials for increased thermal conductivity lateral and towards top and PCB 3D Integration Manufacturing and test solutions Backside processing, assembly and test of Wide-IO application processors Cost - Cost - Cost Cost reduction strategies for existing technologies 3

4 What is ewlb? Wafer Level Packaging technology, utilizes well developed wafer bumping infrastructure, with an innovative wafer reconstitution process to package Known Good Dice. Wafer level package, uses mold compound to support the fan-out I/Os. Fan-In WLP PKG size = Chip size ewlb/fan-out WLP PKG size > Chip size chip Fan-In Interconnects only - Number and pitch of Interconnects must be adapted to the chip size Only Single chip packaging solution ewlb expands the application space for Wafer Level Packaging! Fan-out Interconnects - #, Pitch of Interconnect is INDEPENDENT of chip size Single/Multi/3D chip packaging solution Improved Yield with KGD 4

5 ewlb Configuration comparison between fan-in vs. fan-out WLP - ewlb is the best fan-out wafer scale package Conventional WLP (fan-in) ewlb (fan-out) footprint larger than die 5

6 Form Factor, Performance & Integration Superior Solutions spanning the needs of mobile and other high-performance applications MCP configurations (down to 0.5mm) The thinnest 3D solution (down to 0.8mm) Scalable heterogeneous integration platform Leading cost/performance solutions (co-design optimized) Ultra fine ball pitch (down to 0.3mm) and maximum I/O density Excellent electrical and thermal performance High bandwidth wide I/O 3D incorporating TSV Enhanced reliability with advanced dielectric materials MLP-PoP configurations - both single and double sided 6

7 ewlb Products Portfolio 2D ewll 2.5D / Extended ewlb ewlb-mlp ewlb is a powerful wafer level and integration solutions platform 7

8 Next Generation ewlb 10mm/10mm line width and line spacing Plated Cu RDL 10mm Thin packaging solution (<0.5mm) 250mm thin ewlb for more design and routing flexibility 3D (double-side) ewlb Multi-die ewlb Embedded Passives 8

9 New packages in ewlb platform Small outline ewlb 3D SiP ewlb (double-side RDL) 2.4x2.4mm ewlb with 2x2mm die, 0.4mm pitch 200um ewlb PoP (ewlb + ewlb/bga) ewll ewlb-pop (single-side RDL) 9

10 Heterogeneous (2.5D) Integration TSV Interposer based solution Logic Analog Thin TSV interposer (TSI) fabrication Logic & Analog bumping Integration of multiple dies to the thin TSI with underfill Integration of TSI-tosubstrate with underfill Package Assembly ewlb based Solution Extended ewlb Logic Analog ewlb fabrication Integration of ewlb to the substrate with underfill Package Assembly Organic substrate ewlb provides a 2.5D integration platform superior to conventional TSV Interposer (TSI) based solutions in overall cost and process simplicity 10

11 Double-side 3D SiP ewlb Test Vehicle Specification PKG: 12x12sqmm, 0.5mm ball pitch Die : 3-die, 2 (3x3mm) + 3x4mm) I/O Count: L RDL (Top and Bottom both) Thickness 450um / 250um 1.2mm 450um 250um 250um Thin Bottom 3D PKG <1.0mm Picture of 3D ewlb PoP packages; Total less than 1.0 mm package height (including solder balls) Low profile 3D ewlb PoP (12x12mm PoP-bottom package) with less than 1mm thickness including solder balls. 11

12 Ultra Low Profile ewlb PoP: ewlb-pop ewlb 3D Interconnects ewlb-pop Successfully qualified for CLR & BLR Thin POP (250um pkg body thickness) Lower warpage during solder reflow cycles Flexibility in memory interface High routing density: L/S=10/10 (um) Compatible with ELK Good thermal performance Q JA 18~22( o C/W) Q JB 3~7( o C/W) for 12x12mm ewmlp) Memory + Si RDL 12

13 ewlb-pop Bottom Package Cross-Sections Si RDL 13

14 ewlb PoP Cross-Sections 14

15 ewlb Cost-reduction path Wafer size Available area increase (Area ratio ~ 2.35) Higher yield in 12 ( >99%) Unit cost decrease ( -25~30%) Stretch the limits 200mm size 8 HVM from mm HVM from New Technology (Panel, size under investigation) 15

16 FO-WLP (ewlb) / Embedded Die Substrate Fan-Out WLP (ewlb) Embedded Die Substrate No substrate Miniaturized and high performance Full module approach with free top surface In HVM 2009, Proven yield > 98% Batch/inline process of wafer level Replacing / Competing with embedding Embedding die in mold during assembly/packaging Simple logistics and supply chain Embedded Active or Chip-in-Substrate (CIS) Achieve PWB design miniaturization Need Cu plating on die Yield concerns of high density substrate Few modules seen in Japanese market since 2005 Embedding die in substrate by substrate manufacturer Complex logistics; how to involve substrate maker Supply chain Component testing Ownership 16

17 fccube - Value Proposition! High Performance l High I/O Density l ELK/ULK Reliability l Fab Node Compatibility Copper (Cu) Column with Pb-Free Cap High I/O density Very fine bump pitch to 80um Superior electro-migration resistance Green package Bond on Lead (BOL) Pad w/ Open SR Structure High I/O density Design rule relaxation Lower cost w/ layer count reduction And No SOP Elimination of ELK/ULK Damage on Advanced Si Nodes (40/28nm) -> 20N Scalability to Fine Bump Pitches down to 40um! Spanning a wide bump pitch spectrum using Cu-column FC TM Flip Chip Redefined Package Types fcbga, fcfbga (fccsp) fcpop / MLP(3D) TSV Mold Underfill (MUF) with Cu column bump Enhanced to fill fine gap (<50u) Cost savings / higher production throughput Potential package size reduction Optimization of Material Flow & Equipment Selection catered to Customer Design Higher production throughput Cost savings 2-Layer Laminate using no-sop, BOL, Open SRO Design 50% cost reduction vs std FC Relaxed substrate design rules Dense routing 17 17

18 fccube Technology Supports Full Range of Product needs Across all Fab Nodes and Bump Pitches! fccube Technology offers optional Interconnection methods: Mass Reflow or Thermo Compression Bonding Allows maximum flexibility in meeting key design requirements across all fab nodes & fine Bump Pitches Core fccube Technology Interconnect Structure Underfill Copper (Cu) Column with Pb-Free Cap, with BOL Pad and Open SR Mold Underfill (MUF) w/ MR & NCP w/ TCB Compatibility fccube Assembly Options Pkg. Types (fcfbga/ MLP/ fcbga) Fab Nodes Assembly Process Primary Benefit Mass Reflow (fccube-mf) Mainstream (infrastructure friendly) & Low Cost 80 40N- >28N - > 20N - > 14N Thermo Compression Bonding (fccube-tcb) Suitable for ultra-high density e.g. TSV Si-to-Si f-t-f/f-t-b bonding fccube Interconnect Option using Mass Reflow (MR) or Thermo Compression Bonding (TCB) offers flexibility to optimize cost / pitch / performance based on Si Node, I/O design, product timing., etc. 18

19 Summary Wafer level packaging is a key technology enabler for future heterogeneous integration with improved electrical performance in the thinnest 3D solution available. STATS ChipPAC started 200mm ewlb HVM in Started world s first 300mm ewlb HVM in 2010 and currently with yield at 99.8% Shipped over 600K (8 & 12 ) carriers to major mobile OEMs. Expanding capacity to meet strong market needs ewlb has an aggressive cost reduction path with aggressive annual cost reduction rate from an already competitive cost structure. Expand ewlb application area beyond mobile applications 2.5D, 3D, Interposer fccube: Powerful, cost-effective Flip Chip solutions platform with design optimizing flexibility 19

20 END of Presentation Thank You! Heinz-Peter Wirtz, Ph.D. Product & Technology Marketing Direct: Mobile:

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