Evolution of Wafer Warpage and Lattice Level Stress of Silicon Wafers with Through Silicon Via Structures along Various Process Integration Steps

Transcription

1 Evolution of Wafer Warpage and Lattice Level Stress of Silicon Wafers with Through Silicon Via Structures along Various Process Integration Steps Woo Sik Yoo WaferMasters, Inc. 246 East Gish Road, San Jose, CA

2 Outline Introduction Importance of Si stress monitoring along TSV process steps Impact of Si stress: Device Performance Variations, Reliability Problems and Yield Problems Parameters to be monitored Wafer level: Warpage Die level: Stress and carrier lifetime Experiment TSV sample preparation Optical Surface Profiling for wafer warpage Raman measurement for stress characterization Photoluminescence measurement for carrier lifetime Results and Discussions Geometrical factor CTE difference Cu grain growth Cu contamination Summary

3 Evolution of Wafer Shape along Various TSV Integration Process Steps a o Screen a o Effective Projection Distance > 8m OSP-300 Optical Surface Profilometer Wafer ID A B C D TSV Process Steps TSV Etch Oxide CMP TSV Cu Filling Wafer Profile Measurement Raman Stress Measurement TSV CMP + Nitride Cap E A B C D E After TSV After TSV CMP Before TSV Etch + Oxide CMP Cu Filling + Nitride Cap Vector Plot of Surface Normal Height Contour Map Wafer Curvature along Crystal Axes

4 Height Range ( m) Evolution of Wafer Shape along Various TSV Integration Process Steps Wafer ID A B C D E TSV Process Steps TSV Etch Oxide CMP TSV Cu Filling TSV CMP + Nitride Cap Wafer Profile Measurement Raman Stress Measurement A B C D E Before TSV Etch + Oxide CMP After TSV Cu Filling After TSV CMP + Nitride Cap A B C D E After TSV After TSV CMP Before TSV Etch + Oxide CMP Cu Filling + Nitride Cap [-1-10] [-100] Wafer Curvature along Crystal Axes [110] [010] [-110]

5 Intensity Raman Characterization of Si Stress The Raman frequency shift of 1cm -1 corresponds to 435MPa of stress and the wavelength shift of nm at 266.0nm nm at 325.0nm nm at 363.8nm nm at 406.7nm nm at 457.9nm nm at 488.0nm nm at 514.5nm nm at 568.2nm nm at 647.1nm nm at 676.4nm FOUP Opener FOUP Opener MRS-300 Multi-Wavelength High Resolution Spectrograph (Polychromator) Ar + Laser l3 Raman l2 Optics l1 Wafer Handling Robot Laser Mirror Auto Focusing Microscope & Wafer Stage Raman Optics Factors Peak Shift Peak Broadening Asymmetry: Ga/Gb Small Stress: s xx + s yy = -435Dw [MPa] Tensile Stress G a G b Raman Shift w 0 ~ 520.3cm -1 Compressive Stress Large

6 Raman Shift (cm -1 ) FWHM (cm -1 ) Intensity (Counts) Raman Shift (cm -1 ) FWHM (cm -1 ) Intensity (Counts) Raman Shift (cm -1 ) FWHM (cm -1 ) Intensity (Counts) Raman Characterization of Si Stress B C E Oxide CMP After Cu TSV CMP + Nitride Cap nm Excitation Raman Linescan Summary Stress Free TSV Openings TSV Openings Cu Filled TSVs

7 Raman Characterization of Si Stress Raman Shift FWHM TSV Opening 300x300 m 2 in 3 m interval Intensity Stress

8 Radiative and Non-Radiative Recombinations Good Crystallinity Good Passivation Strong PL Auger Process Photoluminescence Low Dopant Concentration Defects, Poor Passivation Dopant Variations Weak PL PL Intensity & Peak Position Variation

9 Intensity Intensity Intensity Intensity Radiative and Non-Radiative Recombinations Poor Passivation and/or Surface Damage Subsurface Defects and/or Implant EOR Damage Poor Passivation and/or Dopant Variations Poor Passivation and/or Poor Crystallinity and/or Heavy Doping 2.33eV 532nm 1.91eV 650nm 1.50eV 827nm 2.33eV 532nm 1.91eV 650nm 1.50eV 827nm 2.33eV 532nm 1.91eV 650nm 1.50eV 827nm 2.33eV 532nm 1.91eV 650nm 1.50eV 827nm ~1.5 m ~1.5 m ~1.5 m ~1.5 m ~4.0 m ~4.0 m ~4.0 m ~4.0 m ~10.0 m ~10.0 m ~10.0 m ~10.0 m

10 PL Intensity Maps around TSVs 650nm Excitation 827nm Excitation 2.33eV 532nm 1.91eV 650nm 1.50eV 827nm ~1.5 m ~4.0 m ~10.0 m Si Stress Dopants Defects Contamination Strongly influence carrier lifetime. PL spectra and intensity variation

11 PL Line Scan Spectra 2D & 3D Images 650 nm Excitation 827 nm Excitation 3D Images 2D Images 3D Images 2D Images TSV TSV nm 1.378eV 1400nm 0.886eV 900nm 1.378eV 1400nm 0.886eV

12 Summary Wafer level and lattice level stress evolution along various TSV process steps was non-destructively characterized. Wafer warpage: Optical Surface Profiler (OSP-300) Si lattice stress: Multiwavelength Raman Spectroscopy (MRS-300) Carrier lifetime: Multiwavelength PL System (MPL-300) Significant wafer warpage evolution was observed alongtsv process steps. Large Si stress variations near TSVs were measured after Cu fill, CMP and Cu anneal. Carrier life time shortening near TSVs were verified by multiwavelength PL characterization. Careful monitoring of important material parameters is strongly recommended during process development and production for quality control.

13 WaferMasters would like to thank Chang Hwan Lee, Seok Ho Jie, Sang Hoon Son, Jong Tae Kim, Hyung Won Yoo, Il Keoun Han and Chul Won Bang of SK hynix Jeff Gambino, Daniel Vanslette and Cameron Luce of IBM Microelectronics Bucknell Webb of IBM Research