Silicon Stress Metrology for Cu-TSVs in 3D ICs

Transcription

1 Silicon Stress Metrology for Cu-TSVs in 3D ICs Colin McDonough, Benjamin Backes, Pratibha Singh, Larry Smith, Wei Wang, and Robert E. Geer College of Nanoscale Science & Engineering, University at Albany, SUNY 257 Fuller Rd, Albany, NY SEMATECH *, 257 Fuller Rd, Albany, NY GLOBALFOUNDRIES Inc., Albany, NY

2 Effect of Thermal Stresses in a 3D-IC Stresses from TSVs crossing through active layer may cause failure or affect performance of nearby devices 3D integration with TSVs consists of a variety of materials with widely varying mechanical properties Thermal cycling during the fabrication process introduces thermomechanical stresses Coefficient of thermal expansion (CTE) mismatch Cu 17.7 ppm/ºc Si 2.61 ppm/ºc Biaxial Stress: TE T 2(1 ) A methodology to measure and model the evolution of thermally induced stresses throughout a 3D process flow is needed TSV Jonas Åberg, et al. COMSOL Multiphysics User s Conference, 2005, Boston. Daniel Bentz, et al. COMSOL Multiphysics User s Conference, 2005, Boston. F. Liu, et al. Electron Devices Meeting, Dec. 2008, San Francisco. 2

3 Determination of Keep-Away-Zone Stress induced mobility change in Si as well as build-up of stresses in TSV arrays requires the designation of TSV Keep-Away-Zones Minimum distance required between: TSV - TSV (Ensure mechanical reliability) TSV - Active devices (Minimize impact on carrier mobility) % Mobility Change for Cu TSV TSV - Active Device n-silicon Keep-Away-Zones p-silicon Minimum perimeter from solid, 5 μmcu-tsv where carrier mobility changed by more than 5% A.P. Karmarkar, X. Xu, and V. Moroz, IEEE 47 th Intl. Reliability Physics Symp., 2009 C. Okoro, et al. International Interconnect Technology Conference,

4 Si stress measurements were carried out using farfield micro-raman Stress fields associated with isolated TSVs and TSV arrays were evaluated Si Stress Measurements near Cu TSVs Raman stress profiling measurements were carried out on post-etch and post-cu CMP TSV test structures Thermal process steps used: Low temperature annealing step precopper CMP Post-CMP anneal step (optional) High temperature dielectric deposition after CMP (T dielectric ) 532 nm Active Device Region 1. Post-etch baseline 1D and 2D scanning 532 nm Active Device Region 2. Post M1 Etch 4

5 Raman Frequency Shift and Stress Relation Typically uniaxial or biaxial stress is assumed Raman peak shift from (001) backscattering (Uniaxial): (cm 1 ) 2 1 [ ps q(s (Pa) 11 S 12 )] Converts Raman peak shift to Stress Biaxial stress in x-y plane (σ x & σ y ): (cm 1 1 ) [ 2 ps q(s 9 11 xx S 12 )]( yyxx (Pa) yy ) 2 0 Phonon Deformation Potentials Si Elastic Compliance Tensor Elements counts Δω<0: tensile Δω>0: compressive p= -1.43ω 0 2 S 11 = 7.68E-2 Pa -1 q = -1.89ω 0 2 S 12 = -2.14E-12 Pa -1 r = -0.59ω 0 2 S 44 = 12.7E-12 Pa -1 ω t ω o ω c frequency (cm -1 ) Ingrid De Wolf (1996) Semicond. Sci. Technol

6 1. Stress maps for isolated TSVs: i. Effect of Si elastic anisotropy ii. Tensile-compressive transition near TSV 6

7 2D Raman Maps of Empty vs. Cu-filled TSV Y Position ( m) Si-Si Raman Shift (cm -1 ) of TSV (pre-fill) Si Empty via X Position ( m) Y Position ( m) Relatively uniform Raman shift profile after etch Si-Si Raman (cm -1 ) Shift of TSV (post Cu CMP) TSV processing induces negative Raman shifts away from TSV (blue) and positive shifts (green/red) Si Cu TSV X Position ( m)

8 2D Raman and Stress Maps of Cu-filled TSV Y Position ( m) Si-Si Raman (cm -1 ) Shift of TSV (post Cu CMP) Si X Position ( m) Cu TSV Y Position ( m) Biaxial conversion to Si stress from Raman shift (MPa) Four-fold symmetry due to Si anisotropy Results in higher tensile stress in Si along <110> directions 2D Stress Map of 5 m Round TSV (post Cu CMP) <110> direction X Position ( m) Compressive stress (green/blue) -90 compressive Tensile stress (yellow/red) tensile 8

9 2D Raman/Stress Map of Empty vs. Cu square TSV Distance ( m) Cu Distance ( m) Cu compressive Distance ( m) Distance ( m) tensile Biaxial conversion to Si stress from Raman shift (MPa) Four-fold symmetry due to Si elastic anisotropy and via shape Results in higher tensile stress in Si along <110> directions 9

10 2. Origin of TSV stress profile 10

11 Residual Stress in Cu TSVs Compressive stresses in Cu TSVs during processing result in yieldinduced strains in Si 1. Post-fill, high-t processing results in compressive strains in Cu TSV can induce yield in Cu (before Si). 2. Cooling of TSV and Si reduces Cu below res. 3. Effective compression in Cu can result in tensile stress in surrounding Si. TSV array Si Cooling Compressive strain in Cu results in tensile strain in Si y Cu Cu Si Heating res Cu Cu yield due to CTE mismatch Courtesy Paul Ho, Univ. of Texas at Austin 11

12 Residual Strain Profile versus Simple Cooling Measured Raman shift profile agrees with model for residual strain in Si due to temperature cycle of TSV Measured Raman shift does not agree with simple cooling of TSV from a higher-t zero stress state Raman Shift (cm -1 ) Residual Strain (cycled to 350 o C) Thermal Strain (cooled from 350 o C) E( Si Cu) T r 2(1 ) a r Position ( m) Simple concept of zero stress temperature likely not sufficient to characterize TSV stress profile 12

13 Raman Profiles & FE Simulation for Isolated TSV 5um Isolated TSVs - Horizontal Scans Si-Si Raman Band Shift (cm -1 ) TSV Die 1 & 2 FEA Stress free Position ( m) FE model of TSV-induced stress profile in Si (350 o C anneal) agrees with experimental Raman data from Dies 1 & 2 13

14 Raman Profiles & Die-to-Die Variation um Isolated TSVs - Horizontal Scans Si-Si Raman Band Shift (cm -1 ) Gray area denotes std. deviation seen from Raman measurement & die-to-die variations TSV Position ( m) Experimental variations of stress profile measurement error & die-to-die Entire dataset exhibits qualitative agreement with FE model (residual strain model) All Die Std. Dev (All Die) Die 1 & 2 FEA Stress free 14

15 Stress Profiles & FE Simulation for Isolated TSV Tensile Stress (MPa) Compressive Position ( m) Compressive strain in Si at isolated TSV > 100 MPa Tensile strain in Si near TSV < 50 MPa Die 1 and 2 All Die FEA (350 o C Anneal) 15

16 3. Stress Mapping in TSV arrays 16

17 Four Linear Round TSVs Horizontal Stress Profile Simulation Measurement 5um 4-Linear Array Comparison - Horizontal Scans Side tensile stress At ~ -0.1 cm -1 Middle tensile stress At ~-0.2 cm -1 Absolute and relative magnitudes of side tensile stress and middle tensile stresses differ between simulation and measurement Si-Si Raman Band Shift (cm -1 ) Side tensile stress at to -0.05cm Position ( m) Die 1 Die 2 Stress free 17

18 Four Linear Round TSVs Vertical Stress Profiles Simulation 0.08 Measurement 5um 4-Linear Arrays Comparison - Vertical Scan Peak tensile stress at ~-0.05cm -1. Recall: Peak side tensile stress for horizontal profile at -0.1cm -1 Si-Si Raman Band Shift (cm -1 ) Peak tensile stress from ~-0.04cm -1 to -0.06cm Position ( m) Die 1, TSV 1 Die 1, TSV 2 Die 2, TSV 1 Die 2, TSV 2 Stress free 18

19 Square TSV Arrays Simulation (infinite array) Measurement (4x4 array) Middle tensile stress at -0.4cm Y Si-Si Raman Band Shift (cm -1 ) Middle tensile stress values measured are at least 4x less than the simulation result Middle tensile stress is larger than the side stress which agree with simulations um 4x4 Array Comparison - Horizontal Scans Middle tensile stress values less than -0.01cm Position ( m) Die 1 Die 2 Stress free 19

20 0.08 5um 8x8 Array Die1 - Horizontal Scans 8x8 Array Die 1: Horizontal Comparison 0.06 Si-Si Raman Band Shift (cm -1 ) Position ( m) Inner profiles show larger tensile shifts than profiles on edge of array Some variation seen between TSVs Inner 1 Inner 2 Edge 1 Edge 2 Stress free 20

21 0.08 5um 8x8 Array Die 1 - Vertical Scans 8x8 Array Die 1: Vertical Comparison 0.06 Si-Si Raman Band Shift (cm -1 ) Position ( m) Inner 1 Inner 2 Edge 1 Edge 2 Stress free Inner profiles show larger tensile shifts than profiles on edge of array Less variation seen between TSVs compared to horizontal profiles 21

22 4. Thermal Evolution of Stress Near TSVs 22

23 Significant variation in Raman shift for low T ex situ anneal (150 o C) Reduced variation in Raman shift for high T ex situ anneal (350 o C) Ex situ anneal can induce Cu deformation Complicates comparison w/ FE model Si-Si Raman Band Shift (cm -1 ) Ex Situ Annealing (Square TSVs) Square TSV Pre-anneal 150 o C anneal 250 o C anneal 350 o C ex situ anneal Stress Free Position ( m) 23

24 0.6 Depth Profiling of TSV-induced Stress Preliminary Data Wavelength Comparison Laser wavelength (nm) Active Device Region Penetration depth (nm) Si , ~ ~1 Si-Si Raman Band Shift (cm -1 ) Position ( m) Comparison between 633nm, 532nm, and 325 nm light sources nm data exhibits lower tensile stress away from TSV (larger depth averaging) 325 nm data exhibits much larger tensile stress away from TSV (surface specific) Stress free 24

25 Summary 1. RT TSV stress profile in Si results from residual stress due to plastic yield of Cu. 2. Good agreement (profile and magnitude) between FE simulation and Raman stress profile data for isolated TSVs. Development ongoing for TSV arrays. 3. Stress in Si strongly affected by number and density of neighboring TSVs (linear vs. 2D arrays). 4. Ex situ annealing studies of post-process TSVs shows reduction in TSV-induced stress in Si for isolated TSVs. Comparison with experiment via ex situ anneals complex. Utilize in situ annealing approach for ongoing work. Funding Support Acknowledgement SEMATECH SRC 25