Reliability Challenges for 3D Interconnects:

Transcription

1 Reliability Challenges for 3D Interconnects: A material and design perspective Paul S. Ho Suk-Kyu Ryu, Kuan H. (Gary) Lu, Qiu Zhao, Jay Im and Rui Huang The University of Texas at Austin 3D Sematech Workshop, Burlingame, March 17, 2011 The University of Texas at Austin 1

2 3D Integration Interposer Memory stacks (Samsung) Intel 300 mm multicore processors J. Bautista, 3D Technology Workshop 2009 TSV memory in mobile phone, 30% thinner 3D integration provides the memory bandwidth required for processor A wide variety in 3D design and application Reliability Issues? The University of Texas at Austin 2

3 Factors impact 3D reliability 3D stack and bonding Materials and configurations Processing of 3D structures Stress impact on reliability Processing induced stresses: via middle and TSV Piezoresistivity effect Keep out zone for devices Interfacial delamination and cracking Effects of metallization, configuration and design Cu plasticity TSV metallization Chip-package interaction Test structures and metrology The University of Texas at Austin 3

4 Factors Impact 3D Reliability 3D stack and bonding TSV Micro-bump interposer Thin wafer handling Die/die bond Wafer/wafer bond. S. Cho, RTI 3D Workshop 12/2010 The University of Texas at Austin 4

5 Factors Impact 3D Reliability Materials and configuration Cu via fill Void free fill Electroplated Cu Grain growth Elastic anisotropy Plasticity TSV metallization Cu vs W Annular TSV Barrier/seed metals TSV joint Cu/Cu vs IMC bond EM and SM S. Cho, RTI 3D Workshop 12/2010 The University of Texas at Austin 5

6 Factors Impact 3D Reliability Processing of 3D structures Via middle process Processing induced stresses Cu/ CTE mismatch TSV pop-up cracking Keep-out zone Packaging Induced stresses Thin die multi-stack Chip-package interaction Cu leakage and contamination Device degradation Interconnect TDDB Keep-out zone Top- (~10 µm) Bottom- (~630 µm) Via last TSV (Fraunhoefer) Handbook of 3D Integration TSV pop-up Cu leakage TSV pop-up (Tezzaron) S. Cho RTI Workshop The University of Texas at Austin 6

7 S. Cho, RTI 3D Workshop 12/2010 The University of Texas at Austin 7

8 3D Integration: Via Middle Process Step A Step B Step C Step D Step E TSV materials: Conductors: Cu, W Insulators: TEOS, polymers Barrier/adhesion: TiN, TaN Geometric aspects: High aspect ratio Thin wafer (~ µm) Diameter (~1-50µm) Pitch (~3-100µm) R. Jones et al. IEEE CPMT 2009 The University of Texas at Austin 8

9 Processing Induced Stress mulation: Front de TSV TEOS/barrier layer deposition 400~430ºC Cu 30ºC 200ºC Cooling down to 30ºC Cu CMP Capping layer deposition 150ºC CVD of 400ºC Cooling down to 25ºC 2 µm 1 µm 10 µm TSV diameter: ~2 µm TEOS TiN Al Cu Critical steps for interfacial delamination and silicon cracking The University of Texas at Austin 9

10 Processing Induced Stresses CVD of 400ºC Shear Stress σ xy Normal Stress σ x Cooling down to 25ºC (MPa) (MPa) y x y x TSV diameter: 2µm Stress controlled by CTE mismatch T, via material and size important Shear stress and tensile normal stress at TSV corners can induce TSV popup and cracking Near surface stresses degrade device performance Keep out zone The University of Texas at Austin 10

11 2D Stress Solution of ngle TSV No elastic mismatch between and Cu Infinite matrix TSV: radius R σ σ r z = σ = σ θ rz E α T = 2(1 v) = σ θz = 0 r θ Stress in R r 2 y x Normal Stress σ x Shear Stress σ xy Stresses controlled by CTE mismatch between TSV and ; via size, material and T important. (µm) (MPa) The University of Texas at Austin 11

12 FEA: Effect of Wafer Thickness on Stress σ r σ rz H/D=2 H/D=10 At the Cu/ interface, the opening stress σ r and the shear stress σ rz decrease with the aspect ratio H/D. TSV with a higher aspect ratio is more prone to delamination and cracking. The University of Texas at Austin 12

13 Potential Fracture Modes of TSVs Cu Cu Cu R-crack C-crack Interfacial crack Pop-up of TSV R-crack may grow in during heating (ΔT > 0) when the circumferential stress is tensile (σ θ > 0). C-crack may grows in during cooling (ΔT < 0) when the radial stress is tensile (σ r > 0). Interfacial crack can grow during both heating and cooling, leading to pop-up of TSV. The University of Texas at Austin 13

14 Stresses near Wafer Surface Cooling stresses: T = -250ºC σ r σ rz Cu Cu σ r Stress Contour σ rz Stress Contour Cu Cu T = 250 K T = 250 K Positive opening stress along Cu/ interface Concentration of the shear stress at the surface/interface junction TSV stresses are 3D in nature with distinct near surface characteristics, which cause degradation of carrier mobility and device performance. The University of Texas at Austin 14

15 Piezoresistivity Effect in MOSFET Device MOSFET (b) (b) 3 J 1 J 1 E 1 2 (b) 1 S ρ µ = = ρ µ Channel + D ( σ + ) 1 1 π σ lσ1 π t 2 3 Directional dependent piezoresistivity coefficient ρ of (001) n-mosfet & p-mosfet Normal stresses in MOSFETs induce resistance (or mobility) change in the devices. Piezoresistivity coefficient ρ is highly directional dependent. The University of Texas at Austin 15

16 Raman measurement of TSV stresses Comparison of FEA and Raman Shift σ +σ θ r σ + σ (MPa) = -470 ω ( cm r θ FEA for TSV is based on an elastic and anisotropic, T= -100 o C. For TSV, σ r and σ θ are opposite in sign and have distinct 3D characteristics. They define KOZ. Raman measures the near surface stresses σ r + σ θ in only; stresses in Cu have to be independently measured. 3 1 ) ~50 μm Oxide layer: 0.8~1 μm 9.45 μm 8.78 μm 6.92 μ m Work in collaboration with H.Y. Son and K.Y. Byun, Hynix The University of Texas at Austin 16 Height=56 µm

17 Mobility Change in p- and n-mosfet Piezoresistivity coefficients (10-4 MPa -1 ) P-MOSFET [110] N-MOSFET [110] Direction π // [110] π [110] n-mosfet p-mosfet µ = µ + ( σ + ) 1 π σ lσ1 π t 2 3 Mobility change in MOSFETs is derived from the TSV-induced thermal stresses near wafer surface (3D FEA). Assuming devices are aligned along [110], the mobility change in p- MOSFETs is more severe than in n-mosfets. The University of Texas at Austin 17

18 Keep-out Zone (KOZ) for p-mos // [110]: Effect of TSV Scaling Effect of TSV diameter Effect of TSV height Effect of TSV Diameter D f : KOZ for p-mos // [110] Df = 10 µm Df = 20 µm Df = 30 µm KOZ = A* D f Effect of Wafer Thickness H: KOZ for p-mos // [110] H = 20 µm H = 50 µm H = 100 µm H = 200 µm KOZ (µm 2 ) KOZ (µm 2 ) D f (µm) TSV aspect ratio H/Df KOZ is calculated based on a criterion of10% decrease in mobility. KOZ scales with the square of TSV diameter. KOZ reduces at a low aspect ratio of TSV (A.R. < 3). KOZ is larger for analog devices than digital devices. (A. Domic, RTI Workshop, 2010) The University of Texas at Austin 18

19 Keep-out Zone (KOZ) for p-mos // [110]: Annular TSV 800 Effect of Annular Structure: KOZ for p-mos // [110] D i = 0 (Full TSV) D i = 10 µm KOZ (µm 2 ) D i = 15 µm KOZ = B* (1-η 2 ) η = D D i f η 2 Area of KOZ can be reduced using an annular TSV structure. The University of Texas at Austin 19

20 Reliability based on Fracture Mechanics G > or < Γ Griffith Criterion Energy release rate (ERR or G): thermodynamic driving force for crack growth, the elastic strain energy released per unit area of the crack; calculated by FEA or other methods. Fracture toughness (Γ): material resistance against cracking, an intrinsic property of the material or interface; measured by experiments. Numerical methods, e.g. FEA and cohesive zone are being developed for calculating G. Experimental techniques, test structures and metrology for measuring Γ at TSV interfaces have to be developed. The University of Texas at Austin 20

21 TSV Interfacial Fracture Heating cycle: T > 0: Interfacial crack driven by shear stress σ rz σ rz σ rz z Cu z Cu r Shear stress σ rz concentration near surface r Cooling cycle: T < 0: Crack driven by both shear stress σ rz and radial tensile stress σ r Mode I + Mode II fracture (more prone to cracking) z r σ rz σ r The University of Texas at Austin 21

22 Steady-state Energy Release Rate (ERR) ΔT Axial symmetric crack Fully filled Cu TSV, Cooling Cu Energy Release Rate G SS (J/m 2 ) 35 Assumption: 1. Linear elasticity 2. Infinite long fiber, long crack length Steady-State ERR, G SS : G G = E( α T ) 4(1 ν ) SS D f = D f 2 E( α T ) (1 + v) 8(1 ν ) SS D f 2 Cooling Heating T ( o C) The University of Texas at Austin TSV diameter, D f (µm) ERR increases with thermal load and TSV diameter. 30

23 Steady-state Solution for ERR FEA modeling of G : (ΔT= -250ºC, cooling ) TSV diameter, D f : 5~20 µm Crack length: 0~30 µm 400 μm Axial symmetric crack 200 μm Energy Release Rate (J/m 2 ) Cu TSV, T= -250 o C Crack Length (µm) G can exceed 10 J/m 2 for D f > 20 µm with crack length reaching the steady state D f = 20 um D f = 15 um D f = 10 um D f = 5 um Dash Lines: Steady-State ERR The University of Texas at Austin 23

24 Delamination of TSV Structures Cu Cu Cu Fully filled TSV Annular TSV TSV w. polymer liner TSV w. nail head Crack driving forces for various TSV interfaces were evaluated using FEA simulations and analytical solutions. The University of Texas at Austin 24

25 TSV Pop-up Mechanism TSV protrusion oxide (a) Cooling (b) Heating (c) TSV pop-up Courtesy Tezzaron TSV pop-up process: (a) Vertical interface debonding under cooling, (b) Horizontal interface debonding under heating, (c) TSV pop-up after repeated thermal cycles. The University of Texas at Austin 25

26 S. Cho, RTI 3D Workshop 12/2010 The University of Texas at Austin 26

27 Effect of TSV Metals TSV D f = 20 μm Material CTE (ppm/k) Young s Modulus (GPa) Poisson s Ratio Al Cu Ni W G SS ( α T ) 2 E D f ETSV = f, ν TSV, ν 4 E The effect of thermal mismatch dominates the energy release rate. The advantage of W over Cu is balanced by its brittleness and the lack of plasticity in deformation. The University of Texas at Austin 27

28 The University of Texas at Austin 28

29 Cu Interface Fracture Energy The debond energy of the Cu interface depends on the material at the interface. It can exceed 40 J/m 2 for a strong CoWP interface. The void growth rate under electromigration can be correlated to the bonding strength at the interface. Stronger interface, slower mass transport. M. Lane, R. Rosenberg, MRS Proc Cu interface can be strengthened with proper barrier layer materials The University of Texas at Austin 29

30 Interface Fracture Energy, G c (J/m 2 ) Cu/TaN Interface Fracture Energy σ ys r pl σ 2 ys as h Cu Plastic zone Γ o = 5 J/m Copper Layer Thickness (µm) h Cu O 2 TaN = D 20 The Cu/TaN interface can be significantly strengthened with plasticity. With plasticity, Cu can yield to improve the interfacial toughness. For Cu TSV with TaN barrier and 10 µm dia., the fracture energy increases from 5 J/m 2 to 40 J/m 2. M. Lane, R. Dauskardt et al, J. Mater. Res., 2000, 15, Ni is similar to Cu in its yielding behavior with plasticity to improve interfacial toughness but W is difficult to yield. The University of Texas at Austin 30

31 Thermal Deformation of TSV Measured by Bending Beam Technique 4 ~ 5 mm o Via Diameter=10 μm o Via pitch=50 μm o TSV set = 6 46 ea / patch ~ 50 mm 600 μm ~50 μm Oxide layer: 0.8~1 μm 9.45 μm 8.78 μm 6.92 μ m Height=56 µm BB specimen Work in collaboration with H.Y. Son and K.Y. Byun, Hynix. The University of Texas at Austin 31

32 Thermal Deformation of TSV Structure (w/ Oxide Layer) Negative Curvature (Heating) Positive Curvature (Cooling) o thickness: ~400 μm o Specimen dimension: 5 50 mm o 2 o C/min for heating From R.T. to ~200 o C, TSV structures show a linearly elastic behavior. The slope can be used to determine material properties. The stress is free around o C, consistent with annealing at ~100 o C. Yielding observed beyond 200 o C, the deformation mechanism and reliability impact are being investigated. The University of Texas at Austin 32

33 Thermal Deformation of TSV Structure (w/o Oxide Layer) o thickness: ~400 μm o Specimen dimension: 5 50 mm o 2 o C/min for heating Without oxide layer, the linear elastic range is extended but the slope is unchanged. The plastic yield behavior is different, suggesting certain contributions from interface and grain boundaries to mass transport. The underlying mechanism of plasticity for electroplated Cu is being investigated. The University of Texas at Austin 33

34 Stress Distribution (ΔT=200 o C) Sample 1 (w/ oxide) Via: V.M=216 MPa Via: σ 11 = -361 MPa Sample 3 (w/o oxide) Via: V.M=220 MPa Via: σ 11 = -356 MPa The University of Texas at Austin 34

35 TSV Daisy Chain Test Structures S. Cho, RTI 3D Workshop 12/2010 With void eliminated, yield improved to 99% The University of Texas at Austin 35

36 Summary There are challenging reliability issues for 3D interconnects arising from the 3D stack configuration and materials and processing of the TSVs. CTE mismatch is a key parameter contributing to the processing induced stresses that control the thermomechanical reliability of the TSV structure. TSV materials and design can be optimized to improve the reliability. The near surface stresses degrade the carrier mobility and thus define the KOZ through the piezoresistivity effect. Numerical methods, e.g. FEA are being developed for evaluating interfacial debonding of TSV structures. Experimental techniques, test structures and metrology for studying TSV reliability are required. The University of Texas at Austin 36

37 Acknowledgement Discussion with Michael Hecker, Global Foundries, Dresden Phil Garrou, Microelectronic Consultant, NC Michael Lane, Emory and Henry College, VA Mike Shapiro, IBM Bob Jones, Zhihong Huang, Freescale Funding Support Semiconductor Research Corporation The University of Texas at Austin 37