Oxidation enhanced di usion during the growth of ultrathin oxides

Transcription

1 Materials Science in Semiconductor Processing 2 (1999) 29±33 Oxidation enhanced di usion during the growth of ultrathin oxides P.A. Stolk*, A.C.M.C. van Brandenburg, A.H. Montree Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, Netherlands Abstract Boron-doped marker layers grown by chemical vapor deposition were used to measure oxidation enhanced di usion (OED) during the growth of ultrathin oxide layers of 3.3 nm. The oxides were grown by three di erent methods: steam oxidation at 6508C, dry furnace oxidation at 8008C and rapid thermal oxidation at 10508C. The e ective B di usion length decreases drastically with oxidation temperature, being lower than 03 nm for steam oxidation. This demonstrates that steam oxidation is ideally suited for minimizing dopant di usion during the growth of gate oxides in advanced CMOS processing. Di usion analysis shows that the enhancement in the equilibrium di usivity increases from a factor of 03 at 10508C to 0350 at 6508C. On the basis of these measurements, parameters in a state-of-the-art OED model have been calibrated to enable accurate process modeling of OED in the regime of thin oxide growth. # 1999 Published by Elsevier Science Ltd. All rights reserved. 1. Introduction The advancing miniaturization of silicon devices puts increasingly stringent demands on the distributions of dopants in the active area of the device. In deep-submicron (0.1 mm) MOS transistors, the dopant distributions in the source/drain extension regions are projected to have junction depths of less than 50 nm in order to minimize short channel e ects [1]. In addition, it has been demonstrated that the use of steep, retrograde channel pro les yields enhanced electrical performance in comparison to the conventional uniformly doped channel [2±4]. The fabrication of steep and narrow dopant distributions is hindered by the injection of point defects during silicon processing. Silicon self-interstitials that * Corresponding author. Tel.: ; fax: address: stolk@natlab.reseach.philips.com (P.A. Stolk) pair with dopants (e.g. boron) give rise to accelerated dopant di usion during the annealing of implantation damage (transient enhanced di usion Ð TED) [5] (and references cited therein), or during oxidation of the silicon surface (oxidation enhanced di usion Ð OED) [6±8]. The resulting e ective boron di usivity, D e B,is proportional to the ratio by which the interstitial concentration C I exceeds the equilibrium concentration C eq I [8]: D eff B ˆ Deq B C I C eq I D eq B F, where D B eq is the boron di usivity under equilibrium conditions and F is de ned as the di usion enhancement factor. Measurements on OED during the growth of relatively thick oxides (>10 nm) have yielded the following generic expression for the enhancement factor F OED [6,9,10] F OED ˆ 1 d T dtox dt g, /99/$ - see front matter # 1999 Published by Elsevier Science Ltd. All rights reserved. PII: S (99)

2 30 P.A. Stolk et al. / Materials Science in Semiconductor Processing 2 (1999) 29±33 where T ox represents the oxide thickness and g is a characteristic exponent smaller than unity [8]. The response function d(t ) is thermally activated according to d(t )=d o exp(e OED /kt ) and is related to the e ciency of interstitial injection at oxidizing surfaces. The increase of F OED with increasing oxidation rate, r ox =dt ox /dt, re ects the observation that faster growing oxide surfaces drive the interstitial concentrations further out of equilibrium. Accurate knowledge of the parameters in Eq. (2) is crucial for ensuring that process simulation tools can reliably predict dopant di usion during oxidation. In present-day CMOS technology, oxide layers as thin as 2±4 nm are used as insulators between the gate electrode and the channel region of MOS transistors. Until today, no analysis has been performed of the OED associated with the growth of such thin gate oxides. Therefore, we have investigated OED in a technologically relevant regime by growing oxides as thin as 3 nm at oxidation temperatures as low as 6508C. Delta-doping marker layers [11±13] were employed to accurately measure enhanced di usion for three di erent oxidation recipes. It was found that the temperature dependence of OED for thin oxides is properly modeled using the concept of Eqs. (1) and (2) using a slight modi cation of the published values for response function d(t ). 2. Experimental Fig. 1. SIMS depth pro les of B marker layers before and after di usion for (a) steam oxidation, (b) furnace oxidation and (c) rapid thermal oxidation. Solid lines represent the asgrown marker layers, solid symbols represent wafers that were subjected to 3.3 nm oxide growth, and open symbols in (b) and (c) represent wafers that were subjected to the same thermal cycle but in fully inert ambient (no oxygen supplied). 1 The oxide thicknesses quoted in this paper represent the physical thicknesses as measured by ellipsometry. Dopant marker layers were grown epitaxially on 6- inch Si wafers by means of chemical vapor deposition (CVD) using an ASM-Epsilon 1 reactor. Fig. 1 shows that the as-grown structure consists of four B deltadoped markers separated by 00.3 mm with a Gaussian spread s o of 012 nm. The maximum B concentration of /cm 3 is representative of channel dopant levels employed in advanced CMOS technology. Thin oxide layers were grown on these samples using three di erent recipes: (1) steam oxidation (SO) during which wafers are subjected to an H 2 /O 2 mixture at 6508C after 30 min stabilization in N 2, (2) furnace oxidation (FO) during which diluted O 2 is supplied to temperature-stabilized wafers at 8008C, followed by inert annealing at 8508C, (3) rapid thermal oxidation (RTO) during which wafers are subjected to diluted O 2 at 10508C in an RTA machine (ramp rate: 508C/s). The SO and FO steps were performed in a conventional horizontal ASM furnace. The nominal values of T ox grown by these recipes was 3.3 nm 1, which matches the thickness of gate oxides in 0.18 mm CMOS technology. Charge-to-breakdown measurements under gate current injection of 25 ma/cm 2 show that all recipes yield comparable oxide defect densities of <1/cm 2 and charge-to-breakdown values of 01 C/cm 2, indicating device-grade quality. In order to measure the di usion behavior under inert conditions, B marker layers were subjected to the FO and RTO recipes while suppres-

3 P.A. Stolk et al. / Materials Science in Semiconductor Processing 2 (1999) 29±33 31 Fig. 2. E ective di usion length L B as a function of oxidation temperature as extracted from Gaussian ts to the B pro les in Fig. 1. Also shown is an estimate for the di usion length under inert conditions at 6508C as derived from process simulations. sing the O 2 ow during annealing to ensure identical thermal budgets. Boron pro les were measured before and after di usion by dynamic secondary ion mass spectrometry (SIMS), employing a 3 kev O + 2 sputtering beam. It was veri ed that the depth resolution of SIMS was suf- cient to measure the steepness of the B marker layers. Gaussian pro les were tted to the measured dopant distributions in order to extract the peak widths before (s o ) and after (s after ) di usion, from which the e ective B di usion length L B during the various thermal cycles was derived: L 2 2 B =(s after s 2 o )/2. As a further re nement, the B di usivities during the inert and oxidizing steps of each recipe were extracted independently by simulating the B di usion during the full thermal cycle using the process simulator TSUPREM-4 (version 6.5.0). It should be noted that the implicit OED models of TSUPREM-4 were switched o in this approach. The simulated di usion pro les were tted to the measurements by tuning the prefactors of the default B di usivities 2, yielding scaling factors for diffusion under inert and oxidizing ambients. 3. Results and discussion Fig. 1 shows B dopant distributions after the growth of 3.3 nm thick oxides using each of the three recipes. The amount of pro le broadening during oxidation is 2 The TSUPREM-4 default di usion coe cient in units of cm 2 /s is given by: D B eq =( p/n i ) exp( 3.46 ev/ kt), where p and n i are the hole and intrinsic carrier concentration, respectively. Fig. 3. Evolution of (a) oxide thickness measured by ellipsometry and (b) e ective di usion length derived from marker layers during steam oxidation at 6508C. drastically reduced with decreasing oxidation temperature, being almost undetectable for SO. The extracted di usion lengths are shown in Fig. 2, con rming that L B strongly decreases with oxidation temperature. Fig. 1 demonstrates that running the RTO and FO anneals under inert conditions signi cantly reduces the broadening of the marker layers when compared to oxidizing conditions. At all temperatures, the L B -values for inert di usion are indeed lower than those for oxidizing ambients Fig. 2, indicating that the growth of ultrathin oxide layers results in a signi cant enhancement in the B di usion. This implies that all oxidation recipes lead to the injection of excess silicon self-interstitials at the oxidizing surface, resulting in OED. It is clear that all dopant markers within one sample exhibit the same amount of OED (see Fig. 1), indicating that the interstitial-enhanced B di usion is independent of depth down to at least 1.3 mm. This implies that the injected interstitials undergo unperturbed migration into the bulk and establish a at di usion pro- le, even at temperatures as low as 6508C. The long migration length indicates that the CVD-grown layers are of high quality in that they contain a low level of interstitial traps [14] (e.g. carbon) [5], in contrast to marker layers grown by molecular beam epitaxy [5,12]. Since the wafer oxidized at 6508C exhibits only marginal broadening of the marker layers, it is impossible

4 32 P.A. Stolk et al. / Materials Science in Semiconductor Processing 2 (1999) 29±33 Fig. 4. Measured (points) and simulated (lines) B distributions for furnace annealing under inert and oxidizing conditions at 800/8508C. The B di usivities in the process simulator TSUPREM-4 were modi ed in order to t simulations to measurements. to extract accurate numbers for F OED using TSUPREM-4. Therefore, thicker oxide layers were grown using prolonged steam oxidation to improve the OED analysis. Fig. 3 shows the evolution of the oxide thickness as measured by ellipsometry, and the e ective B di usion length as derived from marker layers. The oxide thickness increases linearly with oxidation time at a constant rate of r ox =0.4 AÊ /min, showing that the initial, linear growth regime during steam oxidation at 6508C is sustained for at least 6 h. It should be noted that the T ox (t ) curve in Fig. 3(a) exhibits an o set of 01.5 nm at t = 0, which re ects the thickness of the oxide layer that is grown during wafer loading. Fig. 3(b) demonstrates that L B scales with the squareroot of time, which implies that broadening of the B marker layers during oxidation is characterized by a constant di usivity. It can thus be concluded that the Fig. 5. Scaling factor of B di usivities (left axis) for inert and oxidizing conditions as obtained by tting TSUPREM-4 simulations to measured B di usion pro les. The dashed curve represents D B eq calculated from the TSUPREM-4 default values for B concentrations of /cm 3. Fig. 6. Arrhenius graph of the measured OED di usion enhancements F OED from Fig. 5, normalized with the oxidation rate according to r g ox, using g = 0.4 and g = 0.5. The solid lines represent ts of the response function d(t ) to the data, whereas the dashed lines represent published results for d(t ) for g = 0.4 [10] and g = 0.5 [9]. steady surface oxidation rate at 6508C results in a constant enhancement of the B di usivity, fully in line with the existing understanding of OED as contained in Eq. (2). Hence, it is justi ed to obtain F OED associated with thin oxide layers from the analysis of marker layers that were subjected to comparatively long oxidation times. The thermal cycles of all oxidation recipes were modeled using TSUPREM-4. As an example, Fig. 4 shows simulated marker layer pro les that were tted to the B distributions measured for FO annealing. Excellent ts were obtained by scaling the B di usivities during inert and oxidizing steps, and the resulting scaling factors F are summarized in Fig. 5. The inert FO and RTO annealing cycles yield F = 1 within the experimental error, con rming that the temperature settings are properly calibrated and equilibrium di usion conditions are indeed achieved. The enhancement factor during oxidation increases from F OED 13 at 10508C tof OED 1350 at 6508C, which is roughly consistent with OED measurements on thicker oxide layers [6,7,9]. In spite of this increase in F OED, the overall B di usion is least pronounced for the lowest oxidation temperature, indicating that the F OED -increase with decreasing temperature is overcompensated by the concomitant reduction of D B eq (see Eq. (1)). This implies that steam oxidation at low temperatures is the bestsuited recipe for retaining steep channel doping pro les during the growth of thin gate oxide layers. The measured values of F OED can be used to analyze the OED response function d(t ) over a large tempera-

5 P.A. Stolk et al. / Materials Science in Semiconductor Processing 2 (1999) 29±33 33 ture range. Upon rewriting Eq. (2), d(t ) is given by d T ˆ F OED 1 r g ox : Analogous to the growth rate data for 6508C Fig. 3, the thin oxide growth at 800 and 10508C is considered to occur in the linear growth regimes so that the oxidation rate r ox can be taken constant. In addition, it is assumed that the interstitial injection rate during dry and wet oxidation is entirely determined by the oxide growth rate (as implicit in the above equation), and is not a ected by possible di erences in the chemical state of the oxidizing surface. Earlier OED studies comparing wet and dry oxidation suggest the latter assumption to be valid [13]. Fig. 6 gives values for d(t ) that were derived from the F OED -data in Fig. 5 and the corresponding oxidation rates using two di erent values for g:g = 0.4 [10] and g = 0.5 [9]. From the semi-log plot of Fig. 6 it is obvious that d(t ) exhibits perfect Arrhenius behavior, and the solid lines are ts yielding d o = (s/cm) 0.4 and E OED =1.7 ev for g = 0.4 and d o = (s/cm) 0.5 and E OED =1.8 ev for g = 0.5. It should be noted that reasonable Arrhenius behavior is found when choosing g in the range 0.25±0.7. The present estimates for d(t ) are slightly lower than published values (Fig. 6), in particular at low oxidation temperatures. This discrepancy cannot be explained by the somewhat di erent values used for the equilibrium di usivity D B eq in the various analyses [9,10] 2. Instead, the di erence could arise from the fact that the published values represent the growth of relatively thick oxide layers (typically 100 nm), whereas the present study is focused exclusively on very thin oxides. For instance, the oxide/silicon interface morphology during the initial stages of growth may di er substantially from that of thicker oxide layers, which could a ect the balance between interstitial injection and recombination at the oxide interface and, hence, the resulting interstitial supersaturation. 4. Conclusions The impact of growing thin gate oxides on the di usion of boron has been investigated for three gate oxide recipes. Dopant marker layers show that the B di usion length during the growth of 3 nm oxides by 3 steam oxidation at 6508C is less than 3 nm, demonstrating that steam oxidation is ideally suited for retaining steep dopant pro les during silicon processing. The measured di usivity enhancements have enabled the calibration of OED model parameters describing the e ciency of interstial injection at oxidizing surfaces. Acknowledgements The authors would like to thank W.B. de Boer for growing the dopant marker layers, J.G.M. van Berkum for performing SIMS analysis and FABWAG for wafer processing. This work was supported by the European ACE Program (Esprit 24115). References [1] Semiconductor Industry Association National Technology Roadmap for Semiconductors, [2] Yamaguchi A, Shiraki Y, Katayama Y, Murayama Y. Jpn J Appl Phys 1983;22 (Suppl.):267. [3] Nakagawa K, Van Gorkum AA, Shiraki Y. Appl Phys Lett 1989;54:1869. [4] Ohguro T, Sugiyama N, Imai S, Usuda K, Saito M, Yoshimoto T, Ono M, Kimijima H, Momose HS, Katsumata Y, Iwai H. IEEE Trans Electron Dev 1998;45:710. [5] Stolk PA, Gossmann H-J, Eaglesham DJ, Jacobson DC, Ra erty CS, Gilmer GH, JaraõÂ z M, Poate JM, Luftman HS, Haynes TE. J Appl Phys 1997;81:6031. [6] Lin AM-R, Antoniadis DA, Dutton RW. J Electrochem Soc 1981;128:1131. [7] Ishikawa Y, Sakina Y, Tanaka H, Matsumoto S, Niimi T. J Electrochem Soc 1982;129:644. [8] Fahey PM, Gri n PB, Plummer JD. Rev Mod Phys 1989;61:289. [9] Lever RF, Gri n PB, Rausch WA. J Appl Phys 1995;78:3115. [10] Kizilyalli IC, Rich TL, Stevie FA, Ra erty CS. J Appl Phys 1996;80:4944. [11] Van Oostrum KJ, Zalm PC, De Boer WB, Gravesteijn DJ, Maes JWF. Appl Phys Lett 1992;61:1513. [12] Gossmann H-J, Ra erty CS, Luftman HS, Unterwald FC, Boone T, Poate JM. Appl Phys Lett 1993;63:639. [13] Kujirai H, Murakami E, Kimura S. Jpn J Appl Phys 1995;34:782. [14] Cowern NEB. Appl Phys Lett 1994;64:2646.