1 VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 33 Problems in LOCOS + Trench Isolation and Selective Epitaxy So, we are discussing about a bipolar junction transistor in integrated circuit and the first problem that we are discussing is the problem of isolation. You have already seen that in older day bipolar junction transistor technology, the isolation was provided by a deep pn junction. So, this was called the junction isolation technique, where the reverse biased pn junction would act as the electrical isolation between adjacent devices. But, this older technology proved to be not quite up to the mark, as the device dimensions were reduced and as we wanted faster and faster devices. So, on both counts junction isolation is not a viable technology, because number one, the diffusion will always have some lateral spread; therefore, as the device dimensions become smaller, it becomes more difficult to control the tub width, isolation tub width and secondly the capacitance associated with these junctions, the collector isolation capacitance which was going to hinder the speed of the transistors. So, from junction isolation technique, we came to dielectric isolation technique and the most common, most useful dielectric, silicon dioxide was used for isolation and therefore we had the LOCOS technique, which is nothing but local oxidation. Local oxidation that is oxidation is carried out at some regions of the semiconductor; the other regions are prevented from getting oxidized by using a silicon nitride mask. So, it is actually the interesting property of silicon nitride that it does not allow oxidation to proceed underneath that has been utilized and LOCOS technique therefore, is a very interesting and very widely used isolation technique today. But, as the device dimensions went on becoming smaller, the LOCOS technique also started to show its limitation and what are these limitations?
2 First of all you see, in LOCOS what do you do? (Refer Slide Time: 3:50) You have the cross section of the semiconductor and you have your active region protected by a layer of silicon nitride. Underneath, there is a thin oxide. This thin oxide, the pad oxide which is called, it is needed, because otherwise silicon nitride will not adhere very well to the silicon. There will be a lot of stress induced. So, if you have a thin pad oxide and on top of that you deposit silicon nitride, then the stress will be less. Therefore, it is common practice whenever you want to deposit silicon nitride, you first have a thin layer of oxide and then only then, after that, on top of that you have the silicon nitride. Ok? So, now let us say I want to etch these portions and then I want to grow the oxide that is the recessed local oxide isolation. Ok?
3 (Refer Slide Time: 5:01) So when I am doing that you see, there will be a little bit of encroachment of oxide here. Underneath this silicon nitride there will be a little bit of encroachment of oxide here and because it is shaped like a bird s beak, this is called the bird s beak problem and this is called the bird s crest problem. This is because oxidation is proceeding not merely in the, on the horizontal surface, but also at the vertical sidewalls. That is why there is a slight encroachment under the silicon nitride. Ok? So, now it is easy for you to appreciate that as we reduce the device dimensions, even this small encroachment may start to pose a problem. If this entire active transistor area itself is very small, then even a small encroachment will be a considerable percentage of the total active area. Ok? So, even the isolation by local oxidation will start to suffer from these problems, because of the encroachment of the oxide. So, then it was thought that instead of trying to grow the oxide, if we can etch and then fill up this etched regions with a deposited, some substance which will be non-conducting, instead of growing the oxide you etch required portions in silicon and then fill up this etched regions with some deposited material and that is in a sense what trench isolation is all about. So, from LOCOS we now go to trench isolation.
4 (Refer Slide Time: 7:20) So, you see, we first started with junction isolation. Then, we have seen, instead of junction isolation we have seen LOCOS and now what we are going to discuss is called a trench isolation. So, in a trench isolation, just as the name suggests this is exactly what is done. You cut a trench in the semiconductor and then you fill the trench with a nonconducting material. So, let us see, what are the steps in this trench isolation process? (Refer Slide Time: 7:56)
5 Look at the figure 1. What do I have? I have the p substrate. On top of that I have the n buried layer and on top of that I have the n epitaxial layer. So far everything is identical to the older, the essential basic bipolar junction transistor technology, right? You have started with the p-type substrate, you have the n buried layer and on top of that you have grown the n epitaxial layer. After that you have a pad oxide and then a double layer, one of CVD silicon nitride and then on top of that a CVD silicon dioxide. You deposit this all over the substrate and then remove it from certain regions where you want the isolation region to exist, where you want the trench to be etched. Ok? So, we had a pad oxide, a silicon nitride and then a silicon dioxide and then we have patterned this layer, so as to expose certain region of semiconductor, while other regions are protected by this layer of silicon nitride and silicon dioxide. Ok? Now, in step 2, we have etched down vertically, vertical etching is done, you see and that is possible only when you use dry etching. So, you see, with the advance of technology, to have such vertical sidewalls, chemical etching, wet chemical etching will not do. So, we have to have dry etching with a lot of directionality, so that we can obtain an etch profile with perfectly vertical sidewall and that is a very, very crucial step in trench isolation, to obtain an etch profile with perfectly vertical sidewalls, right and then once you have obtained this perfectly vertical side walls, you do a boron implant, so that you realize a p region here. Why we do it, will tell you a little later, right? For the time being, let us just accept that once this vertical etching is done, we do a boron implant, so that in this p-type substrate, we create a In between these two p region separating the two n regions. Ok? n regions, we have a p region by boron implantation. So, again you see, it is the advance of technology; only by implantation process, we can afford to have a thin p region so exactly defined. So, you have utilized two more modern technologies. One is dry etching, in order to obtain the vertical sidewalls and the other one is ion implantation to have a tight control over the p region. Ok? Let us come to step number 3. Now, you have your trench. So, in trench isolation this was essentially the first step, to etch the trench. What should we do next? We should fill the trench using a non-conducting material. So, we fill the trench by undoped polysilicon;
6 we simply deposit undoped polysilicon. But prior to this polysilicon deposition, before we do this polysilicon deposition, notice that the thin oxidation step is carried out. After the boron implantation, you carry out a thin oxidation. So, where will oxidation progress actually? Oxidation will progress only on the sidewalls and on the bottom surface. It cannot progress here and here, because these portions are protected by silicon nitride, right? So, I have just a thin oxide layer on the sidewalls as well as on the bottom surface, just on top of the p region and now we deposit undoped polysilicon. So, undoped polysilicon is deposited like this. This is another very crucial process, because you want this polysilicon to be deposited uniformly in the trench. Unless you adjust the parameters of deposition carefully, it might not fill the entire trench, there might be gaps. Ok? So, you have cut your trench. The trench walls are lined with oxide and you have deposited polysilicon on top of that. So, you have filled up your trench. Next point is planarization, because topography is very important in integrated circuit. We must have a planar surface. This surface definitely does not look planar, right? So, what we have to do? We have to etch it back. Using silicon nitride as the etch stop layer, we etch it back, so that you have the poly coming only up to here, up to the top of the trench. Ok? Then, you remove the silicon nitride and silicon dioxide and simply carry out another oxidation, thin oxidation, so that the top of the polysilicon layer is also oxidized. So, now look at the trench. What do you have? You have the bottom p-type substrate and then you have this p region and you have two buried n regions on both sides and on top of that the two regions of the n epitaxial layer. So, one transistor will be housed here, the other transistor will be housed here. In between we have a trench which is lined in all directions by silicon dioxide and filled up by undoped polysilicon; therefore, this trench region is non-conducting. So, it provides the electrical isolation. Now we come to question, why did we need the importance of this have? p implantation? What is the p boron implantation? Look at the bottom of the trench. What do we
7 (Refer Slide Time: 15:12) We have an n region here, another n region here, separated by a thin oxide and then on top of that the undoped poly and we have the p region here. So, does it remind you of something? If properly biased it can actually act like the channel region of a MOSFET. I have two n regions separated by a p substrate, on top of which I have a thin gate oxide. So, there is a possibility that this channel could start conducting, in which case these two n regions will no longer be isolated. So, how do you prevent that? By putting a very heavily doped p region here. If the substrate of the MOSFET is very heavily doped, it is more difficult to invert the surface, right? The conduction can only take place when the substrate has got inverted. So, if the substrate is heavily doped, it is that much more difficult to invert the surface. So, by putting a channel from conducting. So, this implant. p region here, we effectively stop the p implantation is therefore called a channel stop It is a channel stop implant which you carry out, in order to ensure that these two n regions are electrically isolated. Even inadvertently, because of the parasitic MOSFET action it should not get turned on. In fact, you know it is a very common practice in MOS technologies - between two adjacent MOS devices, you always put a channel stop implant, so that the drain of one MOSFET and the source of the other, next MOSFET do
8 not get electrically connected inadvertently and you do that by simply putting a channel stop implant in between the two. We will discuss more about it when we discuss MOS technologies. But, even in bipolar junction transistor it may be a problem. Along with the bipolar junction transistor, you may get a parasitic MOSFET and you must ensure that this parasitic MOSFET does not start conducting and you ensure that by giving a channel stop implant, so that the substrate is very heavily doped and it is very difficult to invert the surface. So, this is what trench isolation is all about. You cut a trench, you fill the trench and then you do planarization. Ok? So, this trench isolation is very useful particularly when we are talking about submicron devices. As we go towards smaller and smaller device geometry, it is very, this technology is becoming a very important point. Another way of course, we can think of providing isolation and that is if we have what is known as selective epitaxy. (Refer Slide Time: 18:41) What exactly is selective epitaxy? Let us see.
9 (Refer Slide Time: 19:11) Suppose I started with the p-type substrate, I had n buried layer here and here and then, normally we have the n epitaxial region all over the place, right? So, a common n epitaxial region was grown for all the transistors. Now, instead of doing this, why not grow epitaxial regions only on top of the buried n layer? (Refer Slide Time: 19:47)
10 Why cannot I have. If I can have that, then my problem of isolation does not even exist and as for as planarity is concerned, I can have these regions oxidized. So, how do we go about it? (Refer Slide Time: 20:27) We start off, by having the p-type substrate and the buried layers. Ok? Then, we grow a deposit, a thick layer of oxide. (Refer Slide Time: 20:52)
11 We etch the oxide in certain regions aligned with the buried layer, right and then, we do a selective epitaxy. You know epitaxy actually means arranged upon. So, an epitaxial layer will be formed only on top of the regions, where it can come in contact with silicon. So, it will grow here and here. So, effectively I will have n epi islands sitting aligned with the n buried layer, ok and this can be done by using HCl with silane. When you are doing the epitaxy, you can do it by adding HCl to silane. If you add HCl to silane, then the formation of silicon on silicon dioxide will be suppressed. There will be no silicon deposition on these regions. There will be only silicon deposition on the available substrate. So, you add.. You do epitaxy using silane. In addition to silane, you also put HCl, so that there is suppression of silicon formation on oxide, ok and you prefer a low pressure process. So, basically you have a low pressure epitaxy. But, selective epitaxy is still not a very perfected technique. (Refer Slide Time: 23:05) Selected epitaxy has a lot of problems and one of the most important problems is called the faceting and this is what faceting is. This is what is known as faceting. That is on the sides where it is coming in contact with the oxide, you do not have epilayer growing in a planar manner, going all the way up. Ok? You have facets forming there and in order to
12 suppress this facet formation you have to take more pains that is you have to coat the silicon dioxide with polysilicon. Ok? (Refer Slide Time: 24:08) So, to suppress facets, see the whole thing is happening, because you are using this silane plus HCl, right, because you want to suppress silicon layer formation on oxide. So this is the sidewall of the oxide. So, even there actually you are going to suppress silicon layer formation. That is why these facets are formed, because the layer cannot grow all the way up. Ok? So in order to suppress that again, you have to coat silicon dioxide with poly; coat this sidewalls with poly, so that the facets will grow all the way up and will give you a planar structure. But still, selective epitaxy has a lot of defects. Ok? So, these are the four possible ways of isolation between adjacent transistors in integrated circuit technology. You can either have junction isolation; in fact, junction isolation is still quite a lot in use, particularly for analog devices, ok where the speed may not be of that much importance. As you go to higher speed devices, ok most modern transistors they will use either LOCOS or more advanced transistors will use trench isolation. Ok? Both of them, incidentally they use the same sort of philosophy I would say, that you etch certain
13 regions in silicon and then you fill that etched region. In LOCOS technique, you fill that region by growing oxide. Because the oxide is being grown, there will be little bit of encroachment on either side, which is the bird s beak problem. In case of trench isolation however, since you are filling it by polysilicon deposition, there is no question of any encroachment. But obviously, in trench isolation, your control has to be very high; you must have perfectly high vertical sidewalls and understand that we are doing all this not only for performance enhancement, but also because we want to waste less and less area for isolation. Essentially, the area that is required by isolation is a waste, is it not? It is not housing your active transistor, so you want to keep only very small regions for isolation. At the same time, the isolation must be effective. So, in trench isolation, actually the dimensions of the trench that is very small. The trench width is less than 1 micron. So, it involves a high degree of control, to etch vertical submicron trenches. (Refer Slide Time: 27:39) That is what I am trying to say is, you see, the height of the trench will be much more than its width, can be much more than its width. So, you have to have very high control on the etch profile. It should be perfectly vertical and then of course, the deposition of
14 polysilicon also is another very crucial step and finally, this thin oxidation. Ok? You see, you need this thin oxide, because you want to seal the polysilicon on all sides. Polysilicon, undoped polysilicon is not going to conduct, but unless it is sealed on all sides by silicon dioxide, you cannot be perfectly sure of electrical isolation. Silicon dioxide is a much better insulator, right? So, I need to have silicon dioxide on all sides. Ok? At the same time if the thickness of this oxide is too high then remember, there is a seam in the polysilicon; it is getting deposited from both sides, so there is a seam here. So, if the thickness of this oxide is too much, then you know oxidation can progress down the seam and it can push the two polysilicon regions apart. So, all the steps have to be very carefully controlled and standardized; both I mean all of them, all three of them. That is etching of the trench, then filling of the trench by polysilicon and then final oxidation step. So, this is a very important step in bipolar junction transistor fabrication, namely the problem of isolation. So, depending on your requirements, you can choose from among the list. If junction isolation will do, you can use junction isolation or else you can use LOCOS or use trench isolation or even selective epitaxy. A lot of work is being done in selective epitaxy, but we cannot say that the problems are completely sorted out. After the isolation step, the next step in bipolar junction transistor is the base. We must have the base region. See, we already have the buried layer for collector, we already have the epitaxial region and then we have the isolation and now is the time to have the base region defined in the epitaxial area. Ok? So this is the next processing step that we are going to discuss, the question of base doping. You know already that for doping I have two techniques, diffusion as well as ion implantation. Now, what, which technique are you going to use in order to dope the base, will depend on the base junction depth.
15 (Refer Slide Time: 31:07) If you have a junction which is, if you want the junction which is say, greater than equal to 0.5 micron, if x j is greater than equal to 0.5 micron, then you can use diffusion or you can use ion implantation. Ok? All the older day bipolar junction transistor technology, they used diffusion based technology. Ok? At that time, the junction depth was greater than or minimum junction depth was about 0.5 micron, so you can use diffusion. You use a two step diffusion which is the most common thing. That is you first have the infinite source diffusion and then follow it up with the drive-in, in order to realize the requisite junction depth, ok and you see, drive-in was usually done in an oxidizing ambient, so that it served two purposes. One is you drive the dopants deeper and at the same time, you also grow an oxide layer on top of the base, because you know the next step will be emitter, so for that we have to protect the base region and then open a small window in the base, right? So, the drive-in in oxidizing ambient actually served both purposes.
16 (Refer Slide Time: 32:37) You have the base doping that is this is your n epitaxial region, this is your p and while doing this itself, you grow a layer of oxide on top. So, after the two step diffusion in base, this is what you are going to achieve. Next step, you will open a window in this base region and then diffuse the emitter. Ok? But then, as ion implantation became a viable technology, there were a lot of points, there were lot of points in favor of ion implantation. Why people wanted to use ion implantation for the base doping? You see base doping is a very crucial parameter. First of all the beta of a transistor, it depends very much on the base doping, on the total amount of dopants, total amount of charge that is placed in the active base region. Ok? So, that is called the Gummel number. The total charge present in the active base that is called the Gummel number and that is very important. That must be low for realizing very high beta. So, if you want a high gain transistor, you must control this Gummel number; you must control the total amount of charge that has been put in the base. Ok? But, you see, you cannot afford to have this Gummel number too low. If you put too low a charge in the base, then there is always the possibility of the base getting punched through. Doping is very small, therefore the depletion region can extend all the way and can just punch through the base. Ok? So, this is the problem of doping. I must have a low
17 Gummel number, but not too low a Gummel number. At the same time, the base junction depth must not be high; I must have a narrow base, right? Otherwise there will be all recombination in the base region. So, one must have a narrow base also to have high beta, ok and you know that it is much easier to control these parameters using ion implantation. Ion implantation offers you a tighter control over the sheet resistance. That is it offers you tighter control over the dose. How are you controlling the dose in ion implantation? Simply by adjusting the beam current; absolutely technology dependent, you can control it precisely. While in case of diffusion, you know, it is not so easy to control; a slight temperature fluctuation, ok diffusion coefficient changes, everything changes, the total dose changes. So, it is much easier to control the total dose in an ion implantation process. Therefore, it is much easier to control the sheet resistance. In fact, sheet resistance is widely used as the parameter during transistor fabrication. As soon as the base region is doped, you measure the sheet resistance. Does it conform to the specified value? If yes, fine, you proceed for further processing. If it does not conform, well, you have to take some remedial measure. So, the sheet resistance after the base doping is a very crucial point and this can be very well controlled if you use ion implantation. However, there is a problem. What is the problem? I do implantation. There is going to be damages; I have to anneal out these damages. If I try to anneal out these damages in oxidizing ambient, I have a problem because there will be dislocations, right? So, I have to anneal out these damages in an inert ambient and also, remember, it is not just the annealing step; any subsequent oxidation step will give rise to dislocations. So, how do I then realize this oxide on top of the base? Simple; all I have to do is a chemical vapour deposition. So, after the base implantation is over, we instead of oxidizing, we do a chemical vapour deposition of silicon dioxide and then we carry out the annealing in an inert ambient. So, that will serve two purposes. What are these two purposes? First of all the damage due to implantation will be annealed out and secondly the CVD oxide will get densified by this heat treatment. Ok?
18 The other thing that is done is if you want to decrease the amount of damage in the active transistor, the other thing that can be done is implant boron through a silicon dioxide layer. (Refer Slide Time: 38:52) That is before the base implantation itself, you grow an oxide on top of the base, right and then you do the implantation through this. It is a thin oxide; it is not going to completely mask the implantation. The only thing that you are going to do is you must adjust the energy of the implantation, such that the peak of implantation is at the oxide semiconductor interface, right?
19 (Refer Slide Time: 39:19) That is what I want you to have is you have oxide and then you have silicon. You adjust the implantation energy, so that the peak is here. What is the advantage? You know that the peak of the damage is slightly in front, because the maximum damage is caused in the region when the ions are still in motion. Peak of the implantation actually signifies that region where most of the ions are coming to rest, right? That is the peak, in very crude terms. In a Gaussian distribution, the peak is where most of the ions are coming to rest. That is the average, right? So, the damage peak is actually just before that. When most of the ions are still in motion that is where it is creating maximum damage. So, if you have the implantation through an oxide layer, through a thin oxide layer and if you can adjust the energy such that the peak of the implantation is occurring right at oxide semiconductor interface, you are ensuring that the damage peak is in the oxide. That is most of the damage is contained in the silicon oxide, in the silicon dioxide layer and your active transistor region is not getting damaged, right? If you do base doping by implantation, these are the factors you must keep in mind. First of all, how to reduce the damage? You can do that by having the implantation done through an oxide layer and secondly, remember that in order to anneal out the damage, you must do the annealing in an inert ambient. Otherwise you will have dislocation,
20 decrease in beta, your main purpose will be defeated. If there are dislocations, beta is anyway going to be down and there will be an increase in the leakage current; increase in the leakage current, breakdown voltage will come down, all kind of undesirable effects if there are dislocations, right? So, you must ensure that after the implantation the annealing is not done in an oxidizing ambient and in order to keep the annealing time and temperature at minimum, you should have the implantation done through an oxide layer. So, these are the normal techniques, so long as the junction depth, the base junction depth is greater than or equal to 0.5 micron. If however the base junction is less than 0.5 micron, you have obviously no choice, but to go for ion implantation. It is going to be very difficult to control it using diffusion. You know why, because in diffusion, always the surface concentration is going to be very high, right? You can bring down the surface concentration only by prolonged drive-in. Ok? But, if you have a limit, a restriction on the junction, then you cannot carry out a prolonged drive-in, right? So, if you want to keep the surface concentration down and at the same time you want to realize a shallow junction, then there is no choice but to go for ion implantation. Diffusion cannot answer to the problem. That is why as soon as the junction depth falls below 0.5 micron for the base, we have no other alternative but to go for ion implantation.
21 (Refer Slide Time: 43:24) But, we are still not talking about really very shallow junction, ok we are just talking about x j less than equal to 0.5 micron, slightly less than 0.5 micron. It is not much, much less than 0.5 micron, but you know around there; 0.4 micron, 0.35 micron, something like that. Ok? So, here again, the only thing you have to make sure is that the problem of dislocation does not arise and you can do that by you know, like I said, by implanting and then annealing in an inert ambient. You have a deposited CVD, deposition of silicon dioxide and then you anneal it in an inert ambient, so that you have the damages annealed out, at the same time you have a dense oxide layer on top of the base which you can use in a subsequent step when you are doing the emitter doping, ok to protect the base.
22 (Refer Slide Time: 44:41) However the problems become more severe when we really go to a very shallow junction that of say, junction depth much less than 0.5 micron that is say x j less than equal to 0.2 micron, for example. Even by ion implantation it is going to be difficult and you know why because, boron is a light atom. Boron is a light atom; boron is therefore very prone to channeling. You have to ensure that sufficient amount of boron goes in, right and it is going to be very difficult, because boron is very light. It will go through a considerable distance before coming to rest, so that is going to be very difficult. How can I reduce the problem of both? Well, I cannot do much about boron being a light atom. Can I do anything? I cannot do anything. It is a property of the material; boron is a light atom. I cannot wish to make it heavy. However, I can play a small trick. I can use molecular boron. Instead of using atomic boron, I can use molecular boron, so that the weight problem is to some extent reduced. Ok? So, one thing is you implant from a molecular boron source, for example BF 2, so that your projected range is reduced; reduced. R p is
23 (Refer Slide Time: 46:14) So, first step, first choice is and then how can I reduce channeling? The one way to reduce channeling is amorphize silicon by a self-implantation prior to boron implantation. That is you do first a silicon implantation. That is the self-implantation, right; silicon implanted with silicon, silicon implanted with itself, ok? That is called the selfimplantation. So, you use sufficient high dose energy of silicon implantation, so that you have a thin amorphous layer of silicon. Ok? So, first do this amorphizing and then you implant boron. Then your channeling problem is going to be minimized. So, that is a second possibility, amorphize silicon with silicon implantation before boron implantation in order to reduce channeling, right? The third possibility is of course, you have a thin silicon dioxide layer on top of silicon, so that the range is cut down, right? Instead of implanting straight into silicon, you are implanting through a thin silicon dioxide layer, so that this, some of the implantation is getting masked by this silicon dioxide layer.
24 (Refer Slide Time: 48:55) So again it is possible to realize a shallow junction and the fourth possibility is what is known as a poly-base technology; diffuse through a polysilicon layer. That is let me just briefly outline this; we can expound on this in the next class. What you want to do is you first deposit a polysilicon layer, undoped polysilicon layer over the entire base. Ok? Then, you do the implantation. Ok? See, you have no restriction on the polysilicon layer thickness. You can have a thick polysilicon layer and then you implant in this polysilicon layer making sure that this implantation does not reach the actual crystalline silicon. Ok?
25 (Refer Slide Time: 50:16) That is to say I have a, this is my poly and this is my crystalline silicon. You do the implantation, so that right here nothing goes into the crystalline silicon. Ok? Now, you use this doped poly as a source and you do, carry out annealing or drive-in, whatever you want to call it, so that actually what happens is you get a shallow junction in the silicon. So, you are not doing the implantation directly into crystalline silicon; you are doing the implantation in the polysilicon making sure that no part of this implantation reaches the crystalline silicon region and next you are going to use this implanted poly as the source; you do a short high temperature treatment, so that this is what you get. You can realize a very shallow junction, 0.15 micron by this technique, ok and this is widely used today for all high speed transistors. Ok? You can carry out annealing at around C and you can realize an x j as low as 0.15 micron, right? So, you see how you are going to dope the base is going to depend on the junction depth. If the base junction is fairly deep that is greater than equal to 0.5 micron, you can use either diffusion or implantation. But of course, people would prefer to use implantation, because it gives you better control. However, if you are doing implantation, remember, you cannot follow it up with an oxidation step, then all subsequent, for all subsequent
26 oxides, you must use CVD oxide and do the annealing in inert ambient. If however the base junction depth has to be less than 0.5 micron, you have to use ion implantation. So long as it is, I mean, if the order of 0.5 micron, you know 0.4 or 0.35 micron, these same precautions will hold good if you do ion implantation. If however you are going really to very, very shallow junctions of junction depth less than 0.2 micron, it is going to be difficult by doing it simply by ion implantation. You must now take adequate precautions that is you should reduce channeling by preamorphizing the silicon substrate, you should try to reduce the projected range of boron implantation by using a molecular boron source or you should try to implant through a silicon dioxide layer or best still, the best alternative is have a polysilicon layer deposited on the base; implant in that polysilicon layer and then use this polysilicon layer as the source, anneal at C, so that you can realize extremely shallow junctions.
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Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection
INSTRUCTIONS Read all of the instructions and all of the questions before beginning the exam. There are 5 problems on this Final Exam, totaling 143 points. The tentative credit for each part is given to
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 5 Crystal Structure contd So far, we have discussed about the crystal structure
Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)
Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1 The Manufacturing Process For a great tour through the IC manufacturing
Chapter 3 Fabrication of CMOS Integrated Circuits Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Background Outline The CMOS Process Flow Design Rules Latchup
3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss the
Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
Processing of Semiconducting Materials Prof. Pallab Banerjee Department of Material Science Indian Institute of Technology, Kharagpur Lecture - 35 Oxidation I (Refer Slide Time: 00:24) Today s topic of
ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior
Construction Analysis National Semiconductor LM2672 Simple Switcher Voltage Regulator Report Number: SCA 9712-570 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale,
EE 330 Lecture 8 IC Fabrication Technology Part II?? - Masking - Photolithography - Deposition - Etching - Diffusion Review from Last Time Technology Files Provide Information About Process Process Flow
VLSI Digital Systems Design CMOS Processing cmpe222_03process_ppt.ppt 1 Si Purification Chemical purification of Si Zone refined Induction furnace Si ingot melted in localized zone Molten zone moved from
Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
Chapter 4 UEEP2613 Microelectronic Fabrication Oxidation Prepared by Dr. Lim Soo King 24 Jun 2012 Chapter 4...113 Oxidation...113 4.0 Introduction... 113 4.1 Chemistry of Silicon Dioxide Formation... 115
2. CMOS Fabrication, Layout, Design Rules Last module: Introduction to the course How a transistor works CMOS transistors This module: CMOS Fabrication Design Rules CMOS Fabrication CMOS transistors are
Radiation Tolerant Isolation Technology Background The following contains a brief description of isolation technologies used for radiation hardened integrated circuits. The technologies mentioned are junction
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
ΚΥΚΛΩΜΑΤΑ VLSI Πανεπιστήμιο Ιωαννίνων CMOS Technology Τμήμα Μηχανικών Η/Υ και Πληροφορικής 1 From the book: An Introduction ti to VLSI Process By: W. Maly ΚΥΚΛΩΜΑΤΑ VLSI Διάρθρωση 1. N well CMOS 2. Active
Problem 1 Lab Questions ( 20 points total) (a) (3 points ) In our EE143 lab, we use Phosphorus for the source and drain diffusion. However, most advanced processes use Arsenic. What is the advantage of
Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW
EE 22 FALL 999-00 THERMAL OXIDATION - Chapter 6 Basic Concepts SiO 2 and the Si/SiO 2 interface are the principal reasons for silicon s dominance in the IC industry. SiO 2 : Easily selectively etched using
FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the
EE 143 CMOS rocess Flow CT 84 D D G Sub G Sub S S G D S G D S + + + + - MOS Substrate Well - MOS Substrate EE 143 CMOS rocess Flow CT 85 hotoresist Si 3 4 SiO 2 Substrate selection: moderately high resistivity,
Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
Part I Amorphous and Polycrystalline Thin-Film Transistors HYBRID AMORPHOUS AND POLYCRYSTALLINE SILICON DEVICES FOR LARGE-AREA ELECTRONICS P. Mei, J. B. Boyce, D. K. Fork, G. Anderson, J. Ho, J. Lu, Xerox
International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 4, Number 3 (2011), pp. 267-274 International Research Publication House http://www.irphouse.com Design Consideration
High Speed Devices and Circuits Prof K. N. Bhat Department of Electrical Engineering Indian Institute of Technology, Madras Lecture 4 Ternary Compound Semiconductors and their Applications Last time we
CMOS Manufacturing Process CMOS Process A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V
Lithography Independent Fabrication of Nano-MOS-Transistors with W = 25 nm and L = 25 nm J. T. Horstmann John_Horstmann@ieee.org C. Horst Christian.Horst@udo.edu K. F. Goser firstname.lastname@example.org Abstract The
UNIT 4 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun Syllabus METALLIZATION: Applications and choices, physical vapor deposition, patterning, problem areas.
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different
Section 4: Thermal Oxidation Jaeger Chapter 3 Properties of O Thermal O is amorphous. Weight Density =.0 gm/cm 3 Molecular Density =.3E molecules/cm 3 O Crystalline O [Quartz] =.65 gm/cm 3 (1) Excellent
-Spring 006 Digital Integrated Circuits Lecture 4 CMOS Manufacturing Process Design Rules EECS141 1 Good News! We are moving to 155 Donner Lab From Thursday, Feb We will be able to accommodate everyone!
Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi
Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
THERMAL OXIDATION - Chapter 6 Basic Concepts SiO 2 and the Si/SiO 2 interface are the principal reasons for silicon s dominance in the IC industry. Oxide Thickness µm 0. µm 0 nm nm Thermally Grown Oxides
Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass
Construction Analysis Xilinx XC4036EX FPGA Report Number: SCA 9706-544 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925
SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY TIRUPACHUR DEPARTMENT OFELECTRICAL AND ELECTRONICS ENGINEERING EE6303 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS 1. Define an Integrated circuit.
EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography
EE 330 Lecture 10 IC Fabrication Technology Part III Metalization and Interconnects Parasitic Capacitances Back-end Processes Devices in Semiconductor Processes Resistors Diodes Review from Last Lecture
Ion implantation Contents 1. Introduction 2. Ion range 3. implantation profiles 4. ion channeling 5. ion implantation-induced damage 6. annealing behavior of the damage 7. process consideration 8. comparison
Construction Analysis SGS-Thomson L4990 Controller Report Number: SCA 9710-560 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS