IN RECENT years, the developments in microelectromechanical

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1 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 4, NOVEMBER Transfer of Metal MEMS Packages Using a Wafer-Level Solder Transfer Technique Warren C. Welch, III, Junseok Chae, and Khalil Najafi, Fellow, IEEE Abstract This paper presents a modular, low profile, waferlevel encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the carrier wafer and TLP bonding of the cap to the device wafer during bonding. The bond and transfer cycle has a maximum temperature of 300 C and lasts about 2.5 h. This approach has been demonstrated with nickel (Ni) caps as thin as 5 microns, with thicker caps certainly possible, ranging in size from 200 m to 1 mm. They were transferred with a lead-tin (Pb-Sn) solder layer and bonded with nickel-tin (Ni-Sn) TLP bonding with greater than 99% transfer yield across the wafer. Index Terms Diffusion soldering, microelectromechanical systems (MEMS) packaging, transferred thin-film packaging, transient liquid phase bonding. I. INTRODUCTION IN RECENT years, the developments in microelectromechanical systems (MEMS) packaging have not kept pace with new achievements in MEMS device research. Many of the new devices that have been developed are fragile, suspended, three-dimensional (3-D) structures that need to be protected during back-end processing steps. Radio frequency (RF) MEMS resonators are one example. They require a small gap to achieve high performance, which makes the devices susceptible to problems from stiction and particles after they have been released [1]. These problems complicate further fabrication steps, such as integration and assembly, by limiting the nature and environment of the final steps to dry processes in a clean environment. A packaging step performed right after the devices are released relaxes these constraints by protecting the devices during the final steps. A wafer-level thin-film packaging approach offers many attractive benefits for this packaging step, including a small footprint, a hermetic seal, low profile encapsulation, and low cost [2]. After the devices have been fabricated and released, the thin-film package can be applied at the wafer level while the devices are still in a clean environment, eliminating the need for Manuscript received December 10, 2004; revised July 8, This work was supported by the Defense Advanced Research Profects Agency (DARPA) under Grants Micro/Nano-Mechanical Signal Processors for Miniaturized Low-Power RF Channel-Select Receivers (F ) and Environment-Resistant Micromachined Inertial Gyroscopes (ER-MIG) (W31P4Q-04-1-R001). The authors are with the Center for Wireless Integrated Microsystems, University of Michigan, Ann Arbor, MI USA ( welchw@ umich.edu). Digital Object Identifier /TADVP costly die-level processing and providing the back-end protection necessary for high yield. Thin-film packages also reduce processing cost by saving valuable die area. A thin-film packaging approach previously reported bond rings an order of magnitude smaller than many conventional bonding technologies in use today [3] [5]. This is a substantial cost savings when you consider the size of the devices to be packaged. A typical MEMS device occupies an area of around m. A conventional bond ring surrounding the device occupies an area six times as large. Reducing this bond ring width can save a large amount of die area. Thin-film packaging also differs from many other wafer-scale packaging approaches because it can create a reliable hermetic seal and still maintain a low profile, making subsequent integration steps easier. Quality metal films have low permeability enabling them to create a hermetic seal with much smaller thicknesses compared to other materials [6]. Thus, the package height is reduced from Pyrex wafer thicknesses of hundreds of micrometers down to a low profile thickness of tens of micrometers without compromising the seal quality. A low-profile cap relaxes the requirements for the subsequent integration and assembly steps and offers more options for the final packaging solution. One approach has achieved good results with epi-poly as the packaging material, but the high temperatures required for fabrication makes integration a challenge, and the package can be used with only a specific set of materials and a dedicated process [7]. Much of the previous work has demonstrated wafer-level thin-film packages that were fabricated on the device wafer prior to releasing the MEMS structures. This approach has all the advantages of thin-film packaging a small footprint, low profile, etc. but fabricating the package on the device wafer limits the processing flexibility because it must be considered in the overall design. For instance, many MEMS process flows use a long etch in hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to remove an oxide sacrificial layer and release the devices. Many materials, such as chromium (Cr) and titanium (Ti), etch very rapidly in HF and are, therefore, not compatible with this type of release. These disadvantages can be overcome by creating the package on a separate carrier wafer, performing the release step on the device wafer, then transferring the package from the carrier wafer to the device wafer. Combining the advantages of a thin-film packaging approach with a modular bond and transfer technique adds process flexibility and eases the integration of the thin-film package without compromising the device process. There are several research efforts pursuing transferred thin-film packaging technology. Most of the efforts have used /$ IEEE

2 644 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 4, NOVEMBER 2005 Fig. 2. Cross section of package before contact. Fig. 1. Cap transfer process overview. polymer bonds to attach packaging caps to the device wafer [8], [9]. For one approach, nickel (Ni) caps were electroplated onto a passivated seed layer on a carrier wafer. The caps were later bonded to a device wafer with different polymers and transferred by removing the carrier wafer. The passivation on the seed layer reduced the adhesion strength between the package cap and the carrier wafer, making it easy to break the bond between the two. The electroplated caps are bonded to the device wafer by polymer bonds, which are neither hermetic nor stable. Another effort used solder bonding for attachment, but it was done at the die level [10]. Electroplated domes were formed on a carrier glass then bonded to the device wafer by solder bonding and transferred by breaking the support tethers. The approach reported below combines a metal cap packaging technology with a transient liquid phase (TLP) metal bond and implements it on the wafer level. The all-metal bond and transfer technique is enabled by a novel solder transfer process that is discussed in the following sections. II. APPROACH AND DESIGN This packaging approach consists of electroplated metal caps formed on a carrier wafer that are transferred to the device wafer. Processing begins with the fabrication of the caps on a carrier wafer (see Fig. 1). First, the solder transfer layer is electroplated into a photoresist mold. Many types of solders are eligible, provided they can be electroplated. Electrodeposition is preferred over other methods, such as screen printing, because it simplifies the processing by allowing further electrodeposition steps to form the package body right on top of the solder transfer layer. After the solder is deposited, the package is electroplated directly onto the solder layer. This completes the fabrication on the carrier wafer. Processing continues on the device wafer with the formation of the TLP bond ring. The bond ring is made up of two layers: a thick layer of the same metal that is used to form the package and a thin layer of a low melting point metal, which is usually tin (Sn) or indium (In). The bond ring is designed to form a strong bond between the device wafer and the package caps during the bond and transfer cycle. After the bond ring is completed, the MEMS device is released and the package caps are simultaneously bonded and transferred by a novel solder transfer technique. The two keys to the solder transfer technique are the weakening of the bond between the package cap and the carrier wafer and the strengthening of the bond between the package cap and the device wafer. These are accomplished simultaneously by taking advantage of certain material properties and interactions at higher bonding temperatures. Through proper design of the transfer solder layer on the carrier wafer and the TLP bond joint on the device wafer, the caps are transferred by simply making contact between the wafers and raising the temperature. An illustration of the package cross section, before contact or heating the wafers, is shown in Fig. 2. A. Solder Transfer Layer The mechanical integrity of a solder joint depends on many factors, including the contact angle between the solder and the surfaces it bonds together. The relative surface tensions of the solder and the other materials in the joint will determine this contact angle. If the surface tension of the solder is higher than the surface tension of the wafer, the solder will form a high contact angle with the surface of the wafer and dewet this surface. This reduces the adhesion strength between the two materials and results in a weakened bond. The weakening of a solder bond by dewetting is used in this transfer approach to facilitate removal of the package caps from the carrier wafer. During bonding, the elevated temperatures cause the solder layer to consume its electroplating seed layer and reveal the surface of the carrier wafer. The surface tension of the carrier wafer is higher than the surface tension of the solder so the solder dewets the carrier wafer and becomes weakly attached (see Fig. 3). After the solder dewets the carrier wafer and everything has cooled, the weakened solder bond is easily broken with minimal force. The selection of a suitable carrier wafer, solder seed layer, and package material is necessary to ensure the transfer solder layer

3 WELCH et al.: TRANSFER OF METAL MEMS PACKAGES USING A WAFER-LEVEL SOLDER TRANSFER TECHNIQUE 645 Fig. 3. Fig. 4. Solder transfer layer dewetting. Dissolution rate of metals in Pb Sn solder. performs properly. First, the carrier wafer needs to have a surface tension higher than the transfer solder layer; typical substrates such as silicon (Si) or Pyrex wafers satisfy this requirement. Second, the electroplating seed layer needs to be a material that is rapidly consumed by the solder at high temperatures and thin enough to be consumed in reasonable time. Fig. 4 shows the dissolution rates of several materials in lead tin (Pb Sn) solder versus temperature. The dissolution rate of a metal by the solder melt is directly correlated to the formation rate of intermetallic compounds between the solder and the metal [11]. Gold (Au) stands out as the best choice for the solder electroplating seed layer because it is rapidly consumed by the solder and it forms no native oxide, which simplifies the electroplating process. Third, the package must be made out of a material that is not consumed rapidly by the solder transfer layer. The package cap is formed by electrodeposition directly on top of the solder transfer layer, thus, the package cap is in direct contact with the solder layer during bonding. If the dissolution rate of the package material is too high, the solder transfer layer will react chemically with the package material and alter its material properties. In a worst case scenario, the solder will fully react with the package material before consuming the seed layer making the transfer process impossible; this constraint removes materials like copper from consideration for the package cap material and makes Ni an attractive choice. All these requirements must be satisfied to ensure a reliable, repeatable transfer process. B. Transient Liquid Phase Bonding Transient liquid phase bonding is widely used in industry to form high-quality metal bonds at relatively low temperatures [11]. The approach is a blend of diffusion bonding and soldering that combines the advantages of both to overcome some shortcomings of each and create a bonding solution that is a good candidate for MEMS packaging. Diffusion bonding relies on solid state diffusion between similar metals to form a continuous joint [12]. It takes high temperatures to accelerate the diffusion, high pressures to ensure good contact between the two metals, and several hours to complete the process. Diffusion bonding also requires very clean and planar surfaces because any contaminants or air gaps will impede the diffusion process. If all the requirements are met, it creates a strong, high quality bond that can survive temperatures much greater than the bonding temperature. Soldering, on the other hand, is a much faster process that takes only minutes to complete as opposed to hours, and offers different advantages compared to diffusion bonding [11]. Soldering relies on a liquid filler material that wets and forms a metallurgical bond to both pieces that need to be joined. It is easy to bond nonplanar surfaces together with soldering, because the solder forms a liquid phase during the bonding process that will flow over nonplanarities. However, unlike diffusion bonds, a solder bond cannot survive higher temperatures than the bonding temperature after it has completed. The liquid filler metal does not sufficiently react with the parent metals to change its melting temperature; it still has the same melting point as before and the bond will remelt if it is exposed to temperatures approaching the bonding temperature. TLP bonding (or diffusion soldering) combines these two approaches to create a solution that combines the advantages of each to make up for the disadvantages of the other. A TLP bond uses a low melting point metal to bond two parent metals together, just as in soldering, but the bonding mechanism is different. Unlike soldering, which relies mainly on the wetting force of the molten solder to form the bond, a TLP bond relies mainly on material reactions between the solder and parent metals for bond formation. The chemical reactions between the solder and parent metals form intermetallic compounds. The presence of these intermetallic compounds raises the remelting temperature of the joint above the original melting temperature of the solder [13], which allows the final joint to survive temperatures much higher than the original bonding temperature, similar to a diffusion bond (see Table I for a listing of some TLP bonding material families and their melting points before and after bonding). However, unlike diffusion bonding, a liquid phase exists during the bonding cycle that will flow over nonplanar surfaces and fill in air gaps. The liquid phase exists only temporarily and cannot fill joints as large as a normal solder process, but it improves on the diffusion bonding process by relaxing the applied pressure and surface planarization requirements for a successful bond. TLP bonding combines the planarization capabilities of a solder process with the high melting temperature of a diffusion process to create an approach well suited for MEMS packaging.

4 646 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 4, NOVEMBER 2005 TABLE I PROCESS AND MELTING TEMPERATURES OF SEVERAL TLP MATERIAL FAMILIES A TLP bond proceeds through four stages as it forms (see Fig. 5). Step 1) The wafers are brought into contact, which sandwiches a low melting-point interlayer between two parent metallizations. Step 2) In this paper, the parent metal is Ni and the low melting-point interlayer is Sn. As the temperature increases, the interlayer melts. Step 3) It then flows over surface nonplanarities. In its molten state, the interlayer reacts with the parent metals to form intermetallic compounds. In this paper, the intermetallic compound is Ni Sn. Step 4) Further heating increases the bond quality by causing the intermetallic compounds to diffuse away from the joint interface and become a solid solution in a pure parent metal joint. TLP bonds are well suited for this type of packaging because they can planarize over feedthroughs and survive much higher temperatures than the formation temperature. MEMS devices need some kind of electrical contact to the environment in order to function properly. Lateral electrical feedthroughs are one way to provide connectivity, but they have a finite step height that cannot be accommodated by nonplanarizing bonds, such as anodic and diffusion bonding. TLP can accommodate most electrical feedthroughs that are less than 1 m tall, because the liquid interlayer melts and planarizes over the feedthroughs during bonding. A simple solder bond is also capable of planarizing lateral feedthroughs, but it limits the choices for subsequent bonding steps because its melting point is the same as its formation temperature. This lower melting point narrows the choices for the final assembly and integration steps. TLP bonding leaves more options open for the final packaging steps because of its thermal robustness. For instance, a Ni Sn TLP bond is formed above the melting point of Sn (232 C). After the Sn has fully reacted with the Ni to form the intermetallic compounds, the melting temperature of the joint is raised to over 400 C [14]. Some of the final packaging and integration steps, such as flip-chip integration, may require high temperatures that would not be compatible with this approach if a solder or polymer bond was used in its place. III. FABRICATION Fabrication begins on the carrier wafer by evaporating a thin titanium (Ti 50 ) gold (Au 500 ) electroplating seed layer Fig. 5. Four stages of TLP bonding. (see Fig. 1). Gold (Au) is used for the seed layer because it is rapidly dissolved by Pb Sn solder and it does not oxidize, making it easy to electroplate other materials on top. Two micrometers of the Pb-Sn (60 40 wt%) transfer solder is electroplated onto this seed layer into a photoresist mold. Any solder alloys, such as lead-free solders, could be used as the solder transfer layer as long as they can be electrodeposited and they satisfy the dissolution rate requirements for the chosen seed layer. Next, the Ni cap is electroplated (5 m thick) directly on the transfer solder by electroplating into the same photoresist mold. After the lid is formed, more photoresist is spun on top of the old resist and the package rim is defined by photolithography. The nickel oxide that formed on the cap is removed in a

5 WELCH et al.: TRANSFER OF METAL MEMS PACKAGES USING A WAFER-LEVEL SOLDER TRANSFER TECHNIQUE 647 Fig. 6. Transferred caps on a Si wafer. Fig. 7. Side view of a transferred cap. dilute HCl solution before electroplating the rim to ensure good adhesion. This completes the fabrication on the carrier wafer. The device wafer fabrication starts with the evaporation of a titanium (Ti 300 ) nickel (Ni 1500 ) seed layer. A photoresist mold is created on top of the seed layer to define a bond ring around the device. A dip in dilute HCl removes the nickel oxide from the seed layer before electroplating to ensure good deposit adhesion. After the bond ring is electroplated, a layer of Sn (1.5 m) is evaporated onto the wafer. By sacrificing the electroplating mold, the Sn is removed from all the areas on the wafer except for the top of the bond rings. Finally, the wafers are aligned and bonded in a Suss SB-6 wafer bonder. The wafers are loaded and the chamber is pumped down to vacuum torr then heated to 300 C. A pressure of 100 kpa is applied to flatten the wafers and ensure good contact across the wafer. After about 2.5 h at temperature, the wafers are allowed to cool to 50 C under vacuum; then the chamber is pressurized and the wafers removed. After bonding, the carrier wafer and device wafer are weakly bound together by the transfer solder and package cap. This bond is easily broken with the tip of a razor blade and the carrier wafer removed leaving the caps bonded to the device wafer. Fig. 8. Closeup of a TLP bond interface and EDAX data. IV. RESULTS AND DISCUSSION The process was run with two different substrates for the device wafer, Pyrex and Si. The transferred and nontransferred caps were counted after bonding to measure the yield. In each case the yield was greater than 99%. The yield was slightly lower with Pyrex as the device wafer (1192 out of 1200 caps transferred) versus silicon (1200 out of 1200 caps transferred). This could be accounted for by the slight thermal mismatch between Si and Pyrex. A picture of a Si wafer with transferred caps is shown in Fig. 6. A scanning electron microscopic (SEM) image of the side of a transferred cap is shown in Fig. 7. After bonding, the TLP bond composition was analyzed in a scanning electron microscope with energy dispersive spec-

6 648 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 4, NOVEMBER 2005 Fig. 9. White light measurement of package deflection. troscopy capabilities. A picture of the bond and the varying composition is shown in Fig. 8. The formation of intermetallics was confirmed by the changing ratio of Ni to Sn across the interface. The Ni composition starts at 97% on the top, and then goes to about 50% Ni/50% Sn near the bond joint, then goes back to 96% on the bottom. The solder transfer process was successful over several wafers from different runs, with a high yield every time. In each case, the solder had completely eaten away at the gold (Au) seed layer and exposed the bare Si. The TLP bond was enough to transfer the devices, but not enough to provide a hermetic seal. The hermetic qualities of the TLP bond were explored by measuring package deflection to determine the pressure inside the packages after bonding. The packages were bonded in a vacuum environment. If the TLP bond provides any type of hermetic seal, the inside of the package should be at a pressure below atmosphere and the lid should be deflected. A white light interferometer was used to accurately measure the package deflection (see Fig. 9). The deflection was measured right after bonding and then again after puncturing the package lid to equalize the pressure to confirm the deflection was not due to stress in the Ni lid. There was no change in the package lid deflection after the pressure was equalized indicating that the TLP bond did not provide any sort of hermetic seal. The deflection was due to stress in the package lid. The thickness of the TLP low melting point interlayer and heating rate play an important role in the planarazation capabilities mentioned previously [20]. If the interlayer is too thin or the heating rate is too low, the low melting point interlayer can be consumed by the parent metal before it transforms into a liquid phase. The intermetallic formation reaction between the parent metal and interlayer can be rapid enough at low temperatures to completely consume a thin interlayer before it can melt. The interlayer thickness becomes the most important parameter in vacuum bonding applications because it is hard to increase heating rate with such high thermal isolation between the wafers and the bonding tool at low pressures. Without air molecules to conduct the heat from the bonding chuck to the wafers, it takes time to heat up the wafers for bonding. The thickness of the interlayer must be increased to better planarize the bond interface. In this process, the interlayer was evaporated onto the bond ring on the device wafer. The maximum allowable thickness was limited to 2 m by the size of the crucible in the deposition system. In the future, we plan to deposit the Sn by electrodeposition, which will allow a thicker interlayer for better planarazation. V. CONCLUSION A method of transferring thin-film metal packages with a novel solder transfer layer has been developed. The method allows packages to be electroplated on a separate carrier wafer and later simultaneously transferred and bonded to a device wafer. This modular approach adds fabrication flexibility to the packaging process and the device process that is not available if the packages are formed on the device wafer. The transfer is accomplished by selective dewetting of a solder transfer layer and the formation of TLP bond between the package cap and device wafer. The TLP bond did not provide a hermetic seal because the low melting point interlayer was too thin, but the attachment strength was high enough to transfer more 99% of the caps from the carrier wafer to the device wafer. In the future, we plan to investigate the planarazation capabilities of thicker, electroplated Sn interlayers. REFERENCES [1] W. T. Hsu, J. R. Clark, and C. T.-C. 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7 WELCH et al.: TRANSFER OF METAL MEMS PACKAGES USING A WAFER-LEVEL SOLDER TRANSFER TECHNIQUE 649 [9] Y. J. Chiang, M. Bachman, and G. P. Li, A wafer-level microcap array to enable high-yield microsystem packaging, IEEE Trans. Adv. Packag., vol. 27, no. 3, pp , [10] J. Y. Chen, A novel device-level micropackaging using micro assembly transfer, in Proc. ASME Int. Mechanical Engineering Congr. Expo., New York, Nov , 2001, pp [11] G. Humpston and D. M. Jacobson, Principles of Soldering. Materials Park, OH: ASM International, [12] S. B. Dunkerton, Diffusion bonding. Process and applications, Weld Met. Fabr., vol. 59, no. 3, [13] T. Studnitzky and R. Schmid-Fetzer, Phase formation and diffusion soldering in Pt/In, Pd/In, and Zr/Sn thin-film systems, J. Electron. Mater., vol. 32, no. 2, [14] P. K. Khanna, G. Dalke, and W. Gust, Morphology and long term stability of Ni/Ni interconnections based on diffusion soldering, Mater. Res. Adv. Tech., vol. 90, pp , [15] D. M. Jacobson and G. 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Welch, III was born in Jacksonville Beach, FL, in He received the B.S. degree in electrical engineering from Lehigh University, Bethlehem, PA, in 2001 and the M.S. degree from the University of Michigan, Ann Arbor, in During his time at Lehigh, he spent one summer at the Department of Energy Princeton Plasma Physics Laboratory developing code to facilitate the visualization of scientific data. The following summer, he was part of the National Science Foundation s (NSF) Research Experience for Undergraduates program at Lehigh s Sherman Fairchild Research Laboratory. At the lab, his work focused on reducing the number of oxide traps at the surface of a silicon carbide MOS capacitor. His research interests include MEMS packaging, intertial sensors, and micromachined power sources. Mr. Welch received the Outstanding Student Leadership Award from the NSF Engineering Research Center for Wireless Integrated MicroSystems in Junseok Chae received the B.S. degree in metallurgical engineering from Korea University, Seoul, Korea, in 1998, and the M.S. and Ph.D. degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, in 2000 and 2003, respectively. From 2003 to 2005, he was a Postdoctoral Research Fellow at Wireless Integrated MicroSystems (WIMS), University of Michigan. He joined the faculty of Arizona State University, Tempe, in August 2005, where he is currently an Assistant Professor in electrical engineering. His areas of interests are MEMS sensors, mixed-signal interface electronics, MEMS packaging, ultrafast pulse (femto-second) laser for micro- and nanostructures, and cell-on-a-chip bio-mems. He had an invited talk at Microsoft, Inc. regarding MEMS technology for consumer electronic applications and is the holder of a couple of U.S. patents. Dr. Chae received the first place prize and the Best Paper Award in a Design Automation Conference (DAC) student design contest in 2001 with the paper entitled Two-dimensional position detection system with MEMS accelerometer for mouse application. Khalil Najafi (S 84 M 86 SM 97 F 00) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, in 1980, 1981, and 1986 respectively. From 1986 to 1988, he was a Research Fellow, from 1988 to 1990 as an Assistant Research Scientist, from 1990 to 1993 as an Assistant Professor, from 1993 to 1998 as an Associate Professor, and since September 1998 as a Professor and the Director of the Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan. His research interests include: micromachining technologies, micromachined sensors, actuators, and MEMS; analog integrated circuits; implantable biomedical microsystems; micropackaging; and low-power wireless sensing/actuating systems. Dr. Najafi was awarded a National Science Foundation Young Investigator Award from 1992 to 1997, was the recipient of the Beatrice Winner Award for Editorial Excellence at the 1986 International Solid-State Circuits Conference, of the Paul Rappaport Award for coauthoring the Best Paper published in the IEEE TRANSACTIONS ON ELECTRON DEVICES, and of the Best Paper Award at ISSCC In 2003, he received the EECS Outstanding Achievement Award, in 2001 he received the Faculty recognition Award, and in 1994 the University of Michigan s Henry Russel Award for outstanding achievement and scholarship, and was selected as the Professor of the Year in In 1998, he was named the Arhtur F. Thurnau Professor for outstanding contributions to teaching and research, and received the College of Engineering s Research Excellence Award. He has been active in the field of solid-state sensors and actuators for more than 20 years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid- State Sensors and Actuators Workshop, and the IEEE/ASME Microelectromechanical Systems (MEMS) Conference. He is the Editor for Solid-State Sensors for the IEEE TRANSACTIONS ON ELECTRON DEVICES, an Associate Editor for the Journal of Micromechanics and Microengineering, Institute of Physics Publishing, and an Editor for the Journal of Sensors and Materials. He also served as the Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 2000 to 2004, and the Associate Editor for the IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING from 1999 to 2000.