The Role of Wafer Foundries in Next Generation Packaging. David McCann, VP Packaging R+D May 28, 2013

Transcription

1 The Role of Wafer Foundries in Next Generation Packaging David McCann, VP Packaging R+D May 28, 2013 Page 1

2 Solutions are Increasingly Silicon-Based RF moves from QFN to wlcsp Driven by footprint and cost Memory moves much closer to the logic in 2.5D and 3D Driven by power reduction and increased bandwidth 3D memory stacks replace 2D DIMMs Driven by bandwidth, density, footprint Courtesy: Micron Technology Interconnect density increases Driven by progressively denser Si nodes Driven by SoC disaggregation Page 2

3 Disaggregation SOC scaling is not delivering full entitlement of cost/area improvement Enables SoC fission into best cost-performance fit node for each chip Enables high bandwidth and increased performance per joule Enables re-use without re-design lower risk and lower cost Cache Core GPU Cache Core GPU Core Core Analog Cache Analog Cache But requires more complex packaging solutions Page 3

4 Reliability in New Packaging Technologies Si Qualification What Customers? Application Specific Test Chips Customer Specific Supply Chains Market Analysis Leading Adaptors What Applications? Understand Drivers What Needs to be Solved? Solution Paths What Packages? What BEoL Stacks? Test Chips How to Ensure Supply Chain is Ready? Understand Barriers with Customer Architecture and Product Groups Understand system solution requirements (BW, power, height, cost) Understand impact to silicon physical environment, interconnect, structure Customer and supply chain participation in test chip design Supply Chain Design Rules, PDK, DfT Strategy, Yield Verification, Cost Roadmap, Lots of Silicon Page 4

5 New Supply Chain Model: Collaboration Consortia Tool Suppliers Material Suppliers Assembly Test Logic Foundry Memory Foundry Customer Supply chain collaboration is required to develop and deliver solutions to customers, developed around the customer s preferred supply chain. Collaboration by the experts in each field Development of solutions in one location with partners, aligned to customers preferred supply chain Early development to support BEoL definition Aligned Design Rules, PDK, Systems Partners fan-out technologies to their factories for smooth production ramp Page 5

6 Supply Chain Inter-Dependencies 3D 2.5D CuPillar Impact of Packaging on TSVs and Transistors Impact of Thinning Interposer Supply Design Rules for Supply Chain Yield Impact of Packaging on BEoL stack Stress of CuP on ELK Design Rules for Supply Chain Yield Metallurgy and Process Decisions Design Rules that Work for Packaging Definition of Yield Loss Ownership Definition of Yield Loss Ownership Test Chips for Supply Chain TSV + M3 Page 6

7 Drive Adoption by Driving Yield which Drives Cost FMEA Detect Method Detect At Test Capability Design Macros Drive Yield Process Control Defect Pareto Systematic Feedback Gather Data Correlation Page 7

8 Technology Development Center at Fab 8 Ground Break April, 2013 Fab 8.1 TDC Page 8

9 Collaborative Development at TDC for Solutions Aligned Consortia Projects Strategic Engagement Partners Customers Technology Key Elements of Technology Leading edge (14nm, 10nm, 7nm) 2.5D, 3D BSI, Bump, Assembly Development Eco-system Partners Supply chain initiatives Solutions before the industry Made in America OSAT Partners Tool Partners Memory Partners DfT Partners Key Customers Page 9

10 Thank You Trademark Attribution GLOBALFOUNDRIES, the GLOBALFOUNDRIES logo and combinations thereof are trademarks of GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners GLOBALFOUNDRIES Inc. All rights reserved. Page 10