AMORPHOUS/ MICROCRYSTALLINE SILICON THIN FILM TRANSISTOR CHARACTERISTICS FOR LARGE SIZE OLED TELEVISION DRIVING

Transcription

1 AMORPHOUS/ MCROCRYSTALLNE SLCON THN FLM TRANSSTOR CHARACTERSTCS FOR LARGE SZE OLED TELEVSON DRVNG Takatoshi Tsujimura BM Japan Abstract Amorphous silicon TFT and the TFT with microcrystalline/amorphous channel layer are studied for the OLED backplane usage. Amorphous silicon TFT V TH shift can be reduced with saturation region operation. There are two mechanisms, which causes V TH shift in saturation region. A mechanism is caused by the continuous current flow and the other is caused by the transient charge injection into gate insulator. SiH4 flow in hydrogen plasma with shorter pumping flow period than the gas residence time produces high transconductance microcrystalline/ amorphous silicon TFT. Keyword OLED, microcrystalline, amorphous, mobility, V TH shift 1 NTRODUCTON Though OLED (Organic Emitting Diode) technology has been already applied to cellular phone and car navigation for commercial product, television application is attractive to fully utilize the OLED performance, such as wide viewing angle, large color gamut, fast response time and punching capability. OLED can be driven by passive or active-matrix configuration and active-matrix configuration which does not forces high brightness emission in very short period is suitable for television use from the OLED lifetime standpoint. For the active-matrix backplane of OLED, LTPS (low temperature poly silicon) technology has been widely used. LTPS technology can deliver large ON current of driver TFT and also has merit in stability in device characteristics during operation. However, the LTPS technology has the limitation in screen size up to about 15~17 inch diagonal because the distributed laser power of laser homogenizer does not fulfill the critical laser power necessary for the crystallization when the screen size is too large. To overcome the size limitation related to the LTPS technology, amorphous silicon TFT technology and microcrystalline silicon TFT technology are attractive. While the maximum glass size of LTPS processing is 730X90mm, over meter square substrate processing is possible for amorphous silicon technology that can realize very low cost fabrication. To realize amorphous silicon TFT operation of OLED, there are two concerns, (1) low mobility and () TFT instability during operation to be solved. n SD 003 conference symposium, the author and the colleagues presented world s largest -inch OLED display with amorphous silicon backplane. 1 This paper discusses about the detailed analysis to get the minimum TFT instabilities and the further improvement to realize large mobility with compatible equipment with conventional a-si TFT equipment to make large-screen OLED operation come true. Realization of OLED backplane technology suitable for the large OLED display mentioned in this paper may have an impact on the technology transition from LCD/CRT television to OLED television.. REQUREMENT FOR OLED DRVNG WTH AMORPHOUS SLCON TFT TFT nstability requirement f neither instability reduction method nor compensation circuit is applied to a-si TFT for OLED driving, large conductance change of a-si TFT would cause large luminance difference depend on the displayed pattern and would cause image-sticking problem. To make a-si OLED driving come true, the TFT current difference must be below the human eye s perception limit, approximately equal to the one gray scale with TFT instability reduction method and pixel-level compensation circuit. There are two mechanism of amorphous silicon TFT degradation already reported, that is, (1) dangling bond formation and () charge. A.R.Hepburn et al claims that dangling bond formation in amorphous silicon is dominant. M.J.Powell reports that dangling bond formation is dominant at low driving voltage and charge trapping is dominant at higher voltage and the degradation is highly dependent on the SiNx gate insulator stoichiometry in the former case and is independent in the latter case 3. M.J.Powell made further analysis that the V TH shift of a-si TFT has power dependence on the time in the case of dangling bond formation, and logarithmic dependence in the case of charge trapping T.Tsujimura, "Amorphous/Microcrystalline Silicon Thin Film Transistor Characteristics for Large Size Oled Television Driving", Japanese Journal of Applied Physics, Vol.43, ssue 8A, pp.51 (004).

2 unless the SiNx gate insulator is Si-rich state whose degradation is dominated by the charge trapping. 4 A.V.Gelatos and J.Kanicki et al. claims that as the Capacitance-Voltage curve shift cannot explained by the Si dangling bond formation model, charge trapping into SiNx might be the degradation mechanism. 56 F.R.Libsch et al. made analysis on the productionlevel TFT and concluded that the amorphous silicon degradation is not dominated by the dangling bond formation, but can be explained Multiple Trapping Model, which attributes the degradation to the transition of band-tail excited state at the interface to the SiNx-amorphous silicon transition layer and to the 7 SiNx deep states. The model also employs the Stretched Exponential Equation to explain the V TH shift = 1 exp ( tst β V τ ) TH V0... (Eq.1) As the TFT degradation studies have been aimed at improving the LCD backplane, all the articles described above use the linear region stress condition, which uses larger gate electrode bias than the drain voltage, and actually saturation region stressing behavior remains unsolved. n this paper, saturation region stressing behavior of a-si TFT is studied and it was proved that large V TH reduction could be achieved to bring OLED driving come true with compensation circuit. TFT Current requirement Required driver TFT current for OLED driving can be described as, LMAX 9a pixel =... (Eq.) η where L MAX : peak luminance, pixel : peak pixel current, η : current efficiency of OLED device, a : pixel pitch As the maximum driver TFT current at given drain voltage can be written as, W pixel = µ COX ( VGS )... (Eq.3) L where W : channel width of driver TFT, L : channel length of driver TFT, µ : TFT field effect mobility, C OX : TFT channel capacitance, V GS : TFT gate voltage, V TH : threshold voltage of TFT Therefore required channel width of driver TFT can be written as, 18LMAX a L W =...(Eq.4) ηµ COX ( VGS ) and is anti-proportional to the ηµ value. For example, when L MAX =450 [cd/m ], η =6[cd/A], µ =0.5[cm /Vsec], V GS =10[V], required channel width of driver TFT is about 319[micron] and bottom emission AM-OLED is impossible. n addition, as amorphous silicon TFT threshold voltage changes due to the stress, pixel-level compensation is necessary. With bottom emission OLED structure, large driver TFT area reduces the flexibility of pixel circuit design that leads to the inaccurate compensation of threshold voltage shift. With top emission structure, TFT complexity can be hidden under the planarization layer as a first floor. OLED device can be fabricated in the second floor and has no filling factor impact. To fit in the OLED pixel of top emission structure, the channel width of driver TFT must be approximately equal or smaller than the OLED pixel width. f two assumptions, (1) driver TFT channel width is equal to the 0 inch WXGA display pixel size 113µm, () television luminance 300 cd/m is used (this value may be the minimum requirement as television), are applied, minimum ηµ value required can be calculated as, 18LMAX a L ηµ = =.88[( cd / A) ( cm / V sec)] WCOX ( VGS )...(Eq.5) As typical a-si TFT has 0.4~0.7[cm /Vsec], OLED device efficiency more than.88/ 0.7 = 4.[ cd / A] must be achieved to drive OLED display. This value can be easily achieved with triplet emitters and with top-level singlet emitters. However as larger ηµ value provides many advantages like luminance increase, higher TFT backplane yield with larger line and space rule, cost reduction with low voltage driver C and power reduction with lower driving voltage, large OLED device efficiency and high TFT mobility are desired. n this paper, mobility improvement with new deposition approach of channel layer is described to have further improvement listed above. 3. AMORPHOUS SLCON TFT NSTABLTY ANALYSS To use amorphous silicon or microcrystalline backplane for large size OLED display, the luminance change due to V TH shift must be under human eye s perception limit. V TH shift reduction technique should be investigated with pixel-level compensation circuit technique to achieve amorphous silicon TFT driving of large size OLED display. This paper reports that Applied Physics, Vol.43, ssue 8A, pp.51 (004).

3 saturation region operation of amorphous silicon TFT suppresses the V TH shift dramatically as compared with the linear region operation that has been studied extensively, and the OLED-driving level stress with saturation region TFT operation produces V TH shift almost without mobility degradation. This finding opens the possibility of V TH shift compensation capability without mobility compensation feature to be used for OLED backplane driving. TFT operation mode dependence of TFT degradation Fig. 1 shows the drain voltage dependence of threshould voltage shift. (V GS =10V) The TFT current can be described as follows, W COX VDS DS = µ {( VGS ) VDS } L when V DS <V GS -V TH (Linear region) and W COX DS = µ ( VGS ) L when V DS >V GS -V TH (Saturation region). Though the TFT current increases as the V DS is increased, the V TH shift in Fig. 1 decreases as the V DS is increased. This result indicates that the current stress is not dominant in the case of a-si TFT operation. The phenomena can be interpreted that, as the V DS is increased, the system is changed from linear region to saturation region and the gate/sinx/a- Si/n+a-Si/drain MS capacitor reduced its voltage stress to give lower charge injection amount into gate insulator SiNx and lower V TH shift. Vth shift [V] V DS =V V DS =10V V DS =15V Time [hours] Fig. 1 TFT degradation dependence on drainsource voltage SD/SD(t=0), µ/µ(t=0) 10% 100% 80% 60% 40% 0% Mobility Current reduction 0% Stress time [sec] Due to Mobility reduction Due to Vth shift Fig. a-si TFT current transition with saturation mode driving stress (V GS =V DS =10V) Fig. shows the a-si TFT current transition with saturation mode stress condition. The result indicates that the V TH shift dominates the most of the TFT current reduction and almost no mobility reduction can be observerd. This result indicates that the V TH compensation circuit with saturation region operation of the driver TFT without mobility compensation capability can be applied for the active-matrix OLED display. Though saturation region operation can suppress V TH shift, further V TH shift reduction is necessary to make the final V TH shift fit within the compensation voltage range after usual television usage. The following discussion depicts the further V TH shift reduction by means of the V TH shift mechanism analysis in saturation region operation. Various driving waveform to achieve OLED luminance To deliver current from driver TFT to OLED diode, there are many selections available. Fig. 3 and Fig. 4 show various examples of voltage stress waveform. The top graph in Fig. 3 shows constant current PXEL flows at any time. (DC condition) The middle graph in Fig. 3 shows 50% duty driving with double current PXEL at ON time. This operation gives also PXEL average current and the average luminance of display is the same as the top one. The bottom graph shows 5% duty driving with 4 times current 4 PXEL at ON time. This case also gives PXEL average current. Though these three cases cause the same luminance in display, the TFT stress behavior is different. (Discussion will be made in 3.3) The shape of the driving pulse also gives variation in driving. Fig. 4 shows the definition of rising time and falling time of signal pulse. With different signal Applied Physics, Vol.43, ssue 8A, pp.51 (004).

4 pulse waveform, different stress result can be obtained. (Discussion will be made in 3.3) By choosing the minimum V TH shift condition, the lifetime of amorphous silicon TFT can be enhanced. OLED PXEL OLED PXEL PXEL OLED 4 PXEL PXEL time time time Fig. 3 Various selection of duty driving V ON V GS =10/0V, Duty=5%(60Hz) V DS =10/0V, Duty=5%(60Hz) Fig. 5 illustrates the BTS test result. DC operation of both gate and drain causes larger V TH shift than the others. (Condition-1) This result indicates that the pulsed operation of a-si TFT in saturation region operation relaxes the charge injection into gate insulator and causes lower V TH shift as in the case of linear region operation. What should be noted is that Condition-, 3 and 4 show almost the same stress test result. This degradation mode may be concealed under dominant degradation mode with DC stress or the degradation may be caused by the transient phenomena under pulsed TFT operation. 1 V GS :10(DC), V DS :10(DC) Vth shift [V] V GS =10/0,V DS =10(DC) V GS =10/0,V DS =10/0 V GS =10/0,V DS =10/0,Duty: Time [hours] Fig. 5 TFT degradation dependence on the gate/drain duty ratio V OFF t RSNG t FALLNG Fig. 4 Rising time and falling time of signal pulse Duty ratio dependence of TFT degradation To judge more detailed mechanism of a-si TFT degradation, comparison between DC operation and pulsed operation is made. The a-si TFT samples are stressed with the following conditions. Condition-1 V GS =10V, DC(Duty=100%) V DS =10V, DC(Duty=100%) Condition- V GS =10/0V, Duty=50%(60Hz) V DS =10V,DC (Duty=100%) Condition-3 V GS =10/0V, Duty=50%(60Hz) V DS =10/0V, Duty=50%(60Hz) Condition-4 Pulse waveform dependence of TFT degradation To determine if the degradation with pulsed operation is caused by transient phenomena, pulse waveform dependence of drain voltage was studied. Fig. 6 shows the rising/ falling time (defined in Fig. 4) dependence. The data clearly show the waveform dependence and the degradation is accelerated with larger rising/ falling time. The reason why the slower transition from V DS =0 to V DS =10V may be the same as the reason discussed in 3.1, that is, longer operation in linear region with the sample t RSNG =t FALLNG =10µsec causes larger charge injection into gate insulator and larger V TH shift. About the degradation due to the transient phenomena, M.Hack et al. reports that after short period when the charge injection is observed, amorphous silicon dangling bond formation starts. 11 However, the degradation that is observed in this saturation region experiment has logarithmic dependence on stress time that can be explained by the charge-trapping mode, and is not the dangling Applied Physics, Vol.43, ssue 8A, pp.51 (004).

5 bond formation that creates power dependence on stress time. This experiment proves that AC driving causes transient charge trapping that does not exist in DC driving. The slower transition condition t RSNG =t FALLNG =10µsec may cause larger V TH shift, as the system is in linear region longer than the fast transition case as discussed in 3.1 Vth shift [V] V DS =10/-10V V DS =10V DC Vth shift [V] t RSNG =t FALLNG =10µsec Time [hours] Fig. 7 TFT degradation dependence on the drain/source voltage inversion - t RSNG =t FALLNG =0µsec Time [hours] Fig. 6 TFT degradation dependence on the gate pulse shape Source/Drain inversion dependence of TFT degradation Fig. 7 shows the source-drain voltage inversion dependence of TFT degradation. Nevertheless V DS is operated with pulsed operation, the V TH shift is larger than the DC sample. The reason may be also the same as the reason discussed in 3.1, that is, as during the transition from V DS =10V to 10 or 10V to 10V, TFT experiences linear region operation and causes larger charge injection and larger V TH shift. Various test result from Fig. 5 to Fig. 7 suggest that there are two V TH shift mechanism of a-si TFT. Mechnism-1) V TH shift mechanism, which appears with continuous current flow. This mechanism disappears with duty AC operation. Mechanism-) V TH shift mechanism, which is caused by transient phenomena. Longer duration in linear region accelerates the degradation. V DS inversion case in Fig. 7 case can be explained with the combination of Mechanism-1 and Mechanism-. To get the minimum V TH shift, DC operation and linear region operation must be avoided. 4. AMORPHOUS SLCON TFT CONDUCTANCE MPROVEMENT TFT mobility improvement with new deposition approach As discussed in., large ηµ value provides significant merit like, luminance, yield, cost reduction and power reduction. From the TFT backplane point of view, large mobility with stability is desired. t is very usual approach to modify CVD recipe when someone is asked to achieve high mobility. Fig. 8 illustrates typical example of amorphous silicon mobility improvement. Though large mobility can be obtained, large mobility does not accompany with TFT stability. This phenomenon can be explained with coulombic interpretation. Larger mobility value causes larger carrier flow and the probability for one Si bond to meet with a carrier increases with proportional relationship as the mobility value. To achieve large OLED television, both high mobility and TFT stability are required and this type of improvement cannot be applied for a-si driving of OLED. Applied Physics, Vol.43, ssue 8A, pp.51 (004).

6 Vth shift [%] Mobility [cm/vsec] Fig. 8 Fig. Bad example of a-si TFT conductance improvement To achieve both high mobility and TFT stability, microcrystalline TFT is attractive. Large mobility more than has been claimed with very stable BTS (Bias temperature stress) test result in some articles 1 13 with microcrystalline TFTs. LBL (Layer by Layer) technique is often used to get good crystallization. 14 With LBL technique, amorphous silicon deposition and amorphous to crystalline conversion by means of the hydrogen plasma treatment are used repeatedly to get the crystalline grain of silicon on the substrate. Though LBL technique can make crystalline silicon grain structure, the deposition rate is very low, as the technology requires H plasma treatment period to convert amorphous silicon to crystalline silicon. n addition, the most bottom region of the grain is still close to amorphous state and the unoptimized amorphous silicon causes poor conductive characteristics when bottom gate TFT is fabricated. n this paper, microcrystalline/amorphous channel layer with new deposition scheme is introduced to achieve high throughput deposition coincided with superior TFT performance. TFT with microcrystalline/amorphous silicon channel layer Background Microcrystalline silicon deposition with LBL or other technique for whole channel layer is too timeconsuming and is not adequate for production. To get the maximum throughput for the mass production, microcrystalline/amorphous silicon double channel layer is used. Fig. 9 shows the conductive characteristics of bottom gate TFT with LBL µc-si/a-si double layer. Conventional bottom gate a-si TFT shows mobility around 0.7 cm /Vsec and is higher than that of the bottom gate TFT with LBL µc-si/a-si double layer, which has around 0.6 cm /Vsec mobility value. This result indicates that the crystallization deposition does not always give the conductance merit. 0E Applied Physics, Vol.43, ssue 8A, pp.51 (004). ds [A] 7E-3 6E-3 5E-3 4E-3 3E-3 E-3 1E-3 Vgs [V] Fig. 9 Bottom gate TFT with conventional LBL intrinsic layer Experimental Condition The structural detail is as follows, Gate electrode: Molybdenum/Aluminum-Nedymium alloy stack Gate insulator: Silicon nitride Source/Drain electrode: Molybdenum/Aluminum/Molybdenum stack Though the electron flows in the channel closest to the silicon/silicon nitride interface, amorphous silicon layer also plays important role to have band bending. The total thickness of amorphous silicon layer + microcrystalline silicon layer is controlled to be 50nm in every experiment. The -V characteristics is measured with V DS =15V. n every DS -V GS characteristics curve, DS is plotted on left axis and the value which corresponds to the saturation mobility, L ( DS ) µ = ( ) [ cm / V sec] COXW VGS (-4) is plotted on the right axis. As the V DS is fixed, the measurement system changes its state from saturation to the linear region as V GS is increased. This is why the saturation mobility value apparently decreases as the V GS is increased. New deposition technique and result With conventional LBL method, hydrogen plasma treatment converts amorphous silicon to polysilicon. Therefore, the amorphous silicon, which remains in grain boundary, is susceptible to the plasma damage. To avoid the plasma damage, conversion of deposition species in gas phase should be investigated. t is reported that the deposition species such as SiH * has large tendency to react with other molecules or Mobility [cm/vsec]

7 radicals and creates polymer chains that causes particles. Particles during deposition causes interlayer short defect and must be avoided. To get the maximum dissolution of silane molecule, it is necessary to reduce the possibility of reactive molecule to meet with other silane-related molecules to prevent from polymer chain growth. A.P.Constant et al. 15 has reported the microcrystalline formation with plasma-enhanced CVD. The technique uses large H flow and high power density to terminate Si dangling bond to form crystalline phase. n this paper, microcrystalline CVD condition (Circle in Fig. 10) is used. When 5nm µc-si layer is deposited with the same condition with successive deposition of a-si 45nm layer, the mobility was 0.73 [cm /Vsec] and was slightly higher than the conventional a-si TFT, but created a lot of particles and is not suitable for production. n this experiment, SiH 4 gas was applied intermittently into constant H Plasma with long residence time enough to have gas dissolution in gas phase. Because of the dilution, deposition species have minimum possibility to be encountered with each other. As the gas residence time is long enough, gas phase dissolution may be dominant, which is different from the conventional LBL method. The residence time of deposition species can be described with the following equation. 16 V PV PV τ = = = (-5) S PS Q (V: Volume, S: Conductance of gas flow, Q:amount of gas per second) With the experimental condition used, residence time τ is about 4.03 seconds. f one SiH4 flow shot is shorter than τ, the hydrogen treatment can be made in gas phase. After SiH4 flow is stopped, SiH4 is diluted with H and the deposition system changes toward larger H/SiH4 ratio. (See arrow in Fig. 10.) As the SiH4 gas is diluted with H, partial pressure of Si species can be written as, QSiH 4tSiH 4 PSi = P QSiH 4tSiH 4 + QH th (P Si : Partial pressure of Si species, Q SiH4 : SiH4 gas flow, t SiH4 : SiH4 gas flow duration, Q H : H gas flow, t H : H flow duration) PSiV QSiH 4tSiH 4PV nsi = = RT ( QSiH tsih QH t ) H RT On the other hand, mean free path of can be describe as, ( QSiH 4t = n πd ) RT PV 1 SiH 4 H H 3 = nqsih 4tSiH 4 Applied Physics, Vol.43, ssue 8A, pp.51 (004). λ = πd + Q (λ: mean free path of Si species, d: diameter of molecule, n: amount of gas) f the H flow lasts as long as the residence time τ, mean free path can be calculated as, λ = [ m] and the Si species collides with each other 369 times until the Si species reaches at the end of the substrate and is exhausted. With this condition, no particles are observed on glass substrate and the interlalyer short defect were not observed. H/SiH4 ratio a-si phase µc-si phase Power Density [mw/cm] Condition in this study Fig. 10 Phase diagram of Plasma-Enhanced CVD with SiH4+H system The TFT characteristics with this deposition technique are shown in Fig. 11. Saturation mobility close to 1. [cm/vsec] is observed. By using the long residence time condition with maximum dissolution of gas species in the gas phase, high mobility can be achieved even with the microcrystalline/ amorphous silicon TFT structure. High mobility operation of TFT can bring larger value of ηµ and is useful for the high brightness television application. ds [A] 7E-3 6E-3 5E-3 4E-3 3E-3 E-3 1E-3 0E Vgs [V] Fig. 11 Bottom gate TFT with microcrystalline/ amorphous channel layer t Mobility [cm/vsec] [ m]

8 Fig. 1 illustrates the Mobility distribution along the gas flow in the substrate and clearly shows that the mobility is increased as the gas species are propagated. t may be the evidence that the Si species dissolution is carried out in gas phase without particle formation. To apply this technique to produce high tranconductance TFT, remote plasma system should be used to have long dissolution time of Si species. With this new deposition approach to deposit microcrystalline film and with the microcrystalline/ amorphous channel TFT structure, both high transconductance and high manufacturing throughput can be obtained. Mobility [cm/vsec] Distance [mm] Fig. 1 Mobility distribution in a glass substrate 5. CONCLUSON To realize large size OLED display, amorphous or microcrystalline silicon driving is necessary. Then mobility issue and V TH instability must be solved. Saturation region operation of a-si TFT gives smaller V TH shift. There are two V TH shift mechanism of a-si TFT in saturation region operation. V TH shift mechanism, which appears with continuous current flow, disappears with duty AC operation. Another V TH shift mechanism is caused by transient phenomena and longer duration in linear region accelerates the degradation. By choosing the driving, which does not use the DC operation and linear region operation, TFT lifetime can be enhanced. SiH 4 flow in hydrogen plasma with shorter pumping flow period than the gas residence time produces high transconductance TFT. The mobility increases as the gas species travel. With high conductance TFT and stable TFT operation, active matrix OLED display can be brighter and can be higher resolution. 6. ACKNOWLEDGEMENTS The author wish to thank the DTech, BM OLED/ TFT team members and managements. 7. REFERENCES 1 T.Tsujimura et al., A 0-inch OLED display driven by Super-Amorphous-Silicon technology, Society for nformation Display 003 Symposium Proceeding, p.6 (003) A.R.Hepburn, C.Main,J.M.Marshall, C.vanBerkel and M.J.Powell, "CHARGE TRAPPNG EFFECTS N AMORPHOUS SLCON/SLCON NTRDE THN FLM TRANSSTORS", Journal of Non- Crystalline Solids 97&98 (1987) p M.J.Powell, C. van Berkel,.D.French and D.H.Nicholls, "Bias dependence of instability mechanism in amorphous silicon thin-film transistors", Appl.Phys.Lett.51(16), p.14, (1987) 4 M.J.Powell, C.van Berkel and J.R.Hughes,"Time and temperature dependence of instability mechanism in amorphous silicon thin-film transistors", Appl.Phys.Lett.54(14), p.133, (1989) 5 A.V.Gelatos and J.Kanicki, "Bias stress-induced instabilities in amorphous silicon nitride/ hydrogenated amorphous silicon structures: s the "carrier-induced defect creation" model correct?", Appl.Phys.Lett.57 (1), p.1197, (1990) 6 J.Kanicki, C.Godet and A.V.Gelatos, "BAS STRESS NDUCED NSTABLTES N AMORPHOUS SLCON NTRDE / CRYSTALLNE SLCON AND AMORPHOUS SLCON NTRDE / AMORPHOUS SLCON STRUCTURES", Mat.Res.Soc.Symp.Proc. Vol.19. (1991) 7 F.R.Libsch and J.Kanicki, "Bias-stress-incued stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors", Appl.Phys.Lett., 6 (11), p.186, (1993) 8 Frank Libsch, "Steady State and Pulsed Bias Stress nduced Degradation in Amorphous Silicon Thin Film Transistors for Active-Matrix Liquid Crystal Displays", EDM Digest, (199) 9 F.R.Libsch and J.Kanicki, "Bias-Stress-nduced Stretched-Exponential Time Dependence of Charge njection and Trapping in Amorphous Silicon Thin- Film Transistors, "Extended Abstract of the 199 nternational Conference on Solid State Devices and Materials, pp (199) 10 F.R.Libsch and J.Kanicki, "TFT Lifetime in LCD Operation", Society for nformation Display 93 Digest, p.455, (1993) 11 M.Hack, R.Weisfield, H.Steemers, M.J.Thompson, Applied Physics, Vol.43, ssue 8A, pp.51 (004).

9 M.F.Willums and P.G.LeComber, "Transient and stress effects in amorphous silicon thin-film transistors", Philosophical Magazine B, 1994, Vol.69, No., D.French et al., Microcrystalline Si TFTs for ntegrated Multiplexers and Shift Registers, Asia Display/ DW 01 Proceedings (001), p P.Roca Cabarrocas et al., Stable microcrystalline silicon thin-film transistors produced, Journal of Applied Physics, Volume 86, Number 1 (1999), p.7079 by the layer-by-layer technique 14 R.B.Wehrspohn et al, Dangling-bond defect state creation in microcrystalline silicon thin-film transistors, Applied Physics Letters, Volume 77, Number 5 (000), p A.P.Constant, "Thin Film Transistors based on microcrystalline silicon on polyimide substrate", Mat.Res.Soc.Symp.Proc.Vol.557, p.683 (1999) 16 Fundamentals of Plasma Processing, Denki Shoin, p.15 Applied Physics, Vol.43, ssue 8A, pp.51 (004).