Effects of Solder Reflow on the Reliability of Flip-Chip on Flex Interconnections Using Anisotropic Conductive Adhesives

Transcription

1 254 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 4, OCTOBER 2004 Effects of Solder Reflow on the Reliability of Flip-Chip on Flex Interconnections Using Anisotropic Conductive Adhesives Chunyan Yin, Hua Lu, Member, IEEE, Chris Bailey, Member, IEEE, and Yan-Cheong Chan, Fellow, IEEE Abstract This paper describes the work of an investigation of the effects of solder reflow process on the reliability of anisotropic conductive film (ACF) interconnection for flip-chip on flex (FCOF) applications. Experiments as well as computer modeling methods have been used. The results show that the contact resistance of ACF interconnections increases after the reflow and the magnitude of the increase is strongly correlated to the peak reflow temperature. In fact, nearly 40 percent of the joints are open when the peak reflow temperature is 260 C, while there is no opening when the peak temperature is 210 C. It is believed that the coefficint of thermal expansion (CTE) mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a three dimensional (3-D) finite element (FE) model of an ACF joint has been analyzed in order to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process. The stress level at the interface between the particle and its surrounding materials is significant and it is the highest at the interface between the particle and the adhesive matrix. Index Terms Anisotropic conductive film (ACF), computer modeling, finite element (FE), reflow, reliability. I. INTRODUCTION THE DRIVE toward smaller, lighter, faster and cheaper electronic products makes flip-chip one of the best packaging technologies for high-end applications. Up until now, eutectic tin-lead solder has been the main stream material used in flip-chip technology but the use of lead in the electronic devices is becoming a more and more serious concern for the consumers and the manufacturing industry due to the alloy s arguably harmful impact on the environment. As part of the effort to achieve green electronics manufacturing, many research activities are now focused on the alternative interconnection materials to tin-lead solder in the electronic packaging industry. Anisotropic conductive film (ACF) which is a particular form of conductive adhesives has attracted a great deal of attention since last decade due to its potential in achieving high-density I/O interconnection and its relative mild impact on the environment. ACFs contain no lead, do not need fluxes or cleaning solvents, and the processing temperature is much lower than that for solder. The types of electronic devices in which ACFs Manuscript received May 4, 2004; revised October 5, This work was supported by the University of Greenwich and the City University of Hong Kong. C. Yin, H. Lu and C. Bailey are with the School of Computing and Mathematical Sciences, The University of Greenwich, London, SE10 9LS U.K. Y.-C. Chan is with the Department of Electronic Engineering, City University of Hong Kong ( C.Yin@gre.ac.uk). Digital Object Identifier /TEPM have been used include chip on board (COB), chip on glass (COG) and more recently chip on the flexible (COF) printed circuit substrate. However, being a relative new technology, ACF flip-chip technology suffers from the drawback of having less reliability data compared with the traditional soldering technology [1]. Therefore any research that generates reliability data and/or helps to understand the failure mechanism of ACF components is deemed to be welcome by the electronic packaging industry. The reliability problem of ACF components is complicated by the fact that ACFs and solder are often used on the same device. In the process of manufacturing this type of devices, the first step is usually to use ACF bonding to achieve high accuracy for fine-pitch placement of some components, and then this is followed by a standard solder reflow process for the formation of the solder interconnections. This approach would allow the advantages of both technologies to be exploited. However, the ability of ACFs to survive solder reflow has been a major concern in this combination process [2]. The aim of this research is to study the effect of solder reflow on the reliability of ACF interconnections. The first part of this work is to assemble a number of flipchips on flexible substrates using ACFs and then subject these components to the solder reflow treatment. Before and after the solder reflow, the contact resistance of the ACF interconnections was measured and used as an indicator of the electrical contact quality of these interconnections. The samples were also cross sectioned and examined using scanning electron microscopy (SEM). The second part of the work is the application of computer modeling method in the analysis of the ACF flip-chips. This part of the work helps to understand the role solder reflow plays on the flip-chips. The influence of geometric, material and process parameters, such as the reflow peak temperature, the coefficient of thermal expansion (CTE) of the adhesive matrix, bump height on the reliability of the ACF interconnections has also been studied. II. EXPERIMENTAL PROCEDURE To investigate the effect of solder reflow on the reliability of ACF interconnections for flip-chip-on-flex (FCOF) applications 20 samples were prepared. A. Test Chip and Substrate The dimensions of a test chip are 11 mm 3 mm with a total of 368 Ni Au bumps arranged along the periphery. The X/04$ IEEE

2 YIN et al.: EFFECTS OF SOLDER REFLOW ON THE RELIABILITY OF FLIP-CHIP ON FLEX INTERCONNECTIONS 255 Fig. 1. Schematics showing a Si chip with daisy-chained bumps. TABLE I SPECIFICATION OF THE ACF Fig. 2. Contact resistance measurement of ACF joints using four point probe method. TABLE III CONTACT RESISTANCE AT DIFFERENT PEAK REFLOW TEMPERATURE TABLE II BONDING PARAMETERS FOR ACF BONDING reflow oven. Three reflow temperature profiles were used in the experiment. The peak temperatures of these profiles are 210 C, 230 C and 260 C, respectively. These peak temperatures cover the range of reflow temperatures of both eutectic SnPb and leadfree solder materials. To achieve these reflow profiles thermal couples were attached to the samples in the calibration process. The samples were put into the reflow oven directly without any protection. dimensions of bumps are 50 m 50 m 4 m. There are 60 daisy-chained bump-groups that run parallel to the length of the chip for electrical connection and another 68 bumps for mechanical support run along the width (see Fig. 1). The adhesiveless flexible substrate used in the experiment is 25- m-thick polyimide and the overall dimensions of the substrate are 50 mm 50 mm. The metal pads on the flexible substrate are made of nickel-gold plated copper. The thicknesses are 12, 4, and 0.5 m for the copper pad, nickel and gold coatings, respectively. B. ACF Materials and Bonding Process A commercial ACF with a thickness of 35 m was used in this study. The specification of this ACF provided by the supplier is summarized in Table I. The flip-chip bonding process was carried out using a Toray Semi-Automatic Flip-Chip Bonder (Toray SA2000). The procedure for the flip-chip mounting consists of several steps: 1) ACF placement and lamination onto the substrate (prebonding); 2) peeling off the cover film; 3) aligning IC chips; and 4) bonding by applying heat and pressure. The schematics of this bonding process can be found in the literature [3]. The bonding conditions used in this experiment are summarized in Table II. C. Solder Reflow After the bonding process, the FCOF assemblies were glued onto printed circuit boards (PCB) and then passed through a D. Experimental Results The contact resistance of the FCOF assemblies was measured by using the four-point probe method and the circuit diagram is shown in Fig. 2. The specifications of the reflow profiles and the related contact resistance measurement results are summarized in Table III. When the peak temperature was 210 C, no open joints were found and the contact resistance was increased by 23 m. When the peak temperature was 230 C, 5% joints were open and the contact resistance increase was 29 m. When the peak temperature was 260 C, nearly 40% open joints were found, and the contact resistance was increased by 60 m. As shown in Fig. 3(a), the conductive particles deformed very well and had a good contact with conductive metallization surfaces before solder reflow. Although no conduction gap had been found after the reflow processes with a 210 C or 230 C peak temperature, the contact areas between the particles and the conductive metallization surfaces decreased. This could be the main cause of the contact resistance increase after reflow. In Fig. 3(d), the formation of the conduction gap is clearly visible after the reflow process with a peak temperature of 260 C. Unlike solder interconnections, the conductive particles are part of the conduction path in an ACF interconnection. The electrical connection between conducting particles and the surrounding metallization is maintained by the contact pressure caused by the elastic/plastic deformation of the particles. Loss of the electrical contact may occur when the adhesive expands in the vertical direction [4]. Owing to the CTE mismatch between

3 256 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 4, OCTOBER 2004 Fig. 3. SEM photos showing the ACF interconnection through conductive particles (a) as-bonded at 200 C, 86.2 Mpa, 10 s, and after reflow with the peak temperature at (b) 210 C, (c) 230 C, and (d) 260 C. the adhesive matrix and the conductive particles (70 C for the polymer particle, 133 C for the adhesive matrix), the expansion of the adhesive matrix is much greater than that of conductive particles when the COF samples are heated during solder reflow. This CTE mismatch could be the cause of the degradation of ACF interconnections in the reflow process. As the COF samples are heated up to over 200 C, the adhesive matrix tries to expand much more than the tiny conductive particles, the induced thermal stress has the tendency to lift the bump from the pad and decrease the contact area of the conductive path and this may lead to the complete loss of electrical contact. For a better understanding of this issue, computer modeling methods were used to analyze the role of solder reflow in the reliability of ACF interconnections. III. COMPUTER MODELING ANALYSIS The simulation of the ACF flip-chip under reflow thermal loading was carried out using the multiphysics software package PHYSICA. Information about this software can be found in the [5]. A. Model Development and Material Properties ACF bonding and the subsequent reflow is a complicated physical and chemical process that involves heat transfer, fluid flow, solid deformation and chemical reaction [6]. In this work, only thermal-mechanical stress during reflow is analyzed. In order to simplify the analysis, the stress created in the bonding process is assumed to be negligible. This means the model is stress free at the reference temperature. Another simplification that has been made concerns the vast range of length-scales in an ACF flip-chip. While the thickness of the particle metallization is about 50 nm and the die is 11 mm in length: the ratio of the two is approximately 1:! In addition, the number of conducting particles is several thousands. All this means that an exact model which includes all the particles and interconnections is simply not achievable with today s computer technology. Therefore, a simplified three-dimensional (3-D) model that includes only the vicinity of a single bump was built. In this model, a single conducting particle is placed in the middle part of the area between the bump and the pad. Furthermore the bump was assumed to be in the middle of the chip so that only one fourth of it needs to be modeled due to the four-fold symmetry of the geometry. Fig. 4 shows the model with one enlarged section so that the particle and the coating layers are visible. In this model, the die, the substrate, the polymer foil and the core of the conducting particles are treated as elastic materials, but the metals are assumed to be elastic-plastic. The basic material properties are given in Table IV. In addition, the yield strength of the Au coating layer is 170 Mpa, which is different from the bulk property of this metal [7]. Since most materials are elastic, static stress analyzes with thermal loads equivalent to the peak reflow temperatures were carried out. The stresses can be interpreted as the maximum stresses the flip-chip may experience during the reflow processes. B. Modeling Results Fig. 5 shows the stresses in the ACF joint at the 210 C peak reflow temperature. The distribution pattern of the stress

4 YIN et al.: EFFECTS OF SOLDER REFLOW ON THE RELIABILITY OF FLIP-CHIP ON FLEX INTERCONNECTIONS 257 Fig. 4. Computer model of the typical ACF joint. TABLE IV MATERIAL CHARACTERISTICS USED FOR THE SIMULATION shows that the interfaces between the particle and other materials are subject to higher stress area than other regions. The highest stress was found at the interface between the particle and the adhesive matrix. The integrity of an ACF interconnection is normally judged by the contact resistance which depends on the contact quality between the particles and pads. Owing to the CTE mismatch of the materials in ACF joints, the contact regions are subject to tensional forces during the reflow process and the loss of contact area of the particles interconnections may occur if the stresses at the interface between the particles and pads are high. The reduction in the contact area size may result in an increase in the contact resistance, and in time this may leads to electrical failure. In order to understand how reflow profiles, material properties and geometric parameters affect the stress levels in the ACF flipchips, a detailed parametric analysis has been carried out. The effect of the reflow peak temperature, the CTE of the adhesive matrix and the bump height has been investigated. 1) Effect of the Reflow Peak Temperature: Three reflow profiles were programmed into the software package as the thermal loads. The effect of reflow peak temperature on the reliability of ACF interconnections was analyzed based on the interfacial stress values. The values of stress at the interface between the particle and pad at the three peak temperatures are shown in Fig. 6. The abscissa represents the distance from the centre of the interface to the point of measurement. The stress decreases first and then increases, reaching the highest value at the interface between the particle and adhesive matrix. The stress also increases with the reflow peak temperature. In fact, about 75% stress variation has been observed when the peak temperature changed from 210 C to 260 C. This shows that the peak reflow temperature that corresponds to lead-free solder may have a great influence on the reliability of ACF interconnections. 2) Effect of the CTE of the Adhesive Matrix: Some previous research works have shown that anisotropic conductive adhesive (ACA) materials with low CTE can significantly enhance thermal cycling reliability of ACA interconnections [8]. To prove this and to estimate the extent at which the CTE of the adhesives can have on the reliability, models with different CTE values have been analyzed. The values of at the interface between the particle and pad with different adhesive matrix CTE values (C C, C C and C C) have been recorded at a fixed peak reflow temperature 210 C and the results are shown in Fig. 7. It has been found that the CTE of adhesive matrix has a great effect on the stresses at the interface. The interfacial tensional stress increases with the CTE of the adhesive matrix, and therefore the reliability of ACF interconnection decreases with the CTE value. 3) Effect of the Bump Height: As an example to show how geometric design parameters may affect the reliability of the

5 258 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 4, OCTOBER 2004 Fig. 5. Stress distribution in the ACF joint. Fig. 6. Interfacial stresses at different peak reflow temperature. Fig. 8. Interfacial stresses with different bump height. Fig. 7. Interfacial stresses with different ACFs CTE. ACF flip-chips, models with three different bump heights have been analyzed. The stress values at the interface between the particle and pad with different bump height have been presented in Fig. 8. It can be seen in the figure that the interfacial stress increases with the bump height. This conclusion contradicts what has been observed in solder based flip-chips but corroborates well with experimental results for ACF joints [9], [10]. This difference between solder and ACF connections reflects the fundamentally different ways in which stress exert its degradation influence. In solder joints the in-plane shear stress causes solder fatigue, but in ACF joints the normal tensional stress damages the contact area. After the flip-chip bonding process, the thickness of the adhesive layer (the distance between the chip and substrate) is mainly dependent on the height of bump and pad. So the effect of initial ACF thickness on the reliability is not considered in this paper. However, the thickness of ACF does affect the flow process during the flip-chip bonding due to the significant temperature gradients which can occur through the adhesive film thickness and the amount of the adhesive that takes part in the viscous flow process [6], [7]. The work presented in this paper has shed some lights on the reliability issue of ACF joints during the reflow process, but the model is too simple to include the effect of the global CTE mismatch and the effect of the conducting particle locations on the reliability. These effects will be studied using a macro-micro modeling method in the future.

6 YIN et al.: EFFECTS OF SOLDER REFLOW ON THE RELIABILITY OF FLIP-CHIP ON FLEX INTERCONNECTIONS 259 IV. CONCLUSION The effect of solder reflow on the reliability of ACF interconnection for FCOF assemblies has been studied using experimental and computer modeling methods. It has been found that the contact resistance of ACF interconnections increased after the reflow process. The extent of this increase is dependent on the reflow peak temperature. At a peak reflow temperature 260 C nearly 40% of the joints were open after being subjected to the solder reflow. 3-D finite element (FE) models with predeformed particles were built and analyzed using the software package PHYSICA. It was found that owing to the CTE mismatch between the materials in the ACF flip-chips, the stresses at the interface between the particle and its surrounding materials are significant and are the highest at the interface between the particle and the adhesive matrix. The interfacial stress increases with the reflow peak temperature. The CTE of adhesive matrix and bump height also have an effect on the interfacial stress. It is believed that high stresses would cause contact area loss and, thus, an increase in contact resistance. ACKNOWLEDGMENT C.Y. Yin would like to thank M.O. Alam of the City University of Hong Kong for his help in the SEM experiments. REFERENCES [1] J. Liu et al., Conductive Adhesives for Electronics Packaging. London, U.K.: Electron Chemical, 1999, pp [2] Anisotropic conductive film for flip-chip applications: An introduction. Tutorial 05. [Online]Available: [3] C. Y. Yin, M. O. Alam, Y. C. Chan, C. Bailey, and H. Lu, The effect of reflow process on the contact resistance and reliability of anisotropic conductive film interconnection for flip chip on flex applications, Microelectron. Reliab., vol. 43, pp , [4] Y. C. Chan, K. C. Hung, C. W. Tang, and C. M. L. Wu, Degradation mechanism of anisotropic conductive adhesive joints for flip chip on flex applications, in Proc. 4th Int. Conf. Adhesive Joining and Coating Technology in Electronics Manufacturing, Jun. 2000, pp [5] PHYSICA Multi-Physics Ltd.. [Online]. Available: uk/~physica [6] D. C. Whalley, L. Chen, and J. Liu, Modeling of the anisotropic adhesive assembly process, in Proc. 4th Int. Symp. Electronic Packaging Technology, Beijing, Aug. 2001, ISBN , pp [7] R. Dudek, S. Meinel, A. Schubert, B. Michel, L. Dorfmüller, P. M. Knoll, and J. Baumbach, Flow characterization and thermo-mechanical response of anisotropic conductive films, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 22, no. 2, pp , Jun [8] M. J. Yim, Y. D. Jeon, and K. W. Paik, Reduced thermal strain in flip chip assembly on organic substrate using low CTE anisotropic conductive film, IEEE Trans. Electron. Packag. Manuf., vol. 23, no. 3, pp , Jul [9] K. Pinardi et al., Effect of bump height on the strain variation during the thermal cycling test of ACF flip-chip joints, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 23, no. 3, pp , Sep [10] C. M. L. Wu, J. Liu, and N. H. Yeung, The effects of bump height on the reliability of ACF in flip-chip, Soldering and SMT, vol. 13, pp , Jan Chunyan Yin received the B.Sc and M.Sc. degrees in material science and engineering from Harbin Institute of Technology, China, in 1999 and 2001, respectively. She is currently working toward the Ph.D. degree in School of Computing and Mathematics Sciences at the University of Greenwich, London, U.K. From 2001 to 2002, she worked as a Research Assistant in the Center for Electronic Packaging and Assembly (EPA) at City University of Hong Kong. Her research work has been focused on the reliability of fine picth assembly using conductive adhesives. Hua Lu (M 01) received the M.Sc. degree in condensed matter physics from Wuhan University, Wuhan, China, in 1988 and the Ph.D degree in computational physics from University of Edinburgh, Scotland, U.K., in From 1992 to 1995, he worked as a Postdoctoral Research Associate at the University of Sheffield, U.K. In 1995, he joined the University of Greenwich, London, U.K., as a Research Fellow and he is now a Senior Research Fellow. His research interests are computational physics and computational engineering. He has published many papers in these areas. Chris Bailey (M 98) received the MBA degree in technology management and the Ph.D. degree in computational mathematical modeling from the University of Greenwich, London, U.K. He is currently a Professor of Computational Mechanics at the University of Greenwich, London, U.K. He spent three years at Carnegie Mellon University, Pittsburgh, PA. His interests are in the development and use of software tools to predict the behavior of materials in manufacturing processes and end products. Over the last ten years he has managed many industrial and government funded projects related to modeling of manufacturing processes and materials behavior. He is also a consultant to a number of companies in the area of virtual prototyping technologies. Dr. Bailey is a member of the IEE, the Society for Industrial and Applied Mathematics (SIAM), the Institute of Mathematics and its Applications (IMA), and The Materials Society (TMS). Yan-Cheong Chan (M 85 SM 95 F 04) received the B.Sc. degree in electrical engineering, the M.Sc. degree in materials science, and the Ph.D. degree in electrical engineering, all from Imperial College of Science and Technology, University of London, London, U.K, in 1977, 1978, and 1983, respectively, and the M.B.A. degree in finance from the University of Hong Kong Business School, Hong Kong, China, in In 1983, he joined the Advanced Technology Department of Fairchild Semiconductor in California as a Senior Engineer, and worked on integrated circuits technology. In 1985, he was appointed to a Lectureship in Electronics at the Chinese University of Hong Kong. From 1987 to 1991, he worked in various senior operations and engineering management functions in electronics manufacturing (including SAE Magnetics (HK) Ltd. and Seagate Technology). He set up the Failure Analysis and Reliability Engineering Laboratory for SMT PCB at Seagate Technology (Singapore). He joined City Polytechnic of Hong Kong (now City University of Hong Kong) as a Senior Lecturer in Electronic Engineering in He is currently Chair Professor of Electronic Engineering and Director of the EPA Center, and Assistant Head for Applied Research and Industry Relations in the Department of Electronic Engineering. He has authored or coauthored over 140 scientific publications in peer-reviewed journals, over 70 international conference papers, and coedited three books. His current research interests include advanced electronic packaging and assemblies, failure analysis, and reliability engineering. He is world renown in electronic product reliability, and has had extensive industrial connections in the local electronics and manufacturing industry. Professor Chan is currently Fellow of the Hong Kong Institution of Engineers and the Institution of Electrical Engineers (UK). He served as in the Executive Committee of the IEE Hong Kong for eight years and as Chairman from 1995 to He was Founding President (2001) and is presently Honorary Chairman of the Hong Kong Electronic Packaging and Manufacturing Services Association. He is currently serving as member of the HKIE Examination and Education committee representing the electronics discipline. Worldwide, he has chaired numerous international technical conferences in electronic product reliability and green electronics, and participated as organizing committee member/international advisor on many others.