Novel Dielectric Etch Chemistry for the next generation of Circuit Edit: Delicate to Low-k Dielectrics and Silicon

Transcription

1 ISTFA 2009, Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis November 15 19, 2009, San Jose, California, USA, p Copyright 2009 ASM International All rights reserved. Novel Dielectric Etch Chemistry for the next generation of Circuit Edit: Delicate to Low-k Dielectrics and Silicon Vladimir V. Makarov*, Leo Krasnobayev, Tiza Lab, LLC, 1665 S. Main Street, Milpitas, California, USA Sabina F. Misquitta Advanced Circuit Engineers, LLC, 316 S. Abbott Avenue, Milpitas, California, USA Abstract A novel solution is presented for dielectric and silicon etching when using FIB for circuit edit. In contrast to commonly used XeF 2, the new solution has a significantly higher activation threshold that allows it to be used for etching new sensitive low-k dielectrics and even thin silicon without the risk of damaging these materials spontaneously. Examples of operations presented are: etching through ultra low-k dielectrics on a front side device, exposure of a conductor through shallow trench isolation (STI), and trimming active silicon when performing circuit edit on a back side device. The advantages in comparison to XeF 2 applications are discussed. Introduction Performing circuit edit (CE) using a FIB on an integrated circuit (IC), is essential for design debug and failure analysis [1]. Fragile, thin inter layer dielectrics and an increase in line and device densities inside semiconductor ICs make CE using the FIB challenging. CE on ICs is performed either from the front side, which is the metallization side, or through silicon from the back side. In both cases, the removal of dielectric and other non-metallic materials to expose the metal line(s) of interest for further edit is one of the key CE operations. Currently, the most used FIB chemistry for dielectric and Silicon removal is XeF 2. This compound was used for decades in the FIB as a reliable dielectric etchant. With the introduction of flip-chip package technology and new low-k dielectrics in the IC industry, XeF 2 revealed some properties that made its use difficult or, in some cases, impossible. Fluorine in the XeF 2 molecule is connected to a noble gas atom and this bonding is relatively weak. As a result, the fluorine from XeF 2 can attack some materials like silicon and some low-k dielectrics either spontaneously or after a very slight external push. Obviously, this makes the use of XeF 2 in the CE of flip-chip devices complicated, where the access to the circuitry can only be obtained through the active silicon. Deposition of protective dielectrics and other precautions must be taken to avoid deterioration of the active silicon by XeF 2, which makes CE more time-consuming and less reliable. One can expect the same sort of problems to occur with low-k dielectrics with weak Si-C bonds. When using XeF 2 through a stack of inter connects on a front side device, this spontaneous attack may lead to aggressive and uncontrolled etching of the low-k dielectrics in the lateral directions [2]. Unwanted lateral etching of dielectrics can increase the complexity and difficulty of the subsequent CE operations leading to lower yields. Therefore, a new solution is required to overcome these difficulties. This kind of solution Novel Dielectric Etch (NDE) is presented in this paper. Application of the New Dielectric Etch Solution for CE on front side devices In this section, the data for using XeF 2 and NDE for etching holes through multiple layers that include sensitive low-k dielectric layers is compared. In Fig 1a, one can see two examples of so-called ballooning lateral broadening of the etched holes when doing this operation using XeF 2. Obviously, the uncontrolled lateral etching occurs in the layers of low-k dielectrics. Though the damage caused by this unwanted etching is not extensive, from the view point of the dimensions, it can potentially compromise the whole CE operation. Fig.1a, b Lateral broadening of the hole when coming through sensitive low-k dielectrics using XeF 2. In both examples one can see that the broadening happens in the dielectric layers while the intermediate thin delimiting layers (probably, etch stoppers) show good resistance to XeF 2 aggression. b) 106

2 As one can see from Fig.1c, application of the NDE on the same structure as the two examples above does not show any damage of low-k dielectric layers. Area of possible corrosion caused by lateral over-etch FIB Access holes FIB deposited protective dielectric Si STI Si c) Fig.1c The new Dielectric Etch Solution does not show any lateral uncontrollable etching when doing the same operation on the same structure as in Fig.1a, b. Application of the New Dielectric Etch Solution for CE on flip-chip devices In the case of CE on flip-chip devices, the first operation requires a fast and coarse etching of large (about 200x200 m) trenches through thick Silicon [3]. In this case, the aggressive formation of the SiF 4 (gas) is beneficial for the fast removal of Silicon. The trenching operation is followed by an etch operation to access the active silicon. At this point, XeF 2 cannot be used since it is very aggressive to Silicon, and exposure of the active silicon to XeF 2 may compromise the operation of active elements of the circuitry. Currently, the normal practice is to use an Iodine-based chemistry to expose the area of interest down to the STI level. Once the STI level is reached (and active silicon is exposed), one needs to expose conducting lines (usually copper lines) beneath STI. At this point, one cannot use the XeF2 (which is damaging to the active silicon) or Iodine (which corrodes the copper). To overcome this problem, the trench floor and the surrounding areas are covered with FIB deposited insulator prior to accessing the metal line of interest [4]. Not only does this operation make the backside CE process longer, but, in cases where the access hole is to come through spatially dense active silicon, the CE becomes impossible. Figure 2 illustrates a scenario in which damage occurs when etching an access hole to a metal line, which is too close to the active silicon. Metal Lines to be exposed Fig. 2 Illustra 2 1 Fig. 2 Illustration of possible risk of active silicon damage when using XeF 2 to access a line that is too close to the active silicon. Note that FIB deposited protective dielectric cannot resolve the issue. Line 1 is accessed safely, but the access hole to line 2 is too close to the active silicon and a lateral spontaneous over-etch occurs on the active silicon when XeF 2 is used. Such unwanted corrosion of active silicon will destroy the device and jeopardize the CE operation. Application of the NDE instead of XeF 2 resolves these problems. As NDE is benign to bare silicon, there is no need to put protective dielectric over the exposed active silicon. The lines of interest can be accessed directly. Figure 3 shows copper metallization exposed through STI in between two uncovered silicon areas using XeF 2 and the new etchant. Lateral spontaneous etch of the active silicon by XeF 2 damages the neighboring active silicon, Fig 3a. The new dielectric etchant is used in a similar location where the spontaneous etching of Silicon is absent and the access hole is clean, Fig 3b. 107

3 b) b) Fig.3. Etch using XeF 2 to expose copper lines in between two active silicon areas causes damage to the neighboring active silicon. b) Same procedure as in but using NDE which is benign to the neighboring active silicon. Moreover, in case the CE plan requires, the NDE allows cutting through active silicon as it is shown in Figs.4a, b. Fig.4a demonstrates a cut through the diffusion area and the exposure of tungsten contacts to this area from the M1 layer. This sort of operation is absolutely impossible when XeF 2 is used because of its aggressiveness to silicon. Besides, the tilted view of this area in Fig.4b, demonstrates significant selectivity of the etching process using the NDE for tungsten and silicon: note the high pillars of the tungsten contacts after silicon removal. This means that one can expect also a serious advantage of SiO 2 (and other dielectrics) etching rate(s) compared to tungsten etching rate when using NDE, which could be very beneficial for the CE on ICs with fully tungsten metallization like some memory microchips. However, additional characterization will be necessary to confirm this expectation. Fig.4. Removal of active silicon using NDE to expose tungsten contacts to M1: top view, b) tilted view (45 degrees). This advantage of the NDE over XeF 2 and Iodine the possibility of cutting through thin (0.5um or less) diffusion layers to access copper metallization, - was demonstrated, in this work, on a flip-chip with 40nm technology. Case Study: Shorting of inverter input/output contacts to copper M1 on a flip-chip device This work was done in several steps on two FIB instruments: The flip-chip device was etched through Silicon to create a large trench (~200x200um). The trenching process was stopped after n-well contrast had been revealed (see Fig. 5). Fig.5 Trench for the case study on NDE application. In the second step CAD navigation was used to find and expose the area of interest (the inverter) and to create landmarks (Fig.6). Up to this point, the operations were done on the DCG OptiFIB instrument. 108

4 Fig. 6 Locally opened STI and active Silicon show target points of the inverter (arrows). Top and bottom arrows show location of the inverter outputs. The middle arrow shows where M1 must be opened to contact the gate. After the opening above had been created, the device was relocated to the instrument equipped with NDE chemistry. The etching of the STI and active Silicon was done in a one box operation (150nm x 650nm) to expose contacts to the inverter outputs and to expose M1 in between (Fig.7). After that the device was returned back to the OptiFIB to finish the edit with conductor deposition to short the exposed contacts. Prior to the deposition on the OptiFIB, the exposed contacts were cleaned with raw beam sputtering and a picture of the area of interest was taken (Fig.7. Occasionally the area of interest is turned 90 degrees clockwise with respect to Fig.6) Fig. 7 Tungsten contacts to inverter outputs and M1 in between are successfully exposed through diffusions and SiO 2 using NDE. No corrosion on the exposed adjacent Silicon is observed. The whole CE operation was completed with the deposition of low resistivity conductor to short three exposed contact. Successful electrical verification of the (expected) device functionality was established. This work has shown that NDE can be used to trim diffusion structures vertically or laterally for CE or device analysis [5]. b) 109 Definitely, these abilities of the new solution will be beneficial for newer CE methodologies [6]. Conclusions In this work, a new FIB dielectric etch solution is proposed. Compared to the commonly used XeF 2, this solution shows no signs of uncontrolled etching of silicon and the newest sensitive ultra low-k dielectrics. Obviously, for CE on front side devices, this solution has a significant advantage over XeF 2 in those cases where new sensitive dielectrics are involved. Regarding CE on back side devices, this advantage becomes even more significant as the new Dielectric Etch solution not only allows CE operations on STI with unprotected active silicon, but also allows trimming diffusions an operation that cannot be done with XeF 2 in principle. Apparently, one should expect a significant increase in the number of reports on successful use of the NDE as it will definitely expand the common practice of CE on back side devices. Promising data were obtained on significant selectivity of the new dielectric etch process over tungsten, which can be another advantage of the NDE over XeF 2 for CE on ICs with tungsten metallization. Acknowledgments The authors would like to thank Jeff Large, Texas Instruments, and Rajesh Jain, DCG Systems, for their inputs, discussions and assistance. References [1] T. Malik, R. Jain, R. Nicholson, T. Lundquist Role of Circuit Edit in Post-Silicon Debug and Diagnosis, presentation at 2nd IEEE Silicon Debug & Diagnosis Workshop, November 2005, Austin, TX [2] C. Richardson, LSI Logic and Jeff Large, TI, Dallas Private Communication, 2008 [3] C. Rue, S. Herschbein, C. Scrudato, Backside Circuit Edit on Full-Thickness Silicon Devices, presentation at 12th European FIB Users Group Meeting (EFUG), September 2008, Maastricht, the Netherlands [4] R Lee, N Antoniou, FIB Micro-surgery on Flip Chips from the Backside, Proc 24 th Int l Symp for Testing and Failure Analysis, Dallas, TX, November 1998, pp [5] Boit, C. et al., Impact of Backside Circuit Edit on Active Device Performance in Bulk Silicon ICs, Proc 36 th IEEE Int l Test Conf, Austin, TX, November 2005, pp [6] R. Schlangen, P.Sadewater, U. Kerst, C. Boit Contact to Contacts or Silicide by Use of Backside FIB Circuit Edit allowing to approach every Active Circuit Node Microelectronics Reliability 46 (2006)

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