Automated High-Throughput Assembly for Photonic Packaging

Transcription

1 Automated High-Throughput Assembly for Photonic Packaging IBM Assembly and Test - Bromont IBM Research - Watson / TRL P. Fortier N. Boyer A. Janta-Polczynski E. Cyr R. Langlois Y. Yoshi H. Numata T. Barwicz 1 Photonics Summit, Cadence, 6 th September 2017, San Jose 2016 IBM Corporation

2 IBM Assembly and Test Bromont, Canada 850K sq. ft. Manufacturing Facility 160K sq. ft. Dedicated Development Facility (C2MI) Photonics Summit, Cadence, 6 th September 2017, San Jose CA 2

3 IBM Packaging Development & Research IBM Assembly & Test, Bromont IBM Tokyo Research Lab IBM T.J. Watson Research Center IBM Zurich Research Lab Photonics Summit, Cadence, 6 th September 2017, San Jose CA 3

4 What to do in Bromont? Photonics Summit, Cadence, 6 th September 2017, San Jose CA 4

5 Outline 1 2 Introduction Silicon Photonic Packaging Vision Fiber array Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 5

6 Historical view of packaging Device: Complex Packaging: Childs play Where the innovation is Brick wall An afterthought Photonics Summit, Cadence, 6 th September 2017, San Jose CA 6

7 Packaging The new era Device performance improvement scaling by node is slowing Devices run hotter and are more fragile Disaggregate functionality > Package integration Packaging innovation SiP 2.5D / 3D Optical Performance Thermal Management Electrical Performance Cost Reliability Manufacturability Packaging is critical for success Co-design with packaging CPI Miniaturization Photonics Summit, Cadence, 6 th September 2017, San Jose CA 7

8 Cost breakdown Packaging cost is a big piece of the pie for Photonics Microelectronic packaging is geared towards low cost Photonics Microelectronics Packaging / Test Device Packaging is key to lower cost of photonics Leverage the microelectronic industry Photonics Summit, Cadence, 6 th September 2017, San Jose CA 8

9 Trends in data communication and processing Increased use of SM optics in the Datacenter Optical Connector Photonic IC CPU / ASICS Bandwidth density Reach Card edge Optics integration: Moving closer to the processing Signal speed Bandwidth density Mid-Board BGA or socket Embedded Packaging will play a key role Silicon Photonics well suited to enable above trends Photonics Summit, Cadence, 6 th September 2017, San Jose CA 9

10 Outline 1 2 Introduction Silicon Photonic Packaging Vision 3 Fiber array 4 5 Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 10

11 Silicon Photonic Packaging Vision Manual / Low volume Automated / High volume Active alignment One connection at a time Custom design Self alignment Multiple connections at a time Standard design Lower packaging cost / Increased scalability Leverage Microelectronic Packaging Infrastructure / Knowhow Photonics Summit, Cadence, 6 th September 2017, San Jose CA 11

12 Packaging Development Focus Areas Typical 2D MCM package with integrated optics ASICS Electrical IC Silicon photonics Ferrule Clip Optical path Photonic flipchip Fiber Polymer Connector (pluggable) Can be applied to 2.5D and 3D package configurations Photonics Summit, Cadence, 6 th September 2017, San Jose CA 12

13 Outline 1 2 Introduction Silicon Photonic Packaging Vision Fiber array Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 13

14 Fiber Array Concept MT fiber ferrule V-groove / butt couple to SiPh chip Standard MT ferrule fiber stub Polymer lid V-groove array Parallel channel array (12ch TV) O, S, C, L bands compatible Couples both polarizations (TE / TM) Assembly using high throughput pick n place tools Photonics Summit, Cadence, 6 th September 2017, San Jose CA 14

15 Fiber Array Concept T.Barwicz et al. OFC 2015 A A V-groove Venting holes Top view without fiber / lid Lid Suspended membrane Mode converter Fiber Adhesive Section A-A: 3D tomography Photonics Summit, Cadence, 6 th September 2017, San Jose CA 15

16 Fiber Array Assembly Sequence N.Boyer et al. ECTC 2017 Dual vacuum pick-tip Buffer feeding Fiber stub feeding Ferrule vacuum port Buffer vacuum port UV transparent picktip UV light Silicon chip Angled sliding plane Off the shelf fiber stub Dual vacuum picktip handles fiber stub and buffer separately Photonics Summit, Cadence, 6 th September 2017, San Jose CA 16

17 Fiber Array Self-alignment T.Barwicz et al. ECTC 2015 Montecarlo tolerance analysis (SS=10K) Tolerances V-groove Fiber core Fiber clad Chip lid Fiber Picktip Lid Close-up of fiber to Si WG alignment Photonic die Si WG Fiber clad Fiber core Self alignment to < 2µm Photonics Summit, Cadence, 6 th September 2017, San Jose CA 17

18 Fiber Array Lateral fiber butting T.Barwicz et al. ECTC 2015 Picker Angle sliding plane Sliding base Chip moves this way Self Forcealignment to < 2µm decomposition Sliding force Fixed base Controlled vertical force translated to horizontal motion for fiber butting Compatible with high throughput placement tools Photonics Summit, Cadence, 6 th September 2017, San Jose CA 18

19 Fiber Array Fiber position validation Fiber A A Assembly Section A-A Metamaterial converter Fiber Adhesive Photonic die Vertical polish through lid Focused Ion Beam cut Fibers well seated in v-groove and butted to metamaterial converter Photonics Summit, Cadence, 6 th September 2017, San Jose CA 19

20 Fiber Array Optical coupling T.Barwicz et al. OFC 2017 Test site: 12 ports form 6 loopbacks Roundtrip includes MT connection db MT loss MT loss + Fiber to Si waveguide loss (-db) port 5-6 is polarization ref. Automated, self-aligned results TE data (raw and F-P filtered) db -2 TE spectral ripple from on-chip Fabry-Perot resonator induced by patterning imperfection. -3 TM data (raw and F-P filtered) Wavelength (um) 1.3 db peak transmission and > 100nm bandwidth Photonics Summit, Cadence, 6th September 2017, San Jose CA 20

21 Outline 1 2 Introduction Silicon Photonic Packaging Vision Fiber array Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 21

22 Compliant Polymer - Concept MT fiber ferrule butt couple Adiabatic couple to SiPh chip Ferrule lid Polymer ribbon Ferrule Parallel channel array (dense 50µm pitch 12ch TV) Polymer coupling region O, S, C, L bands compatible Couples both polarizations (TE / TM) Compliant material for CPI risk mitigation Assembly using high throughput pick n place tools 8 x 2.5µm x 0.2µm Photonics Summit, Cadence, 6 th September 2017, San Jose CA 22

23 Compliant Polymer - Concept T.Barwicz et al. OFC 2015 Plug in standard fiber MT ferrule Photonics Summit, Cadence, 6 th September 2017, San Jose CA 23

24 Resulting misalignment (µm) (um) Compliant Polymer Self alignment to chip Brut data T.Barwicz et al. ECTC 2014 ridge groove Polymer ribbon Polymer waveguides Chip waveguides Placement misalignment top left top right bottom left bottom right Photonic chip Photonic chip Sectional view (Features not to scale) Acceptable target range Intentionally Purposefully induced misalignment (um) (µm) Top view Self align to < 2µm using standard high throughput placement tools (±10µm) Photonics Summit, Cadence, 6 th September 2017, San Jose CA 24

25 Compliant Polymer Self alignment to ferrule Y.Taira et al. ECTC 2015 Micrograph of polished ferrule facet Ferrule lid 100 um Polymer ribbon backing Ferrule Polymer waveguides Selfalignment structure New design Old design Self alignment to < 2µm Photonics Summit, Cadence, 6 th September 2017, San Jose CA 25

26 Compliant Polymer Adhesive bondline control N.Boyer et al. ECTC 2016 Adhesive thickness profile Confocal Interferometry (non destructive) Top view UV light UV transparent picktip Chamfered picktip design Thicker adhesive at chip and taper edge reduces scattering. Thin adhesive in adiabatic coupling region Sectional view Photonics Summit, Cadence, 6 th September 2017, San Jose CA 26

27 Compliant Polymer Optical Coupling T.Barwicz et al. FIO to 2.6 db loss over ~100 nm bandwidth. Both polarizations / all channels. Connector pin alignment can add < 0.5 db loss. No impact from preliminary stressing with 25 cycles at -40 to 85ºC. Photonics Summit, Cadence, 6 th September 2017, San Jose CA 27

28 Outline 1 2 Introduction Silicon Photonic Packaging Vision Fiber array Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 28

29 Photonic flipchip Concept 10 μm Photonic interconnect along this edge Solder-induced self-alignment Secondary photonic die (InP) Si photonic die or wafer Photonic connection Secondary photonic die (InP) Si photonic die Si photonic die or wafer Pick and place (±10 μm), then anneal (< ±1 μm) Compatible with high-throughput microelectronic assembly low cost, scalable. Surface tension re-alignment known for decades addressing 3D accuracy and yield. Photonics Summit, Cadence, 6 th September 2017, San Jose CA 29

30 Photonic flipchip Experimental demonstration JW.Nah et al. ECTC 2015 Cross-section of stops after assembly Secondary photonic die Infrared view through assembly at anneal Pad on bottom chip Butting Lateral stop on flipped chip Pad on top chip Align stop Vertical and lateral stop on photonic die Si photonic die/wafer 10 μm 50 μm Cross-section of solder pads after assembly Secondary photonic die Si photonic die SnAg solder 10 μm Solder pads offset by design for sustained force at butting Photonics Summit, Cadence, 6 th September 2017, San Jose CA 30

31 Chip-to-chip loss (db) Photonic flipchip Optical coupling demonstration T.Barwicz al. OFC 2017 Self-aligned secondary photonic dies Solder-aligned loss with nanotaper coupler Si photonic die 0.26 Y (μm) Wavelength (μm) X (μm) 0.58 Corresponding misalignment range Silicon used as top & bottom die for convenience, but any material is possible. 1.1 db loss consistent with misalignment due to accuracy of lithographic stops. Photonics Summit, Cadence, 6 th September 2017, San Jose CA 31

32 Solder force (μn) Solder force (μn) Photonic flipchip Yield improvement Y.Martin et al. ECTC 2016/2017 Horizontal misalignment Solder forces in typical designs Lateral force 6% Plated solder thickness (μm) Vertical misalignment Tolerances with solder reservoirs 120 Lateral force 60 ~2X Plated solder thickness (μm) Composite image of advanced design with solder volume self-balancing Optical IR Sensitivity to solder-volume as a yield-limiting mechanism Working on solder volume self-balancing through integrated reservoirs Photonics Summit, Cadence, 6 th September 2017, San Jose CA 32

33 Outline 1 2 Introduction Silicon Photonic Packaging Vision Fiber array Compliant Polymer Photonic Flip Chip 6 7 Connector (pluggable) Conclusion Photonics Summit, Cadence, 6 th September 2017, San Jose CA 33

34 Connector Concept Clip design is for demo purposes. Clip is permanently attached to module. Low profile. Assembly using high throughput pick n place tools. Standard MT multi-fiber cable Demo Silicon Photonic Module with embedded connector Photonics Summit, Cadence, 6 th September 2017, San Jose CA 34

35 Connector Concept A.Janta-Polczynski et al. Photonics North 2017 System Ferrule ready to be connected clip lid Standard MT Fiber interface Optical Interface to chip Exploded view Si Ph Laminate substrate Mated Module System ferrule within latches Clip and MT interface on polymer are secured to the lid overhang Photonics Summit, Cadence, 6 th September 2017, San Jose CA 35

36 Conclusion Packaging is one of the critical keys to success Leverage microelectronic knowhow and infrastructure for photonic packaging Cost / Scalability Demonstration of (singlemode, multi-channel array) photonic assembly compatible with high-throughput microelectronic facilities Focus on 3 photonic interconnect packaging processes Parallelized fiber assembly Compliant polymer interface Solder-aligned photonic flip-chip Photonics Summit, Cadence, 6 th September 2017, San Jose CA 36

37 Team and Acknowledgement IBM Watson, NY USA Design, fabrication, analysis IBM Research - Tokyo Ribbon-ferrule assembly Outside partners Ted Lichoulas Eddie Kimbrell GlobalFoundries (former IBM) Chip manufacturing IBM Bromont C2MI Assembly, measurement Shotaro Takenobu Katsuki Suematsu Matsuhiro Iwaya Masato Shiino Photonics Summit, Cadence, 6 th September 2017, San Jose CA 37

38 Photonic flipchip Concept Thank you! Follow our progress: Through our IBM Research website Google Silicon nanophotonic packaging. IBM Packaging and Test: 38 Photonics Summit, Cadence, 6 th September 2017, San Jose CA 38