Nanium Overview. Company Presentation
|
|
- Eleanore Ginger Hill
- 5 years ago
- Views:
Transcription
1 Nanium Overview Company Presentation
2 Nanium Overview Our name and logo nano prefix of Greek origin referring to small objects ium suffix of Latin origin that includes the formation of scientific terms such as the name of elements The logo suggests a crystalline atomic structure as a unifying symbol of different resources 2
3 NANIUM s historical background NANIUM is an independent company in the semiconductor market, providing contract Assembly and Engineering Services for WLP, Packaging, Assembly & Test. Qimonda Portugal s Restructuring Plan was approved on 25th November 2009 with a new and stable shareholder structure: Tex t Tex t Portuguese State 41,06% 17,88% 41,06% Tex t
4 NANIUM s differentiated value proposition High Quality High Volume / Cost effective manufacturing High Flexibility / Fast prototyping capability Large technology diversity Complete engineering service offer World-class facilities & equipment Big projects start small
5 A world-class facility in Europe A state-of-the-art facility located in Portugal, near Porto. with > $1B cumulated investment!
6 NANIUM s overall infrastructure Labs & Engineering 200/300mm WLP & RDL Wafer test Package Assembly Final test Shipping Electrical characterization Material analysis Qualification Reliability Failure analysis Lithography Sputtering Plating Wet Etching Furnace Wafer molding Wafer thinning Ball dropping Probe test Parametric wafer test Laser repair Grinding Dicing Die attach SMT for modules Wire bonding Pick, flip & place Molding Plating Trim & form Marking Singulation Final test Burn-in Modules test Inspection systems Packing (trays, Tape & reel) Preconditioning Shipping A world-class facility for die / wafer / module level assembly, test & packaging Plus associated labs for characterization, reliability & failure analysis
7 NANIUM s Four Business Offers 1-High volume Packaging, Assembly & Test services 2-High volume 200mm / 300mm WLP & Wafer Test services Lead frame based Laminate based MCP, MCM, stacked dies SiP RDL Fan-in WLP Fan-Out WLP Wafer Test Wafer Thinning Wafer Molding Wafer Bumping Fast prototype and qualification runs Production of small series Innovative package prototypes Flexible technology diversity management Technology transfer Package development Test engineering & development Quality & Supply Chain Management consulting services Laboratories 3-Flexible pilot line for Packaging, Test & SMT 4-Turnkey engineering services Package & Test development, Lab and Consulting
8 Lead frame based Laminate based MCP, MCM, stacked dies SiP 1 - High volume Packaging, Assembly & Test services
9 Packaging, Assembly & Test services Lead frames & Laminates Package portfolio include Leadframe-based TSOP, QFP, QFN, SO Laminate-based LGA, BGA Interconnections available Wire-Bonding, Flip-Chip
10 Packaging, Assembly & Test services Multi Chip Packages (MCP) / Micromodules NANIUM also has extensive volume manufacturing experience of multi-chip memory packages, combining Wafer-level RDL techniques (redistribution) with multiple die stacking in a package. NANIUM s large technology portfolio combined with its strong engineering knowhow and experience enable new innovative MCP/SiP configurations (stacked, sideby-side, MEMS, Sensors, cpv, HB-LED Packages) SiP / MCM Complex MCP Micromodules / Chip on board COB MEMS & Sensor packages
11 2 - High volume 200mm / 300mm WLP & Wafer Test services RDL Fan-in WLP Fan-Out WLP Wafer Test Wafer Thinning Wafer Molding Wafer Bumping
12 Sample for a product: New Packaging Technologies Wafer Level Packaging (WLP) 200mm / 300mm Fan-in WLCSP Fan-in WLCSP Technology Features Bare-die handling Full wafer ball-apply Assembly of WLP on DIMM PCB & over-mold (Wafer Level Package on Board) Pitch mm Ball size Standard component test & burn-in (FBGA like) Si Chip Si Chip Metal II Photo-IMID RDL-ISOI RDL-metal traces RDL-ISOII Solder ball bond pad WLP WLPoB NANIUM has long time experience in WLCSP development and manufacturing memory applications WLCSP services offer include: RDL / UBM / Balling / Test + other BE steps (such as marking, singulation and tape&reel) 12
13 New Packaging Technology 300mm Fan-Out WLP (FO-WLP) Reconstitution Re-building of artificial wafer of dies and mold compound Molded artificial wafer is the starting point for thin-film technology Redistribution Using thin-film-technologies for application of dielectric, metal line and solder stop Ball Apply and Singulation Standard BGA-Ball apply Test, Mark, Scan, Pack Standard or wafer level based test flow
14 First ever 300mm Fan-out WLP realization! (1/2) Based on Infineon s ewlb technology Production line ramping in high volume production by Q3-2010!
15 First ever 300mm Fan-out WLP realization! (2/2) 300mm Recon-Wafer (chip backside) Overmolded (before backside grinding) 300mm Recon-Wafer (active chip side) Solder Spheres placed Epoxy mold compound Recon-Wafer = Chip Carrier
16 Fast prototype and qualification runs Production of small series Innovative package prototypes 3 - Flexible pilot line for Packaging, Test & SMT Flexible technology diversity management Technology transfer
17 Flexible pilot line for Packaging, Test & SMT Modules & Micro-modules NANIUM is set to become a one-stop-shop for module design, qualification and manufacturing across a very wide range of applications as the company is based on A strong experience of volume manufacturing of memory modules A wide internal technology portfolio (including SMT mounting) High engineering skills NANIUM s services include Fast prototype and Qualification runs Production of small series Innovative package prototypes: SiP, MCM, HB-LED, MEMS, sensors, c-pv Technology transfer and Flexible technology diversity management
18 Flexible pilot line for Packaging, Test & SMT From concept to production ramp-up New package Technologies Fast Prototyping Proof of concept, design validation, customer sampling Qualification runs Electrical characterization, reliability stress tests Packaged IC or module Production of small series Flow enhancement, yield tracking, early failure rate analysis NANIUM has long experience in transferring new package technologies in HVM to third-parties in Asia! Technology transfer To industrial partner
19 4 - Turnkey engineering services Package / test development, Lab & Consulting Package development Test engineering & development Quality & Supply Chain Management consulting services Laboratories
20 Turnkey engineering services for Package & Test development, Lab and Consulting Complete semiconductor Business line Marketing IC/system Design Product Engineering Test Engineering Supply Chain Management Quality Engineering Package design Definition of production flow Co-design & thermomechanical modeling Test program development DfM, DfT Yield tracking Electrical characterization Choice and follow-up of contracted partners Production planning Follow-up of production quality and reliability Handling of customer returns Failure analysis Root cause tracking Containment plan Qualification NANIUM s Turnkey engineering services Rely on NANIUM s full engineering services for part or all of your business line engineering tasks and focus on your value adding priorities: marketing and IC / System design!
21 Thank you for your attention NANIUM S.A. Avenida 1 de Maio Vila do Conde Portugal
System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb)
System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) Steffen Kröhnert, José Campos, Eoin O Toole NANIUM S.A., Vila do Conde, Portugal Outline Short Company Overview NANIUM Introduction
More informationIMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY
IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY B. Rogers, C. Scanlan, and T. Olson Deca Technologies, Inc. Tempe, AZ USA boyd.rogers@decatechnologies.com ABSTRACT Fan-Out Wafer-Level Packaging
More informationChips Face-up Panelization Approach For Fan-out Packaging
Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips
More informationWire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017
Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization
More informationChallenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012
Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer
More informationIME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum
IME Technical Proposal High Density FOWLP for Mobile Applications 22 April 2014 Packaging driver for portable / mobile applications Key drivers/needs Smaller form-factor lower profile, substrate-less Higher
More informationCost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology
Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology by Meenakshi Prashant, Seung Wook Yoon, Yaojian LIN and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
More information3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan
3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio Contents Package trends and roadmap update Advanced technology update Fine
More informationInnovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA
Innovative Advanced Wafer Level Packaging with Smart Manufacturing Solutions YOON Seung Wook, Ph.D MBA Director, STATS ChipPAC Outline 1 2 3 Introduction of Smart Manufacturing & Wafer Level Packaging
More informationSEMI Networking Day 2013 Rudolph Corporate Introduction
SEMI Networking Day 2013 Rudolph Corporate Introduction Rudolph Technologies: Corporate Profile Business: Semiconductor capital equipment company dedicated exclusively to inspection, advanced packaging
More information3D Integrated ewlb /FO-WLP Technology for PoP & SiP
3D Integrated ewlb /FO-WLP Technology for PoP & SiP by Yaojian Lin, Chen Kang, Linda Chua, Won Kyung Choi and *Seung Wook Yoon STATS ChipPAC Pte Ltd. 5 Yishun Street 23, Singapore 768442 *STATS ChipPAC
More informationFlexible Carrier Enables Automated Test-in-Tray. Dr. Tom Di Stefano Centipede Systems
Flexible Carrier Enables Automated Test-in-Tray Dr. Tom Di Stefano Centipede Systems Running in Parallel TnT is limited only by Test Electronics Parallel test at fixed DUT positions Parallel to 256+ DUTS
More informationHot Chips: Stacking Tutorial
Hot Chips: Stacking Tutorial Choon Lee Technology HQ, Amkor Enabling a Microelectronic World Mobile Phone Technology Change Feature Phone Smartphone Smartphones as a Percentage of All Phones Source : The
More informationSemiconductor IC Packaging Technology Challenges: The Next Five Years
SPAY025 May 2006 White Paper Mario A. Bolanos, Director Semiconductor Group Packaging Technology Development, Texas Instruments In the era of communications and entertainment, growth of consumer electronics
More informationSystem in Package: Identified Technology Needs from the 2004 inemi Roadmap
System in Package: Identified Technology Needs from the 2004 inemi Roadmap James Mark Bird Amkor Technology Inc System in package (SiP) technology has grown significantly in the past several years. It
More informationBoard Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages
Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages by Seng Guan Chow, Yaojian Lin, Bernard Adams * and Seung Wook Yoon** STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
More informationClose supply chain collaboration enables easy implementation of chip embedded power SiP
Close supply chain collaboration enables easy implementation of chip embedded power SiP Gerald Weidinger, R&D Project Leader, AT&S AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13
More informationInnovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level ewlb Technology
Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level ewlb Technology Jacinta Aman Lim, Vinayak Pandey* STATS ChipPAC Inc. 46429 Landing Parkway, Fremont, CA 94538, USA *STATS ChipPAC
More informationThin Wafers Bonding & Processing
Thin Wafers Bonding & Processing A market perspective 2012 Why New Handling Technologies Consumer electronics is today a big driver for smaller, higher performing & lower cost device configurations. These
More information3D-WLCSP Package Technology: Processing and Reliability Characterization
3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging
More informationThales vision & needs in advanced packaging for high end applications
Thales vision & needs in advanced packaging for high end applications M. Brizoux, A. Lecavelier Thales Global Services / Group Industry Chemnitzer Seminar June 23 th -24 th, 2015 Fraunhofer ENAS - Packaging
More informationChip Packaging for Wearables Choosing the Lowest Cost Package
Chip Packaging for Wearables Choosing the Lowest Cost Package Alan Palesko alanp@savansys.com (512) 402-9943 www.savansys.com Slide - 1 Agenda Introduction Wearable Requirements Packaging Technologies
More informationForschung für die Elektroniksysteme von morgen
Forschung für die Elektroniksysteme von morgen R. Aschenbrenner Outline Trends in Advanced Packaging Was ist Panel Level Packaging Embedding für Fan Out Embedding für LP Beispiele Trend on ICs and Packages
More informationCopyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply
Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics
More informationFan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution
Fan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution by Jacinta Aman Lim and Vinayak Pandey, STATS ChipPAC, Inc. Aung Kyaw Oo, Andy Yong, STATS ChipPAC Pte. Ltd. Originally published
More informationFailure Modes in Wire bonded and Flip Chip Packages
Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization
More informationSEMI MEMS Tech Seminar (Sept 26, Cornaredo, Italy)
SEMI MEMS Tech Seminar (Sept 26, 2013 - Cornaredo, Italy) Opportunities of Wafer Level Embedded Technologies for MEMS Devices T. Braun ( 1 ), K.-F. Becker ( 1 ), R. Kahle ( 2 ), V. Bader ( 1 ), S. Voges
More informationGlass Carrier for Fan Out Panel Level Package
January 25, 2018 NEWS RELEASE Development of HRDP TM Material for Formation of Ultra-Fine Circuits with Glass Carrier for Fan Out Panel Level Package - Aiming for mass production in collaboration with
More informationRF System in Packages using Integrated Passive Devices
RF System in Packages using Integrated Passive Devices by Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn STATS ChipPAC 1711 W. Greentree Drive, Suite #117, Tempe, AZ 85284, USA Tel: 480-222-1722
More informationRoundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit
Roundtable 3DIC & TSV: Ready for HVM? European 3D TSV Summit Infineon VTI Xilinx Synopsys Micron CEA LETI 2013 Yann Guillou Business Development Manager Lionel Cadix Market & Technology Analyst, Advanced
More informationBridging Supply Chain Gap for Exempt High-Reliability OEM s
Bridging Supply Chain Gap for Exempt High-Reliability OEM s Hal Rotchadl hrotchadl@premiers2.com www.premiers2.com Premier Semiconductor Services Tempe, AZ RoHS exempt high reliability OEMs breathed a
More informationChapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
More informationChallenges for Embedded Device Technologies for Package Level Integration
Challenges for Embedded Device Technologies for Package Level Integration Kevin Cannon, Steve Riches Tribus-D Ltd Guangbin Dou, Andrew Holmes Imperial College London Embedded Die Technology IMAPS-UK/NMI
More information9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :
9 rue Alfred Kastler - BP 10748-44307 Nantes Cedex 3 - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr February 2012 - Version 1 Written by: Romain FRAUX DISCLAIMER
More information"ewlb Technology: Advanced Semiconductor Packaging Solutions"
"ewlb Technology: Advanced Semiconductor Packaging Solutions" by Sharma Gaurav@, S.W. Yoon, Yap Yok Mian, Shanmugam Karthik, Yaojian Lin, Pandi C. Marimuthu and Yeong J. Lee* STATS ChipPAC Ltd. 5 Yishun
More informationNovel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima
Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.
More informationKGC SCIENTIFIC Making of a Chip
KGC SCIENTIFIC www.kgcscientific.com Making of a Chip FROM THE SAND TO THE PACKAGE, A DIAGRAM TO UNDERSTAND HOW CPU IS MADE? Sand CPU CHAIN ANALYSIS OF SEMICONDUCTOR Material for manufacturing process
More informationDesign for Flip-Chip and Chip-Size Package Technology
Design for Flip-Chip and Chip-Size Package Technology Vern Solberg Solberg Technology Consulting Madison, Wisconsin Abstract As new generations of electronic products emerge they often surpass the capability
More informationPanel Discussion: Advanced Packaging
Dr. Steve Bezuk Senior Director IC Packaging Engineering Qualcomm Technologies, Inc. Panel Discussion: Advanced Packaging PAGE 1 Technical Challenges of Packaging (Mobile Focus) Materials Die materials
More informationDesign and Assembly Process Implementation of 3D Components
IPC-7091 Design and Assembly Process Implementation of 3D Components Developed by the 3-D Electronic Packages Subcommittee (B-11) of the Packaged Electronic Components Committee (B-10) of IPC Users of
More informationYOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT
YOUR Strategic TECHNOLOGY PARTNER Wafer Back-End OPTO PACKAGING PROCESS DEVELOPMENT CONCEPT FLIP CHIP PROTOTYping ENGINEERING TESTING SMT PRODUCTION CHIP ON BOARD SUPPLY CHAIN MANAGEMENT Next Level 0f
More informationFlip Chip - Integrated In A Standard SMT Process
Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical
More informationFRAUNHOFER INSTITUTE FOR RELIABILITY AND MICROINTEGRATION IZM DEPARTMENT WAFER LEVEL SYSTEM INTEGRATION BERLIN
FRAUNHOFER INSTITUTE FOR RELIABILITY AND MICROINTEGRATION IZM DEPARTMENT WAFER LEVEL SYSTEM INTEGRATION BERLIN WAFER LEVEL SYSTEM INTEGRATION ELECTRONIC PACKAGING AT FRAUNHOFER IZM The Fraunhofer Institute
More informationDevelopment of Next-Generation ewlb Packaging
Development of Next-Generation ewlb Packaging by Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu and *Rajendra Pendse STATS ChipPAC Singapore *Fremont, California USA Ganesh V. P, Andreas Bahr and
More informationAdvanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation
Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes Jason Chou and Sze Pei Lim Indium Corporation Agenda Company introduction Semiconductor assembly roadmap challenges Fine
More information3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014
3D Wirebondless IGBT Module for High Power Applications Dr. Ziyang GAO Jun. 20, 2014 1 1 Outline Background Information Technology Development Trend Technical Challenges ASTRI s Solutions Concluding Remarks
More informationNext Generation ewlb (embedded Wafer Level BGA) Packaging
Next Generation ewlb (embedded Wafer Level BGA) Packaging by Meenakshi Prashant, Kai Liu, Seung Wook Yoon Yonggang Jin, Xavier Baraton, S. W. Yoon*, Yaojian Lin*, Pandi C. Marimuthu*, V. P. Ganesh**, Thorsten
More informationUltra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes
Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and
More informationAdvancements In Packaging Technology Driven By Global Market Return. M. G. Todd
Advancements In Packaging Technology Driven By Global Market Return M. G. Todd Electronic Materials, Henkel Corporation, Irvine, California 92618, USA Recently, the focus of attention in the IC packaging
More informationSemiconductor Packaging and Assembly 2002 Review and Outlook
Gartner Dataquest Alert Semiconductor Packaging and Assembly 2002 Review and Outlook During 2002, the industry continued slow growth in unit volumes after bottoming out in September 2001. After a hearty
More informationThe Packaging and Reliability Qualification of MEMS Resonator Devices
The Packaging and Reliability Qualification of MEMS Resonator Devices Pavan Gupta Vice President, Operations Yin-Chen Lu, Preston Galle Quartz and MEMS Oscillators source: www.ecliptek.com Quartz Oscillators:
More informationSilicon Wafer Processing PAKAGING AND TEST
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
More informationFLIP CHIP CHIP ON BOARD SMT ENGINEERING OPTO PACKAGING SUPPLY CHAIN MANAGEMENT TESTING YOUR INNOVATIVE TECHNOLOGY PARTNER PRODUCTION CONCEPT
YOUR INNOVATIVE TECHNOLOGY PARTNER CHIP ON BOARD OPTO PACKAGING PROCESS DEVELOPMENT CONCEPT FLIP CHIP ENGINEERING TESTING PRODUCTION SMT SUPPLY CHAIN MANAGEMENT PROTOTYPES HIGH-PRECISION ASSEMBLY OF MICRO-
More informationPackage Solutions and Innovations
Package Solutions and Innovations with Compression Molding IEEE SVC CPMT Aug 2015 Presented by C.H. Ang Towa USA Company Profile www.cpmt.org/scv 1 Corporate Overview Company: Towa Corp., Kyoto Japan Established:
More informationLED Die Attach Selection Considerations
LED Die Attach Selection Considerations Gyan Dutt & Ravi Bhatkal Alpha, An Alent plc Company Abstract Die attach material plays a key role in performance and reliability of mid, high and super-high power
More informationForecast of Used Equipment Market Based on Demand & Supply
Forecast of Used Equipment Market Based on Demand & Supply 2013. 06. 05 Thomas LEE Ⅰ. Market Introduction 300 200 150 _ Wafer Demand by Devices Type and Used Equipment Targets 20 to 0.13 0.13 to 0.5 >
More informationFanout Flipchip ewlb (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solution
Fanout Flipchip ewlb (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solution by Seung Wook Yoon,*Patrick Tang, **Roger Emigh, Yaojian Lin, Pandi C. Marimuthu, and *Raj Pendse STATS
More informationGraser User Conference Only
2.5D/3D Design Solution Eric Chen & Scott Liu 31/Oct/2014 Roadmap data is provided for informational purposes only and does not represent a commitment to deliver any of the features or functionality discussed
More informationDefining The Future Through Partnerships
v4 May 10, 2018 Agenda 1. About Us 2. Business Units 3. Customers 4. Quality 5. Markets & Applications 6. Team 7. Value Proposition The Valingro Group Valingro builds Businesses that transcends time Presence
More informationQuality Starts With Me
1 DAEWON COMPANY INTRODUCE DAEWON COMPANY INTRODUCE 2 Quality Starts With Me ABOUT DAEWON Daewon has founded in 1975 and has grown into a leading supplier of plastic Extrusion and injection molded products
More informationBasic PCB Level Assembly Process Methodology for 3D Package-on-Package
Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be
More informationWafer Level Chip Scale Package (WLCSP)
Freescale Semiconductor, Inc. Application Note Document Number: AN3846 Rev. 4.0, 8/2015 Wafer Level Chip Scale Package (WLCSP) 1 Introduction This application note provides guidelines for the handling
More informationFABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION
FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION NCCAVS Joint Users Group Technical Symposium San Jose, June 7 th, 2017 Markus Arendt, SÜSS MicroTec
More information3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack
1 3D & 2½D Test Challenges Getting to Known Good Die & Known Good Stack Advantest Corporation 2 The final yield Any Multi-die Product Must Consider the Accumulated Yield Assume Test Can Provide 99% Die
More informationDie Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.
Die Attach Materials Die Attach G, TECH. 2U. TECHNICAL R&D DIV. 2 Topics 3 What it is X 5,000 X 10,000 X 50,000 Si Chip Au Plating Substrate Ag Resin 4 Current Products Characteristics H9890-6A H9890-6S
More informationFOR SEMICONDUCTORS 2007 EDITION
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2007 EDITION ASSEMBLY AND PACKAGING THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS
More informationDevelopment of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology
Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology by J. Osenbach 1, S. Emerich1, L. Golick1, S. Cate 2, M. Chan3, S.W. Yoon 3, Y.J. Lin 4 & K. Wong 5, 1LSI Corporation
More informationRecommendation for Handling and Assembly of Infineon Hallsensor PG-SSO Packages
Recommendation for Handling and Assembly of Infineon Hallsensor PG-SSO Packages Additional Information DS4, August 2012 Edition 2012-08-06 Published by Infineon Technologies AG 81726 Munich, Germany 2012
More informationAN Handling and processing of sawn wafers on UV dicing tape. Document information. Sawn wafers, UV dicing tape, handling and processing
Handling and processing of sawn wafers on UV dicing tape Rev. 2.0 13 January 2009 Application note Document information Info Keywords Abstract Content Sawn wafers, UV dicing tape, handling and processing
More informationNew Technology for High-Density LSI Mounting in Consumer Products
New Technology for High-Density Mounting in Consumer Products V Hidehiko Kira V Akira Takashima V Yukio Ozaki (Manuscript received May 29, 2006) The ongoing trend toward downsizing and the growing sophistication
More informationIC Integrated Manufacturing Outsourcing Solution
IC Integrated Manufacturing Outsourcing Solution Integrated One-Stop Service Mature and Low Cost Loop for IC Manufacturing Taiwan s Comprehensive Resources Fast and Easy Engagement to Our Solution Professional
More informationMobile Device Passive Integration from Wafer Process
Mobile Device Passive Integration from Wafer Process Kai Liu, YongTaek Lee, HyunTai Kim, and MaPhooPwint Hlaing STATS ChipPAC, Inc. 1711 West Greentree, Suite 117, Tempe, Arizona 85284, USA Tel: 48-222-17
More informationAPPLICATION NOTE 1891 Understanding the Basics of the Wafer-Level Chip-Scale Package (WL-CSP)
Maxim > App Notes > GENERAL ENGINEERING TOPICS PROTOTYPING AND PC BOARD LAYOUT WIRELESS, RF, AND CABLE Keywords: chip scale package, flip chip, CSP, UCSP, U-CSP, BGA, WLCSP May 01, 2008 APPLICATION NOTE
More informationDevelopment of System in Package
Development of System in Package In recent years, there has been a demand to offer increasingly enhanced performance for a SiP that implements downsized and lower-profile chips at lower cost. This article
More informationRecent Advances in Die Attach Film
Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The
More informationEncapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )
Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong
More informationLow Cost Wafer Bumping of GaAs Wafers
Low Cost Wafer Bumping of GaAs Wafers Andrew Strandjord, Thorsten Teutsch, Axel Scheffler, Bernd Otto, and Jing Li Pac Tech USA - Packaging Technologies, Inc. Santa Clara, CA USA 95050 408-588-1925 Abstract
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More informationInnovative Substrate Technologies in the Era of IoTs
Innovative Substrate Technologies in the Era of IoTs Dyi- Chung Hu 胡迪群 September 4, 2015 Unimicron Contents Introduction Substrate Technology - Evolution Substrate Technology - Revolution Glass substrate
More informationALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY
ALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY Herbert J. Neuhaus, Ph.D., and Charles E. Bauer, Ph.D. TechLead Corporation Portland, OR, USA herb.neuhaus@techleadcorp.com ABSTRACT Solder
More informationEPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS
As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic
More informationSimulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging
Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging Wei Sun, W.H. Zhu, Kriangsak Sae Le and H.B. Tan United Test
More informationElectronic Costing & Technology Experts
Electronic Costing & Technology Experts 21 rue la Nouë Bras de Fer 44200 Nantes France Phone : +33 (0) 240 180 916 email : info@systemplus.fr www.systemplus.fr May 2013 Version 1 Written by Romain Fraux
More informationA New Company & Approach In MEMS Semiconductor Materials & Engineering Services
A New Company & Approach In MEMS Semiconductor Materials & Engineering Services www.ubotic.com Semi Networking Day Italy Founded & Location Founded in 2009 Hong Kong & Dongguan, China Company Background
More informationGreat Team Backend Foundry, Inc. ltd.com
Great Team Backend Foundry, Inc. www.gtbf ltd.com 1 A leader of semiconductor packaging and tes?ng services, specialized in power management, small signal, discrete and control ICs packages. 2 Date of
More informationSimulation of Embedded Components in PCB Environment and Verification of Board Reliability
Simulation of Embedded Components in PCB Environment and Verification of Board Reliability J. Stahr, M. Morianz AT&S Leoben, Austria M. Brizoux, A. Grivon, W. Maia Thales Global Services Meudon-la-Forêt,
More informationEnabling Technology in Thin Wafer Dicing
Enabling Technology in Thin Wafer Dicing Jeroen van Borkulo, Rogier Evertsen, Rene Hendriks, ALSI, platinawerf 2G, 6641TL Beuningen Netherlands Abstract Driven by IC packaging and performance requirements,
More informationInvestor presentation 24 April 2013
Investor presentation 24 April 2013 2009 ASM Proprietary Information Safe Harbor Statements All matters discussed in this business and strategy update, except for any historical data, are forward-looking
More informationEffects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages
Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages Bhavesh Varia 1, Xuejun Fan 1, 2, Qiang Han 2 1 Department of Mechanical Engineering Lamar
More informationNSOP Reduction for QFN RFIC Packages
NSOP Reduction for QFN RFIC Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, CA mbora@psemi.com Abstract Wire bonded packages using conventional copper leadframe have been used in industry for
More informationPower Electronics Packaging Solutions for Device Junction Temperature over 220 o C
EPRC 12 Project Proposal Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C 15 th August 2012 Page 1 Motivation Increased requirements of high power semiconductor device
More informationEMS Electronic Manufacturing Services Excellence in quality and reliability.
EMS Electronic Manufacturing Services Excellence in quality and reliability www.rafi.de 2 RAFI ELECTRONIC MANUFACTURING SERVICES CUSTOMER BENEFITS WE PROTECT YOUR GOOD REPUTATION RAFI is an owner-managed
More informationMTS Semiconductor Solution
MTS 0 unplanned down time Solution Lowest operating Cost Solution Energy saving Solution Equipment Fine Pitch and UPH Upgrade solution Quality & Yield Improvement Solution Reliability Enhancement Solution
More informationRecent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3)
Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3) Wei Keat Loh 1, Ron Kulterman 2, Haley Fu 3, Masahiro Tsuriya 3 1 Intel Technology Sdn. Bhd.
More informationEmbedding Passive and Active Components: PCB Design and Fabrication Process Variations
Embedding Passive and Active Components: PCB Design and Fabrication Process Variations Vern Solberg Solberg Technical Consulting Saratoga, California USA Abstract Embedding components within the PC board
More informationHYPRES. Hypres MCM Process Design Rules 04/12/2016
HYPRES Hypres MCM Process Design Rules 04/12/2016 Direct all inquiries, questions, comments and suggestions concerning these design rules and/or HYPRES fabrication to: Daniel T. Yohannes Tel. (914) 592-1190
More informationTSV Interposer Process Flow with IME 300mm Facilities
TSV Interposer Process Flow with IME 300mm Facilities Property of Institute of Microelectronics (IME)-Singapore August 17, 2012 Outline 1. TSV interposer (TSI) cross sectional schematic TSI with BEOL,
More informationNondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab
Nondestructive Internal Inspection The World s Leading Acoustic Micro Imaging Lab Unmatched Capabilities and Extensive Expertise At Your Service SonoLab, a division of Sonoscan, is the world s largest
More informationCopper Wire Packaging Reliability for Automotive and High Voltage
Copper Wire Packaging Reliability for Automotive and High Voltage Tu Anh Tran AMPG Package Technology Manager Aug.11.2015 TM External Use Agenda New Automotive Environments Wire Bond Interconnect Selection
More information